JPS5544272A - Voltage-pulse width conversion circuit - Google Patents

Voltage-pulse width conversion circuit

Info

Publication number
JPS5544272A
JPS5544272A JP11769378A JP11769378A JPS5544272A JP S5544272 A JPS5544272 A JP S5544272A JP 11769378 A JP11769378 A JP 11769378A JP 11769378 A JP11769378 A JP 11769378A JP S5544272 A JPS5544272 A JP S5544272A
Authority
JP
Japan
Prior art keywords
pulse width
terminal
voltage
time constant
conversion circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11769378A
Other languages
Japanese (ja)
Inventor
Katsumi Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11769378A priority Critical patent/JPS5544272A/en
Publication of JPS5544272A publication Critical patent/JPS5544272A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Abstract

PURPOSE: To reduce the cost by decreasing the number of pins in case of circuit integration, by making common the time constant terminals for the pulse width setting constituting the voltage-pulse width conversion circuit, with the input terminals for the pulse width control voltage.
CONSTITUTION: The trigger terminal 21 is connected to the gate of FET element 22 being the switching element, and the constant voltage souce 23 is connected to the drain of the element 22. Further, the time constant terminal 24 is connected to the source of the element 22, and terminal 24 is grounded via the capacitor 25. Further, the terminal 24 is connected to the input terminal 27 for pulse width control voltage and to the output terminal 29 in series with the inverter 28. Thus, the output pulse different in the pulse width is produced corresponding to the level of the input voltage, but since the time constant terminal 24 setting the pulse width and the pulse width control voltage input terminal 27 are made common, the number of pins can be less.
COPYRIGHT: (C)1980,JPO&Japio
JP11769378A 1978-09-25 1978-09-25 Voltage-pulse width conversion circuit Pending JPS5544272A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11769378A JPS5544272A (en) 1978-09-25 1978-09-25 Voltage-pulse width conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11769378A JPS5544272A (en) 1978-09-25 1978-09-25 Voltage-pulse width conversion circuit

Publications (1)

Publication Number Publication Date
JPS5544272A true JPS5544272A (en) 1980-03-28

Family

ID=14717951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11769378A Pending JPS5544272A (en) 1978-09-25 1978-09-25 Voltage-pulse width conversion circuit

Country Status (1)

Country Link
JP (1) JPS5544272A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6166284U (en) * 1984-10-05 1986-05-07
JPS6166283U (en) * 1984-10-05 1986-05-07

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6166284U (en) * 1984-10-05 1986-05-07
JPS6166283U (en) * 1984-10-05 1986-05-07

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