JP3396555B2 - Semiconductor pump circuit - Google Patents
Semiconductor pump circuitInfo
- Publication number
- JP3396555B2 JP3396555B2 JP05687895A JP5687895A JP3396555B2 JP 3396555 B2 JP3396555 B2 JP 3396555B2 JP 05687895 A JP05687895 A JP 05687895A JP 5687895 A JP5687895 A JP 5687895A JP 3396555 B2 JP3396555 B2 JP 3396555B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- switch
- power supply
- clocked inverter
- boosted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Semiconductor Integrated Circuits (AREA)
- Dc-Dc Converters (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体ポンプ回路に関
する。FIELD OF THE INVENTION The present invention relates to semiconductor pump circuits.
【０００２】[0002]
【従来の技術】従来より、入力信号をトグルさせて電源
より電流をくみ出し、出力電位を電源電圧より高い電位
とするようなポンプ回路が数多く知られてきた。最近で
は、ドライバー側トランジスタのゲートに３Ｖｃｃ近い
電位を与えるようなＤｏｕｂｌｅ ｂｏｏｓｔｅｄ ｌ
ｅｂｅｌ ｇｅｎｅｒａｔｏｒのついたポンプ回路など
が知られ、より高い昇圧電位を得ることができるように
なっている。2. Description of the Related Art Heretofore, many pump circuits have been known which toggle an input signal to draw out a current from a power supply to make an output potential higher than a power supply voltage. Recently, a double boosted transistor which gives a potential close to 3 Vcc to the gate of a driver side transistor has been recently developed.
A pump circuit with an ebel generator is known, and a higher boosted potential can be obtained.
【０００３】しかし、これらのポンプ回路は、図７に示
すように、電源Ｖｃｃから出力電位に電流を流すために
大量の消費電流を必要とする。高い昇圧電位を得れば得
るほど、消費電流の問題は重要となってきていた。However, as shown in FIG. 7, these pump circuits require a large amount of current consumption in order to pass a current from the power supply Vcc to the output potential. As the higher boosted potential is obtained, the problem of current consumption has become more important.
【０００４】[0004]
【発明が解決しようとする課題】上記のように従来のポ
ンプ回路では、高い出力電位を得るために大量の電流を
消費していた。本発明の目的は、昇圧に必要な大量の電
流を軽減することにある。As described above, the conventional pump circuit consumes a large amount of current in order to obtain a high output potential. An object of the present invention is to reduce a large amount of current required for boosting.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記の課題を
解決するために、次のような手段を講じた。本発明の半
導体ポンプ回路は第１に、逆相の入力信号が入る２つの
ポンプ回路が少なくとも１セットあり、電源電圧より高
い出力電位を作り、出力昇圧電位として出力するポンプ
回路において、逆相の入力信号に応じ、ＰＭＯＳトラン
ジスタにより第１の端子を充電する手段と、ＮＭＯＳト
ランジスタにより第１の端子を放電する手段と、第１の
端子を電源から遮断する手段を有する第１のクロックト
インバータと、逆相の入力信号に応じ、ＰＭＯＳトラン
ジスタにより第２の端子を充電する手段と、ＮＭＯＳト
ランジスタにより第２の端子を放電する手段と、第２の
端子を電源から遮断する手段を有し、前記第１の端子と
逆相で前記第２の端子を動作させる第２のクロックトイ
ンバータと、前記第１の端子に駆動側の端子である第３
の端子が接続され、他端子が昇圧すべき端子である第４
の端子に接続される第１の昇圧用キャパシタと、前記第
２の端子に駆動側の端子である第５の端子が接続され、
他端子が昇圧すべき端子である第６の端子に接続される
第２の昇圧用キャパシタと、前記第４の端子と電源の間
に設けられた第１のスイッチと、前記第４の端子と出力
昇圧電位の間に設けられた第２のスイッチと、前記第６
の端子と電源の間に設けられた第３のスイッチと、前記
第６の端子と出力昇圧電位の間に設けられた第４のスイ
ッチと、前記第１の端子と前記第２の端子をショートさ
せて、逆相の入力信号、あるいは入力信号から何らかの
バッファを経て作られたやはり逆相の信号を、前記第１
乃至第４のスイッチと前記第１のクロックトインバータ
及び前記第２のクロックトインバータとがともにオフし
た状態で、逆相の信号が反転する直前にショートさせる
手段とを具備する。本発明の半導体ポンプ回路は第２
に、逆相の入力信号が入る２つのポンプ回路が少なくと
も１セットあり、電源電圧より高い出力電位を作るポン
プ回路において、逆相の入力信号に応じ、ＰＭＯＳトラ
ンジスタにより第１の端子を充電する手段と、ＮＭＯＳ
トランジスタにより第１の端子を放電する手段と、第１
の端子を電源から遮断する手段を有する第１のクロック
トインバータと、逆相の入力信号に応じ、ＰＭＯＳトラ
ンジスタにより第２の端子を充電する手段と、ＮＭＯＳ
トランジスタにより第２の端子を放電する手段と、第２
の端子を電源から遮断する手段を有し、前記第１の端子
と逆相で前記第２の端子を動作させる第２のクロックト
インバータと、前記第１の端子に駆動側の端子である第
３の端子が接続され、他端子が昇圧すべき端子である第
４の端子に接続される第１の昇圧用キャパシタと、前記
第２の端子に駆動側の端子である第５の端子が接続さ
れ、他端子が昇圧すべき端子である第６の端子に接続さ
れる第２の昇圧用キャパシタと、前記第４の端子と電源
の間に設けられた第１のスイッチと、前記第４の端子と
前記第６の端子の間に設けられた第２のスイッチと、前
記第６の端子と出力昇圧電位の間に設けられた第３のス
イッチと、前記第１の端子と前記第２の端子をショート
させて、逆相の入力信号、あるいは入力信号から何らか
のバッファを経て作られたやはり逆相の信号を、前記第
1乃至第３のスイッチと前記第１のクロックトインバー
タ及び前記第２のクロックトインバータとがともにオフ
した状態で、逆相の信号が反転する直前にショートさせ
る手段とを具備する。The present invention takes the following means in order to solve the above problems. First, the semiconductor pump circuit of the present invention has at least one set of two pump circuits to which input signals of opposite phases are input, and in the pump circuit which makes an output potential higher than the power supply voltage and outputs as an output boosted potential, A first clocked inverter having means for charging the first terminal with a PMOS transistor, means for discharging the first terminal with an NMOS transistor, and means for cutting off the first terminal from a power source in accordance with an input signal; A means for charging the second terminal with a PMOS transistor, a means for discharging the second terminal with an NMOS transistor, and a means for cutting off the second terminal from a power source in accordance with an input signal of a reverse phase, A second clocked inverter that operates the second terminal in a phase opposite to that of the first terminal; and a third terminal that is a driving-side terminal for the first terminal.
The other terminal is the terminal to be boosted
A first boosting capacitor connected to the terminal of, and a fifth terminal that is a driving side terminal connected to the second terminal,
A second boost capacitor connected to the sixth terminal whose other terminal is to be boosted, a first switch provided between the fourth terminal and a power supply, and the fourth terminal The second switch provided between the output boosted potentials and the sixth switch
A third switch provided between the terminal and the power supply, a fourth switch provided between the sixth terminal and the output boosted potential, and a short circuit between the first terminal and the second terminal. Then, the reverse-phase input signal or the reverse-phase signal generated from the input signal through some buffer is used as the first signal.
A means for short-circuiting the fourth switch, the first clocked inverter, and the second clocked inverter, both of which are off, immediately before the inverted signal is inverted. The semiconductor pump circuit of the present invention is the second
There is at least one set of two pump circuits to which an input signal of opposite phase is input, and in the pump circuit which produces an output potential higher than the power supply voltage, a means for charging the first terminal with a PMOS transistor in response to the input signal of opposite phase. And NMOS
Means for discharging the first terminal by means of a transistor;
, A first clocked inverter having means for cutting off the terminal from the power source, means for charging the second terminal with a PMOS transistor in response to an input signal of opposite phase, and an NMOS
Means for discharging the second terminal by the transistor;
A second clocked inverter for operating the second terminal in a phase opposite to that of the first terminal, and a means for disconnecting the terminal from the power source, and the first terminal being a driving side terminal. The third booster capacitor is connected to the third terminal and the other terminal is coupled to the fourth terminal which is the terminal to be boosted, and the second terminal is connected to the fifth terminal which is the driving side terminal. And a second boosting capacitor whose other terminal is connected to a sixth terminal which is a terminal to be boosted, a first switch provided between the fourth terminal and a power source, and a fourth switch. A second switch provided between a terminal and the sixth terminal, a third switch provided between the sixth terminal and the output boosted potential, the first terminal and the second switch. Short the terminals and make a reverse phase input signal or input signal through some buffer. The still signals of opposite phases were, the first
The first to third switches and the first clocked inverter and the second clocked inverter are both turned off, and means for short-circuiting immediately before the inverted signal is inverted.
【０００６】[0006]
【作用】本発明では、逆相の入力信号を反転直前にショ
ートさせることにより、反転に必要な電流を１／２に軽
減し、少ない消費電流で従来と同様の昇圧効果を得るこ
とができる。In the present invention, the reverse phase input signal is short-circuited immediately before the inversion, so that the current required for the inversion can be reduced to 1/2, and the boosting effect similar to the conventional case can be obtained with a small current consumption.
【０００７】[0007]
【実施例】以下、図面を参照しながら本発明の実施例を
説明する。図１は、本発明のポンプ回路の第１の実施例
である。図１で、逆相の入力信号をＶＩＮ，／ＶＩＮと
し、昇圧電位をＯＵＴとする。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a first embodiment of the pump circuit of the present invention. In FIG. 1, the reverse-phase input signals are VIN and / VIN, and the boosted potential is OUT.
【０００８】この回路の動作を簡単に説明する。まずＶ
ＰＨＩがＬで、Ｔｒ．５がｏｆｆしているときを考え
る。ＶＩＮは、ＯＶと電源電圧Ｖｃｃの間をトグルする
が、ＶＩＮがＬからＨになると、Ｎ１はＨからＬとな
り，Ｎ２はＮ１と容量結合しているのでＨはＬとなる。The operation of this circuit will be briefly described. First V
PHI is L and Tr. Consider when 5 is off. VIN toggles between OV and the power supply voltage Vcc, but when VIN changes from L to H, N1 changes from H to L and N2 changes to H because L2 is capacitively coupled with N1.
【０００９】ＳＷ１，ＳＷ２は最初のどちらもｏｆｆし
ているが、Ｎ２がＬとなった後にＳＷ１をＨとして、Ｔ
1 をｏｎさせる。こうすることにより、電源Ｖｃｃから
Ｎ２に電流が流れ込み、それにつれてＮ２の電位はＶｃ
ｃまで上昇する。一方Ｎ１はＮ２と容量結合しているた
め、Ｎ２の上昇につれて上がりかけるが、インバータに
よりＬにおさえられる。ここでインバータＩ１のＶｓｓ
側に電流が流れる。Both SW1 and SW2 are initially off, but after N2 becomes L, SW1 is set to H and T
Turn 1 on. By doing so, a current flows from the power supply Vcc to N2, and the potential of N2 is accordingly Vc.
rise to c. On the other hand, since N1 is capacitively coupled with N2, it rises as N2 rises, but is held low by the inverter. Here, Vss of the inverter I1
Current flows to the side.
【００１０】次にＳＷ１をＬとしてＴ1 を閉じた後、Ｖ
ＩＮをＨからＬにする。Ｎ１はＬからＨとなり、Ｎ２も
Ｖｃｃから２Ｖｃｃとなる。その後ＳＷ２をＬからＨに
してＴ2 をｏｎさせると、Ｎ２から出力電位ＯＵＴに向
かって電流が流れ、ＯＵＴは昇圧される。Ｎ２もＯＵＴ
と同電位となる。[0010] After the next SW1 closed T 1 as L, V
Change IN from H to L. N1 changes from L to H, and N2 also changes from Vcc to 2Vcc. When then is on the T 2 and the SW2 from L to H, a current flows toward the output potential OUT from N2, OUT is boosted. N2 is also OUT
It becomes the same potential as.
【００１１】ＳＷ２がｏｎし、Ｎ２の電位が下がった瞬
間、Ｎ１もＶｃｃからＬに落ちようとするが、Ｎ１はイ
ンバータによりＨを維持する。このときインバータのＶ
ｃｃ側から電流が供給される。At the moment when SW2 turns on and the potential of N2 drops, N1 tries to drop from Vcc to L, but N1 maintains H by the inverter. At this time, V of the inverter
Current is supplied from the cc side.
【００１２】一方／ＶＩＮが入力する側のＮ３，Ｎ４に
ついても、上記と全く同様に動作する。以上の動作は従
来のポンプ回路と同じであるが、本発明ではＶＩＮ，／
ＶＩＮが反転する直前にクロックトインバータをｏｆｆ
し、ＶＰＨＩをＨにして、Ｎ１とＮ３をショートさせ
る。Ｎ１、Ｎ３がともに１／２Ｖｃｃとなったあとで、
ＶＰＨＩをＬとしてＮ１とＮ３を分離し、ＶＩＮ，／Ｖ
ＩＮを反転させ、クロックトインバータをｏｎさせる。On the other hand, N3 and N4 on the input side of / VIN operate in exactly the same manner as above. The above operation is the same as that of the conventional pump circuit, but in the present invention, VIN, /
The clocked inverter is turned off immediately before VIN is inverted.
Then, VPHI is set to H, and N1 and N3 are short-circuited. After N1 and N3 both become 1 / 2Vcc,
VPHI is set to L and N1 and N3 are separated, VIN, / V
IN is inverted and the clocked inverter is turned on.
【００１３】このようにすると、インバータの反転時に
流れる電流を１／２にすることができ、消費電流を軽減
することができる。また、出力電位ＯＵＴが電源電圧Ｖ
ｃｃに近いときに、消費電流低減の効果は特に顕著であ
る。In this way, the current flowing when the inverter is inverted can be halved, and the current consumption can be reduced. Further, the output potential OUT is the power supply voltage V
When it is close to cc, the effect of reducing current consumption is particularly remarkable.
【００１４】図２は、第１の実施例のポンプ回路の波形
図である。図１の説明にあったように、ＶＩＮ，／ＶＩ
Ｎは０Ｖ−Ｖｃｃの間を変動する矩形波である。各波形
のタイミングは、ＶＰＨＩはＶＩＮ，／ＶＩＮが反転す
る直前にＨになり、ＶＩＮ，／ＶＩＮが反転する前にＬ
に戻るパルス波である。また、ＳＷ１はＶＩＮがＨにな
り、Ｎ２がＬとなった後にＨとなってＴ1 をｏｎさせ
る。そして、ＶＰＨＩが立ち上がるまえにＳＷ１はＬと
なってｏｆｆする。ＳＷ２はＶＩＮがＬになり、Ｎ２が
Ｈとなった後にＨとなってＴｒ．２をｏｎさせる。そし
て、ＶＰＨＩが立ち上がるまえにＳＷ２はＬとなってｏ
ｆｆする。ＳＷ３は／ＶＩＮがＨになり、Ｎ４がＬとな
った後にＨとなってＴｒ．３をｏｎさせる。そして、Ｖ
ＰＨＩが立ち上がるまえにＳＷ３はＬとなってｏｆｆす
る。ＳＷ４は／ＶＩＮがＬになり、Ｎ４がＨとなった後
にＨとなってＴ4 をｏｎさせる。そして、ＶＰＨＩが立
ち上がるまえにＳＷ４はＬとなってｏｆｆする。なお、
ＣＬＫ，／ＣＬＫは、ＶＰＨＩがＨとなってショートが
開始するのと同時または直前にｏｆｆしてインバータを
切り、ＶＰＨＩがＬとなってショートが解除されるのと
同時、または直後にｏｎしてインバータを動作させる。
そして、出力電位であるＯＵＴは、ＳＷ２，ＳＷ４，が
開いて電流が流れる度に昇圧していく。FIG. 2 is a waveform diagram of the pump circuit of the first embodiment. As explained in FIG. 1, VIN, / VI
N is a rectangular wave varying between 0V and Vcc. As for the timing of each waveform, VPHI becomes H immediately before VIN and / VIN are inverted, and is L before VIN and / VIN are inverted.
Is a pulse wave returning to. Further, SW1 becomes H after VIN becomes H and N2 becomes L to turn on T 1 . Then, SW1 becomes L and turns off before VPHI rises. As for SW2, VIN becomes L, N2 becomes H, then becomes H, and Tr. Turn 2 on. Then, SW2 becomes L before VPHI rises.
ff SW3 becomes H after / VIN becomes H and N4 becomes L, and becomes Tr. Turn 3 on. And V
SW3 becomes L and turns off before PHI rises. SW4 is / VIN becomes L, N4 is cause on the T 4 becomes H after becoming the H. Then, SW4 becomes L and turns off before VPHI rises. In addition,
CLK and / CLK are turned off at the same time as or immediately before VPHI becomes H and a short circuit starts, and the inverter is turned off, and at the same time or immediately after VPHI becomes L and a short circuit is released. Operate the inverter.
The output potential OUT is boosted every time SW2, SW4 are opened and a current flows.
【００１５】図３に第２の実施例を示す。第２の実施例
は、第１の実施例において外部入力としていたＳＷ１〜
４を、ダイオード接続で代替したものである。この回路
でも、各クロックのタイミングや動作は第１の実施例と
同じである。ただし、出力電位ＯＵＴは、Ｎ２，Ｎ４か
らＶｔ落ちした電位までしか上昇しない。FIG. 3 shows a second embodiment. In the second embodiment, SW1 to SW1 which are external inputs in the first embodiment are used.
4 is replaced with a diode connection. Also in this circuit, the timing and operation of each clock are the same as in the first embodiment. However, the output potential OUT rises only from N2, N4 to the potential dropped by Vt.
【００１６】図４に第３の実施例を示す。第３の実施例
は第１の実施例のバリエーションであり、ＳＷ２，ＳＷ
４のタイミングは第１の実施例のそれと同じであり、動
作も同様である。FIG. 4 shows a third embodiment. The third embodiment is a variation of the first embodiment and includes SW2, SW
The timing of No. 4 is the same as that of the first embodiment, and the operation is also the same.
【００１７】図５に第４の実施例を示す。第４の実施例
は第２の実施例のバリエーションであり、動作も同様で
ある。図６に第５の実施例を示す。FIG. 5 shows a fourth embodiment. The fourth embodiment is a variation of the second embodiment and operates in the same way. FIG. 6 shows a fifth embodiment.
【００１８】第５の実施例は、逆相の信号ＶＩＮ，／Ｖ
ＩＮが入力する回路を直列に接続したものである。この
動作を簡単に説明する。ＶＩＮがＬからＨ，／ＶＩＮが
ＨからＬになると、Ｎ１，Ｎ２はＬ，Ｎ３，Ｎ４はＨと
なるから、Ｔ2 はｏｆｆし、Ｔ3 はｏｎする。そこで、
Ｎ４からＯＵＴに向かって電流が流れる。次にＶＩＮ／
ＶＩＮが反転してＶＩＮがＨからＬに，／ＶＩＮがＬか
らＨになると、Ｎ１，Ｎ２はＨ，Ｎ３，Ｎ４はＬとなる
から、Ｔ2 はｏｎし、Ｔ3 はｏｆｆする。そこで、Ｔ2
を介してＮ２よりＮ４に電流が流れる。In the fifth embodiment, opposite phase signals VIN, / V are used.
A circuit in which IN is input is connected in series. This operation will be briefly described. VIN is H from L, / VIN when changes from the H to L, N1, because N2 is L, N3, N4 becomes H, T 2 is off, T 3 is turned on. Therefore,
A current flows from N4 to OUT. Then VIN /
VIN is inverted to L from VIN is H, / VIN when becomes H from L, N1, because N2 is H, N3, N4 becomes L, T 2 is on, T 3 is turned off. So T 2
A current flows from N2 to N4 via.
【００１９】ＶＰＨＩをＨにしてＮ１とＮ３をショート
させるタイミングは上記実施例と同じで、ＶＩＮ，／Ｖ
ＩＮの反転の直前である。この実施例でも、出力電位Ｏ
ＵＴが電源電圧Ｖｃｃに近いときに、消費電流低減の効
果は特に顕著である。The timing when VPHI is set to H and N1 and N3 are short-circuited is the same as in the above-mentioned embodiment.
Immediately before the inversion of IN. Also in this embodiment, the output potential O
When UT is close to the power supply voltage Vcc, the effect of reducing current consumption is particularly remarkable.
【００２０】[0020]
【発明の効果】以上述べた様に、本発明によれば、ポン
プ回路の逆相の入力信号を反転直前にショートさせるこ
とにより、インバータで消費される電流を減少し、少な
い消費電流で従来と同じ昇圧効果を実現できる。As described above, according to the present invention, the current consumed by the inverter is reduced by short-circuiting the input signal of the opposite phase of the pump circuit immediately before the inversion, and the current consumption is reduced as compared with the conventional one. The same boosting effect can be realized.
【図１】 本発明の第１の実施例の回路図。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
【図２】 本発明の第１の実施例の波形図。FIG. 2 is a waveform diagram of the first embodiment of the present invention.
【図３】 本発明の第２の実施例の回路図。FIG. 3 is a circuit diagram of a second embodiment of the present invention.
【図４】 本発明の第３の実施例の回路図。FIG. 4 is a circuit diagram of a third embodiment of the present invention.
【図５】 本発明の第４の実施例の回路図。FIG. 5 is a circuit diagram of a fourth embodiment of the present invention.
【図６】 本発明の第５の実施例の回路図。FIG. 6 is a circuit diagram of a fifth embodiment of the present invention.
【図７】 従来技術を示す回路図。FIG. 7 is a circuit diagram showing a conventional technique.
Ｔ１〜Ｔ５…トランジスタ Ｉ１，Ｉ２…インバータ Ｎ１〜Ｎ４…ノード T1 to T5 ... Transistor I1, I2 ... Inverter N1 to N4 ... Nodes
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−105538（ＪＰ，Ａ) 特開 平６−282339（ＪＰ，Ａ) 特開 平８−102655（ＪＰ，Ａ) 特開 平９−231752（ＪＰ，Ａ) 特開 昭55−71058（ＪＰ，Ａ) 特開 昭62−61420（ＪＰ，Ａ) 特開 昭63−224665（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H02M 3/07 H01L 21/822 H01L 27/04 H03K 19/20 ─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-6-105538 (JP, A) JP-A-6-282339 (JP, A) JP-A-8-102655 (JP, A) JP-A-9- 231752 (JP, A) JP-A-55-71058 (JP, A) JP-A-62-61420 (JP, A) JP-A-63-224665 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H02M 3/07 H01L 21/822 H01L 27/04 H03K 19/20
Claims (2)
少なくとも１セットあり、電源電圧より高い出力電位を
作り、出力昇圧電位として出力するポンプ回路におい
て、 逆相の入力信号に応じ、ＰＭＯＳトランジスタにより第
１の端子を充電する手段と、ＮＭＯＳトランジスタによ
り第１の端子を放電する手段と、第１の端子を電源から
遮断する手段を有する第１のクロックトインバータと、 逆相の入力信号に応じ、ＰＭＯＳトランジスタにより第
２の端子を充電する手段と、ＮＭＯＳトランジスタによ
り第２の端子を放電する手段と、第２の端子を電源から
遮断する手段を有し、前記第１の端子と逆相で前記第２
の端子を動作させる第２のクロックトインバータと、 前記第１の端子に駆動側の端子である第３の端子が接続
され、他端子が昇圧すべき端子である第４の端子に接続
される第１の昇圧用キャパシタと、 前記第２の端子に駆動側の端子である第５の端子が接続
され、他端子が昇圧すべき端子である第６の端子に接続
される第２の昇圧用キャパシタと、 前記第４の端子と電源の間に設けられた第１のスイッチ
と、 前記第４の端子と出力昇圧電位の間に設けられた第２の
スイッチと、 前記第６の端子と電源の間に設けられた第３のスイッチ
と、 前記第６の端子と出力昇圧電位の間に設けられた第４の
スイッチと、 前記第１の端子と前記第２の端子をショートさせて、逆
相の入力信号、あるいは入力信号から何らかのバッファ
を経て作られたやはり逆相の信号を、前記第１乃至第４
のスイッチと前記第１のクロックトインバータ及び前記
第２のクロックトインバータとがともにオフした状態
で、逆相の信号が反転する直前にショートさせる手段と
を具備することを特徴とする半導体ポンプ回路。 1. Two pump circuits for receiving input signals of opposite phases are provided.
There is at least one set, and output potential higher than the power supply voltage
A pump circuit that is made and outputs as an output boosted potential
Then, according to the reverse phase input signal,
The means for charging the terminal 1 and the NMOS transistor
Means to discharge the first terminal and the first terminal from the power supply
A first clocked inverter having a means for shutting off , and a PMOS transistor for providing a first
2 means for charging the terminal and an NMOS transistor
Means to discharge the second terminal from the power source
A means for shutting off the second terminal in a phase opposite to the first terminal;
And a second clocked inverter for operating the terminal of the second terminal is connected to a third terminal which is a driving side terminal to the first terminal.
And the other terminal is connected to the fourth terminal, which is the terminal to be boosted.
The first boosting capacitor is connected to the second terminal, and the fifth terminal, which is a driving side terminal, is connected to the second terminal.
And the other terminal is connected to the sixth terminal, which is the terminal to be boosted
Second boosting capacitor, and a first switch provided between the fourth terminal and a power supply
And a second terminal provided between the fourth terminal and the output boosted potential.
A switch and a third switch provided between the sixth terminal and the power supply
And a fourth terminal provided between the sixth terminal and the output boosted potential.
Reverse the switch by shorting the first and second terminals
Phase input signal or some buffer from the input signal
The signals of the opposite phase generated through the
Switch, the first clocked inverter, and the switch
A state in which both the second clocked inverter are turned off
Then, with a means to short circuit immediately before the reverse phase signal is inverted
A semiconductor pump circuit comprising:
少なくとも１セットあり、電源電圧より高い出力電位を
作るポンプ回路において、 逆相の入力信号に応じ、ＰＭＯＳトランジスタにより第
１の端子を充電する手 段と、ＮＭＯＳトランジスタによ
り第１の端子を放電する手段と、第１の端子を電源から
遮断する手段を有する第１のクロックトインバータと、 逆相の入力信号に応じ、ＰＭＯＳトランジスタにより第
２の端子を充電する手段と、ＮＭＯＳトランジスタによ
り第２の端子を放電する手段と、第２の端子を電源から
遮断する手段を有し、前記第１の端子と逆相で前記第２
の端子を動作させる第２のクロックトインバータと、 前記第１の端子に駆動側の端子である第３の端子が接続
され、他端子が昇圧すべき端子である第４の端子に接続
される第１の昇圧用キャパシタと、 前記第２の端子に駆動側の端子である第５の端子が接続
され、他端子が昇圧すべき端子である第６の端子に接続
される第２の昇圧用キャパシタと、 前記第４の端子と電源の間に設けられた第１のスイッチ
と、 前記第４の端子と前記第６の端子の間に設けられた第２
のスイッチと、 前記第６の端子と出力昇圧電位の間に設けられた第３の
スイッチと、 前記第１の端子と前記第２の端子をショートさせて、逆
相の入力信号、あるいは入力信号から何らかのバッファ
を経て作られたやはり逆相の信号を、前記第1乃至第３
のスイッチと前記第１のクロックトインバータ及び前記
第２のクロックトインバータとがともにオフした状態
で、逆相の信号が反転する直前にショートさせる手段と
を具備することを特徴とする半導体ポンプ回路。 2. Two pump circuits for receiving input signals of opposite phases are provided.
There is at least one set, and output potential higher than the power supply voltage
In the pump circuit to be created, the first
And means to charge the first terminal, the NMOS transistor
Means to discharge the first terminal and the first terminal from the power supply
A first clocked inverter having a means for shutting off , and a PMOS transistor for providing a first
2 means for charging the terminal and an NMOS transistor
Means to discharge the second terminal from the power source
A means for shutting off the second terminal in a phase opposite to the first terminal;
And a second clocked inverter for operating the terminal of the second terminal is connected to a third terminal which is a driving side terminal to the first terminal.
And the other terminal is connected to the fourth terminal, which is the terminal to be boosted.
The first boosting capacitor is connected to the second terminal, and the fifth terminal, which is a driving side terminal, is connected to the second terminal.
And the other terminal is connected to the sixth terminal, which is the terminal to be boosted
Second boosting capacitor, and a first switch provided between the fourth terminal and a power supply
And a second terminal provided between the fourth terminal and the sixth terminal
Switch and a third switch provided between the sixth terminal and the output boosted potential.
Reverse the switch by shorting the first and second terminals
Phase input signal or some buffer from the input signal
After that, the signals of the opposite phase generated through
Switch, the first clocked inverter, and the switch
A state in which both the second clocked inverter are turned off
Then, with a means to short circuit immediately before the reverse phase signal is inverted
A semiconductor pump circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05687895A JP3396555B2 (en) | 1995-03-16 | 1995-03-16 | Semiconductor pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP05687895A JP3396555B2 (en) | 1995-03-16 | 1995-03-16 | Semiconductor pump circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08256472A JPH08256472A (en) | 1996-10-01 |
| JP3396555B2 true JP3396555B2 (en) | 2003-04-14 |
Family
ID=13039681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP05687895A Expired - Fee Related JP3396555B2 (en) | 1995-03-16 | 1995-03-16 | Semiconductor pump circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3396555B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7116154B2 (en) * | 2003-08-06 | 2006-10-03 | Spansion Llc | Low power charge pump |
-
1995
- 1995-03-16 JP JP05687895A patent/JP3396555B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08256472A (en) | 1996-10-01 |
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