JPH03154111A - Clear signal generating circuit - Google Patents

Abstract

PURPOSE:To eliminate the variance of time until a clear signal is outputted after a timing pulse is generated by providing a capacitor whose capacity is comparatively small on a transfer means. CONSTITUTION:The capacity of a capacitor 14 of a transfer circuit 202 is made considerably smaller than the capacity of a capacitor 8 of a smoothing circuit 203. A pulse signal (e) outputted from a NOR circuit 6 of a detecting circuit 201 becomes a signal for detecting a leading edge of a timing pulse (a), and a pulse signal (d) outputted from a NAND circuit 12 becomes a signal for detecting a trailing edge of the timing pulse (a). The time until a clear signal (j) is varied from '1' to '0' after the timing pulse (a) starts to be outputted is determined by a ratio of the capacity of the capacitor 8 and the capacity of the capacitor 14 and a frequency of the timing pulse (a), and it does not depend on a resistance value of a resistance 5a for constituting a delaying circuit 5, and a capacity value of a capacitor 5b. In such a way, the time until the time of generation of the clear signal from the time of generation of the timing pulse can be made constant.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a clear signal generation circuit used in a power supply section of an electric watch, etc. This invention relates to a clear signal generation circuit that operates normally when the power is turned off.

[Conventional technology]

When an electric timepiece is powered on, a voltage higher than the normal voltage is required to operate the electric timepiece immediately after the power is turned on. Therefore, circuits have been used that supply a voltage higher than the normal voltage immediately after the power is turned on, and then provide a clear signal to switch to supply the normal voltage. FIG. 3 is a circuit diagram showing a conventional clear signal generating circuit that generates such a rear signal.

In the figure, 1 is a timing pulse generation circuit, which is composed of an oscillation circuit and a frequency divider. The output of the timing pulse generation circuit 1 is given to the detection circuit 201. Detection circuit 20
1 consists of inverters 2, 3, and 4, a delay circuit 5, and a two-way NOR circuit 6. As is well known, the delay circuit 5 includes a resistor 5a and a capacitor 5b. The NOR circuit 6 has one input connected to the timing pulse generation circuit 1 through a series circuit of inverters 2 and 3 and a delay circuit 5, and the other input connected to the timing pulse generation circuit 1 through the inverter 4. 202 is a transmission circuit for transmitting the output of the detection circuit 201 to the smoothing circuit 203;
O3) transistor (hereinafter abbreviated as NMO3) 7.

The gate of the NMOS 7 is connected to the output of the NOR circuit 6, and the source is connected to the ground potential vss.

The smoothing circuit 203 includes a capacitor 8 and a resistor 9.

Capacitor 8 and resistor 9 are connected to the drain of NMOS 7 and power supply v
Connected in parallel between DD and DD.

A waveform shaping circuit 204 binarizes the output of the smoothing circuit 203. The waveform shaping circuit 204 is the inverter 10.1
Consists of one series circuit body.

Next, the operation will be explained using the waveform diagram shown in FIG. When the power is turned on, the timing pulse generation circuit 1 is supplied with the power supply voltage vDD. The output of the timing pulse generation circuit 1 becomes either "01" or "1" for some time after the power is turned on, depending on the rise characteristics of the power supply voltage vDD and the startup characteristics of the oscillation circuit.In this conventional example, As shown in FIG. 4, the timing pulse generating circuit 1 is assumed to hold "0" until the oscillation circuit starts operating after the power is turned on.

Next, when the oscillation circuit starts operating, the timing pulse generation circuit 1 outputs a timing pulse a. Timing pulse a passes through inverter 2.3 in detection circuit 201 and is delayed by delay circuit 5 constituted by resistor 5a and capacitor 5b, resulting in a pulse signal S. NOR circuit 6
A pulse signal S is input to the two manual inputs together with a pulse signal C obtained by inverting the timing pulse a by an inverter 4. N
.

The R circuit 6 outputs a pulse signal e that is "1" only when both of the two human powers are "0".

The NMOS 7 constituting the transfer circuit 202 has N.

The pulse signal e, which is the output of the R circuit 6, becomes conductive only during the period when it is "1", and the capacitor 8 of the smoothing circuit 203 is charged. This charging lowers the potential i of the negative electrode of the capacitor 8. When the pulse signal e becomes "0", the NMOS 7 becomes non-conductive. When NMOS7 becomes non-conductive, the potential i
is maintained at the potential at the time when NMOS7 becomes non-conductive. The resistor 9 is for setting the potential i to "1" when there is no pulse signal e, and therefore the time constant of the capacitor 8 and the resistor 9 must be sufficiently larger than the period of the pulse signal e. Since the capacitor 8 is gradually charged by repeating conduction/non-conduction of the NMOS 7, the potential i of the negative electrode of the capacitor 8 gradually decreases. Then, the potential i is binarized based on the threshold value vTl+ of the inverter 10 in the waveform shaping circuit 204, and becomes a clear signal j.

In other words, when the potential i is larger than the threshold value vTH, the clear signal j becomes "1°", and when it is smaller, it becomes "O".When the clear signal j becomes "0", the signal is sent from the power supply section of the electric clock to the drive section. The supplied voltage is switched from a voltage higher than the normal voltage (eg 1.55V) to a normal voltage (eg IV).

[Problem to be solved by the invention]

The conventional clear signal generation circuit is constructed as described above, and a delay circuit 4 consisting of a resistor 5a and a capacitor 5b delays the timing pulse a to create a pulse signal S, and when this pulse signal is inverted, the timing pulse a is inverted. A pulse signal e is created by performing a NOR operation with a pulse signal C, which is a signal. The resistance value of the resistor 5a and the capacitance value of the capacitor 5b vary greatly during manufacturing. Therefore,
There are problems in that the pulse width of the pulse signal e varies, the falling time of the potential i varies, the point at which the potential i becomes equal to or less than the threshold value VTH varies, and the point at which the clear signal j becomes "0" varies. Ta.

This invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a clear signal generation circuit in which the time from when a timing pulse is generated to when a clear signal is output does not vary. .

[Means to solve the problem]

The clear signal generating circuit according to the present invention includes timing pulse generating means for generating a timing pulse, and is connected to the timing pulse generating means, detects a predetermined edge of the timing pulse from the timing pulse generating means, and detects a first edge of the timing pulse from the timing pulse generating means.
edge detection means for generating a pulse, and pulse generation means connected to the edge detection means and generating a second pulse having a certain relationship with the first pulse; a first switching means connected to a potential and switched according to the level of the first pulse; one end connected to the other end of the first switching means and switched according to the level of the second pulse; a second switching means, and one electrode is at a second potential and the other electrode is connected to the other end of the first switching means;
transmission means including first capacitors of relatively small capacitance each connected to a common connection point with one end of the switching means; one electrode being at a third potential and the other electrode being at the second potential;
a smoothing means including second capacitors each having a relatively large capacity connected to the other end of the switching means; and a waveform shaping means for binarizing.

[Effect]

Since the capacitance of the first capacitor in this invention is relatively small, even if the conduction period of the first switching means changes due to a change in the pulse width of the first pulse, the first capacitor
The capacitor is instantly charged when the first switching means becomes conductive. Subsequently, when the second switching means conducts in response to the second pulse, the charge charged in the first capacitor is small and can be instantly transferred to the second capacitor, so that the pulse width of the second pulse changes. This will charge the battery until it reaches a completely balanced state.

〔Example〕

FIG. 1A is a circuit diagram showing one embodiment of a clear signal generating circuit according to the present invention. In the figure, the difference from the conventional circuit shown in FIG. 3 is that the NAND circuit 12. P channel M
OS transistor (hereinafter abbreviated as PMOS) 13. and a new capacitor 14 is provided. The NAND circuit 12 has one input connected to the delay circuit 5 and the other input connected to the output of the inverter 4. The PMOS 13 has a gate connected to the output of the NAND circuit 12 and a drain connected to the NMOS
The drain and source of 7 are connected to a capacitor 8 that constitutes a smoothing circuit 203, respectively.

Capacitor 14 is connected to power supply VDD, NMOS7 and PM0S
13 drain common connection points. Note that the capacitance of the capacitor 14 is considerably smaller than that of the capacitor 8.

Next, the operation will be explained using the waveform diagram shown in FIG. The operation in which the timing pulse generation circuit 1 outputs the timing pulse a from the time the power is turned on is the same as the conventional one. That is, the timing pulse generation circuit 1 generates the timing pulse a after a certain period of time has elapsed, as in the conventional case. As in the conventional case, the timing pulse a is delayed for a certain period of time via the inverter 2.3 and the delay circuit 5, and becomes a pulse signal N.
It is applied to one input of the OR circuit 6, and is inverted by the inverter 4 and sent as the pulse signal C to the NOR circuit 6.
is given to the other input of Therefore, the NOR circuit 6 applies the pulse signal e to the gate of the NMOS 7 as in the conventional case. The pulse signal e is a signal that detects the leading edge of the timing pulse a.

On the other hand, the pulse signal is input to one input of the NAND circuit 12.
Pulse signal C is also applied to the other input of NAND circuit 6. The NAND circuit 12 receives a pulse signal C and a pulse signal C.
Take the NAND with P and use the result as a pulse signal d
Give it to the gate of MO313. The pulse signal d is a signal obtained by detecting the trailing edge of the timing pulse a.

The NMOS 7 is conductive only during the period when the pulse signal e is "1", and the capacitor 14 is charged by the conduction of the NMOS 7. At this time, since the capacitance of the capacitor 14 is quite small, the capacitor 14 is completely charged during the period when the pulse signal e is "1". Due to this charging, the potential f of the negative electrode of the capacitor 14 decreases as shown in FIG. P
The MOS 13 is conductive only during the period when the pulse signal d is "0". When PMOS 13 becomes conductive, capacitor 14 and capacitor 8 in smoothing circuit 203 are connected in parallel. At this time, as is clear from FIG.
”, there is no period in which the pulse signal d is “0”. Therefore,
NMOS7 and PMO313 do not become conductive at the same time. By connecting capacitor 14 and capacitor 8 in parallel, most of the charge charged in capacitor 14 is discharged, and this discharged charge is transferred to capacitor 8.
is charged to. As the capacitor 14 is discharged, the potential f of the negative electrode of the capacitor 14 rises again as shown in FIG. As the capacitor 8 is charged, the potential g of the negative electrode of the capacitor 8 decreases as shown in FIG. As described above, since the capacitance value of the capacitor 14 (designated as C14) is considerably smaller than the capacitance value of the capacitor 8 (designated as C8), most of the charge charged in the capacitor 14 is instantly charged to the capacitor 8. Therefore, the potential g falls sharply.

The amount of charge charged in the capacitor 8 gradually increases as the NMOS 7 and PMOS 13 are alternately turned on and off. As the amount of charge charged in the capacitor 8 increases, the potential g of the negative electrode of the capacitor 8 gradually decreases as shown in FIG. Then, when the potential g becomes lower than the threshold value vTH of the inverter 10, the clear signal j
changes from “1” to “0”.

For example, the threshold "TI" of the inverter 10 is set to [1/2] (v
DD-vss), potential g at the start of timing pulse generation
and the potential f is v 1. The capacitor D in the initial state is set to 0. First, N.M.
When OS7 becomes conductive, the potential f becomes equal to the power supply voltage v88. Therefore, the amount of charge charged in the capacitor 14 at this time is C14 (vDD'SS). Next, NMOS7
is in a non-conductive state, and PMO 313 is in a conductive state. P.M.O.
If the potential g at the time when 813 becomes conductive is vl, then according to the law of conservation of charge, C14 (vDD - vSS) - (c + c) (V,, -V, ) -
(1) 14 8 holds true. When formula (1) is transformed, it becomes. One more time each time NMOS7. If the potential g when PMO513 becomes conductive is v2, c (V - V ) + C (V, D - Vl)1
4 DOSS 8 - (C+C) (V,, -V2) ・(3)4
8 holds true. When formula (2) is substituted into formula (3) and transformed, the following is obtained: VDD-v2 (4). Similarly, NMOS7. PMO313
If the potential g when becomes conductive is VN, then VDD-vN holds true.

For example, if you want to change the clear signal j from "1" to 0 when NMOS7 and PMO313 become conductive 10 times, VDD-VN-(1/2) < v on-v
By substituting (ss) and N-10 into equation (5) and solving, the ratio between the capacitance value C and the capacitance value c14 can be found.

As mentioned above, since the capacitance value C14 is set to a small value, the delay time in the delay circuit 5 changes due to variations in the resistance value of the resistor 5a and the capacitance value of the capacitor 5b that constitute the delay circuit 5 during manufacturing. Even if the pulse width of the pulse signal e changes, the capacitor 4 is always fully charged during the period when the pulse signal e is "1". In addition, since the capacitance value C14 is set to a small value and the amount of charge is also small, even if the delay time in the delay circuit 5 changes and the pulse width of the pulse signal d changes as described above, the pulse signal d becomes "0". During the period ``, the charge in the capacitor 4 always moves to the capacitor 8 until it reaches a completely balanced state. Therefore, after the timing pulse a starts being output, the clear signal j changes from "1" to "
The time it takes to change to 0'' is determined by the capacitance C8 of capacitor 8.
and the capacitance C14 of the capacitor 4 and the frequency of the timing pulse a, and does not depend on the resistance value of the resistor 5a constituting the delay circuit 5 and the capacitance value of the capacitor 5b. As a result, even if there are variations in the resistance value of the resistor 5a and the capacitance of the capacitor 5b, the time from when the timing pulse a starts to be output until the clear signal j changes from "1" to "0" can be kept constant. .

In the above embodiment, the switching means in the transfer circuit 202 is composed of the NMOS 7 and the PMO 813, but by changing the configuration of the detection circuit 201, the switching means can be composed only of the PMOS or only the NMO 3. Furthermore, the switching means may be constructed of other switching elements such as bipolar transistors instead of MOS transistors.

Further, in the above embodiment, the first potential is set to the ground potential v83,
Although the second potential is the power supply voltage "DD", it may be reversed.

In addition, in the above embodiment, the clear signal j changes from “1” to “0”.
We have explained the case where the clear signal j changes to “
The present invention can also be applied to the case of changing from "0" to "1".

Furthermore, in the above embodiment, the leading edge of the timing pulse a was detected to generate the pulse signal d, and the trailing edge was detected to generate the pulse signal e. The circuit configuration may be configured as shown in FIG. 1B to generate the pulse signals d and e. In other words,
By eliminating the NAND circuit 12 in FIG. 1A and passing the pulse signal e, which is the output of the NOR circuit 6, through the inverter 100 and the delay circuit 200, it is delayed by a certain period of time from the pulse signal e and is an inverted signal of the pulse signal e. A pulse signal d may also be generated.

Moreover, the pulse signals d and e are provided by NMOS7. Any signal may be used as long as it is an alternating signal that does not make the PMOS 13 conductive at the same time. An infinite number of such signals can be generated by adjusting the delay time of the delay circuit 200 shown in FIG. 1B, for example.

Further, in the above embodiment, the second and third potentials are set to the power supply VD.
Although it is set as D, different potentials may be used.

〔Effect of the invention〕

As described above, according to the present invention, the first switching means has one end connected to the first potential and is switched according to the level of the first pulse, and the other end of the first switching means has one end connected to the first potential. a second switching means connected to and switched according to the level of the second pulse;
and a first electrode having a relatively small capacitance, one electrode of which is connected to a second potential, and the other electrode of which is connected to a common connection point between the other end of the first switching means and one end of the second switching means. The transmission means includes a capacitor, and the smoothing means includes a second capacitor having a relatively large capacitance, one electrode of which is connected to the third potential, and the other electrode of which is connected to the other end of the second switching means. , even if the conduction period of the first switching means changes due to a change in the pulse width of the first pulse, the first capacitor is instantly charged by the conduction of the first switching means, and then , when the second switching means conducts in response to the second pulse, the charge in the first capacitor is instantaneously transferred to the second capacitor, and the change in the pulse width of the second pulse causes the second switching means to become conductive. Even if the conduction period of the switching means changes, the second capacitor is charged until it is fully balanced. Therefore, the time from the time the timing pulse is generated to the time the clear signal is generated is the first. Regardless of the change in the pulse width of the second pulse, the first. This is determined by the capacitance ratio of the second capacitor and the period of the timing pulse. If the capacitance ratio of the second capacitor and the cycle of the timing pulse are kept constant, there is an effect that the time from the time the timing pulse is generated to the time the clear signal is generated can be kept constant.

[Brief explanation of the drawing]

FIG. 1A is a circuit diagram showing one embodiment of the clear signal generating circuit according to the present invention, FIG. 1B is a circuit diagram showing another configuration of the detection circuit, and FIG. 2 is a circuit diagram showing the operation of the circuit shown in FIG. 1. FIG. 3 is a circuit diagram showing a conventional clear signal generation circuit, and FIG. 4 is a waveform diagram for explaining the operation of the circuit shown in FIG. 3. In the figure, 1 is a timing pulse generation circuit, 5 is a delay circuit, 6 is a NOR circuit, 7 is an NMO3°8 and 14 is a capacitor, 12 is a NAND circuit, 13 is a PMO8,10
0 is an inverter, 200 is a delay circuit, 201 is a detection circuit, 202 is a transmission circuit, 203 is a smoothing circuit, 204 is a waveform shaping circuit, vDD is a power supply voltage, and v88 is a ground potential. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Timing pulse generation means for generating a timing pulse; and edge detection means connected to the timing pulse generation means and configured to detect a predetermined edge of the timing pulse from the timing pulse generation means and generate a first pulse. , and detection means including pulse generation means connected to the edge detection means and generating a second pulse having a certain relationship with the first pulse; a first switching means that is switched according to the level of the first pulse, and a second switching means that has one end connected to the other end of the first switching means and that is switched according to the level of the second pulse. and a relatively small capacitance switch having one electrode connected to a second potential and the other electrode connected to a common connection point between the other end of the first switching means and one end of the second switching means. a smoothing means including a second capacitor having a relatively large capacitance, one electrode of which is connected to a third potential, and the other electrode of which is connected to the other end of the second switching means; A clear signal generation circuit comprising: waveform shaping means connected to the smoothing means and binarizing the output of the smoothing means depending on whether the output of the smoothing means is larger or smaller than a predetermined level.