JPH03102911A - Clock signal generating circuit - Google Patents

Abstract

PURPOSE:To prevent the inverting timing of a biphase clock signal, from being overlapped even when a power voltage is fluctuated by providing a clock generating circuit comprising a couple of gate circuits, a detection circuit and a timing adjustment circuit. CONSTITUTION:When a power voltage VDD rises and a voltage V1 reaches a threshold level of an inverter 19 as a detection circuit or over, its output goes to a low level and an output of an inverter 20 goes to a high level. Thus, transfer gates forming a timing adjustment circuit are turned off and transfer gates 13, 17 are turned on. Then an output of NOR gates 1, 2 being components of the clock generating circuit is given to one input of the gates 2, 1 via inverters 11, 12, the gate 13, inverters 15, 16 and the gate 17. As a result, the output is delivered to the other gate after trailing of the output of either gate 1, 2 and after being retarded in the inverters 11, 12 or 15, 16 and the biphase clock signal whose inverting timings are not overlapped even when the power voltage is fluctuated is generated to prevent malfunction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock signal generation circuit that generates two-phase clock signals whose output inversion timings do not overlap in time from a single-phase clock signal.

[Conventional technology] Conventionally, a clock signal that drives the internal gate of a semiconductor integrated circuit (hereinafter referred to as LSI) is external to the LSI or
It is supplied from the oscillation circuit inside the I and drives the gate inside the LSI.

By the way, in shift registers, dynamo-tsuta circuits, etc., if the rising and falling timings of the two-phase clock signals used match, it may cause malfunctions, so conventionally, two-phase clock signals are used. When a signal is generated from a single-phase clock signal, the rising and falling timings of the clock signals are made to not logically overlap.

FIG. 4 is a circuit diagram showing the configuration of a conventional clock signal generation circuit that generates such a two-phase clock signal. Clock signal CLK is supplied to one input terminal of NOR gate 1 and also to one input terminal of NOR gate 2 via inverter 3 . The output of NOR gate 2 is supplied to the other input terminal of NOR gate 1,
The other input terminal of the NOR gate 2 is supplied with the output of the NOR gate 1. NOR gate}1.2 drives resistors Rl-R2 and capacitors C1 and C2, respectively, and outputs two-phase clock signals φ and φ.

According to this circuit, as shown in FIG.
When the clock signal CLK rises, the clock signal φ, which is the output of the NOR gate 1, first falls, and then, in response to the fall of the output of the NOR gate 1, the clock signal φ, which is the output of the NOR gate 1, falls.
Clock signal φ, which is the output of R gate 2, rises.

Furthermore, when the clock signal CLK falls at timing B, the clock signal φ, which is the output of NOR gate 2, first falls, and then, in response to the fall of the output of NOR gate 2, the output of NOR gate 1 Clock signal φ rises.

This prevents the inversion timings of the two-phase clock signals from overlapping.

[Problems to be Solved by the Invention] However, in the conventional clock signal generation circuit described above, the rise time and fall time of the clock signal are determined by the ability of the transistor constituting the NOR gate as a clock driver. As shown at timings C and D in Figure 5, when the power supply voltage of the LSI changes to, for example, VDD + ΔV, the rise time and fall time of the clock signals φ and φ increase, and the clock signals φ and φ overlap. There is a problem. For this reason, conventional clock signal generation circuits have a problem in that internal circuits such as shift registers and dynamic circuits malfunction due to fluctuations in power supply voltage.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a clock signal generation circuit in which the inversion timings of two-phase clock signals do not overlap even due to fluctuations in power supply voltage.

[Means for Solving the Problems] In the clock signal generation circuit according to the present invention, one output state changes in response to input of a single-phase clock signal, and the other output state changes in accordance with the change in this output state. A clock generation circuit consisting of a pair of gate circuits that generates two-phase clock signals by changing the voltage, a detection circuit that detects the power supply voltage, and an output inversion of the two-phase clock signals according to the detection result of this detection circuit. The present invention is characterized by comprising a timing adjustment circuit that adjusts timing.

[Function] According to the present invention, the detection circuit detects the power supply voltage, and the timing adjustment circuit adjusts the output inversion timing of the two-phase clock signal based on the detection result, so even if the power supply voltage fluctuates, It is possible to prevent the output inversion timings of two-phase clock signals from overlapping, and to generate a preferable clock signal that does not cause malfunction in a circuit to which the two-phase clock signals are supplied.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing the configuration of a clock signal generation circuit according to a first embodiment of the present invention. Note that in FIG. 1, the same parts as in FIG. 4 are given the same numbers, and explanations of overlapping parts will be omitted.

In FIG. 1, NOR gates 1 and 2 are a pair of gate circuits forming a clock generation circuit.

Between the output of NOR gate 1 and one input of NOR gate 2, a series circuit of inverters 11, 12 and transfer gate 13, and transfer gate 14 are connected in parallel. Also, the output of NOR gate 2 and the NO
An inverter 15. is connected to one input of the R gate 1.
16 and the transfer gate 17, and the transfer γ gate 18 are connected in parallel. and,
These constitute a timing adjustment circuit.

On the other hand, a resistor R3,
R4 is connected in series. The potential V1 at the connection point of the resistors R3+R4 is input to the inverter 19, and the output of the inverter 19 is supplied to the gate of the transfer gate 14.18 and is also input to the inverter 20. Further, the output of the inverter 20 is supplied to the gates of the transfer T gates 13 and 17. These resistors R3 and R4 and inverters 19 and 20 constitute a detection circuit.

Next, the operation of the clock signal generation circuit according to the present embodiment, which is configured in the same way, will be explained based on the timing diagram of FIG. 2.

When the voltage VI obtained by dividing the power supply voltage vDD by the resistors R3 and R4 is below the threshold value of the inverter 19, the output of the inverter 19 is at a high level, and the inverter 20
Since the output of transfer game 1- becomes low level,
14.18 is on, transfer gate 13.17 is off, and the outputs of NOR gates 1 and 2 are connected to one input of each of NOR gates 2 and 1 via transfer gates 14 and 18, respectively.

Therefore, in this case, timing A. As shown in H, as in the conventional case, NOR gates 1 and 2 repeat the operation in which the output of either NOR gate 1 or 2 immediately rises after the output of the other falls, resulting in a two-phase system in which the inversion timings do not overlap. Clock signals φ and φ will be generated.

On the other hand, C. As shown by D, when the power supply voltage van rises to VDD+ΔV and the voltage V becomes equal to or higher than the threshold value of the inverter 19, the output of the inverter 19 becomes low level and the output of the inverter 20 becomes high level, so that the transfer gate 14 and 18 are off, transfer 1 gate 13.17 is on, and the outputs of NOR gates 1 and 2 are connected to inverter 11.12 and transfer gate 13.
Niinharta 15.18 and transferate l
7 to one input of each of the NOR gates 2 and 1, respectively.

Therefore, in this case, as shown at timings C and D in FIG. 2, the rise time and fall time of the clock signals φ and T increase, but the output of either one of the NOR gates 1. After falling, inverter 11.1
After a delay time of 2 or 15.16, this is transmitted to the other gate and its output rises. As a result, two-phase clock signals φ, φ whose inversion timings do not overlap even if the power supply voltage fluctuates are generated.

FIG. 3 is a circuit diagram of a clock signal generation circuit according to a second embodiment of the present invention.

In the above embodiment, the timing adjustment circuit was inserted between the output and input of the pair of NOR gates 1 and 2, but in this embodiment, the driving capacity can be adjusted on each output side of the NOR gates 1 and 2. Inverters 23 and 24 are provided.

That is, the output of NOR gate 1 is connected to the power supply VDD and the ground GN.
A CMOS inverter consisting of a P-channel MOS transistor 3l and an N-channel MOS transistor 32 connected in a complementary pair between P-channel MOS transistors 33 and 34 and an N-channel MOS transistor 35
, 36.

Similarly, the output of NOR gate 2 is connected to power supply VDD and ground G.
A CMOS inverter consisting of a P-channel MOS transistor 37 and an N-channel MOS transistor 38 connected in a complementary pair between the P-channel MOS transistor 39 and 40 and an N-channel MOS transistor 41
, 42.

On the other hand, a detection circuit is constituted by R5 and REI connected in series between the power supply Voo and the ground GND, and two-stage inverters 21 and 22 connected to their voltage-divided output terminals. The output of inverter 21 is input to the gate of P-channel MOS transistor 34.40, and the output of inverter 22 is input to the gate of N-channel MOS transistor 35.41.
is input/entered into the gate.

According to this circuit, the power supply voltage V. Voltage V2 obtained by dividing D
is below the threshold value of inverter 21, the output of inverter 21 is at a high level, and inverter 2? Since the output of transistors 34, 35, 4 is low level,
0.41 are all turned off, and clock signals φ and φ are driven only by transistors 31 and 32 and transistors 37 and 38, respectively.

Next, the power supply voltage vDD rises, and the voltage V2 is applied to the inverter 2.
When the threshold value of 1 is exceeded, the output of the inverter 21 becomes low level and the output of the inverter 22 becomes high level, so transistors 34, 35, 40.41 are all turned on, and the clock signals φ, φ are output from the transistor 31, respectively. to 3
6 and transistors 37 to 42.

In this case, since the driving ability is improved compared to the former, the rise time and fall time of the clock signals φ and φ are faster than before, and it is possible to prevent the clock signals φ and φ from overlapping each other. can.

This embodiment has the advantage that the pulse widths of the clock signals φ, φ can be further widened.

Note that the present invention is not limited to the embodiments described above. For example, in the above embodiment, a resistor is used as the power supply voltage detection circuit, but it is also possible to use a MOS transistor.

[Effects of the Invention] As explained above, according to the present invention, the power supply voltage is detected and the output inversion timing of the two-phase clock signal is adjusted based on the detection result, so even if the power supply voltage fluctuates, , the output inversion timings of two-phase clock signals can be prevented from overlapping, and malfunctions of shift registers, dynamic circuits, etc. can be prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a clock signal generation circuit according to a first embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the same circuit, and FIG. 3 is a clock signal generation circuit according to a second embodiment of the present invention. FIG. 4 is a circuit diagram of a conventional clock signal generation circuit, and FIG. 5 is a timing diagram showing the operation of the same circuit. 1, 2; NOR gate, 3, 11, 12,
15.18.19-24; Inverter, 13,14.
17, 18;}Transfergate, 31, 33.34,
37, 39, 40; P channel MOS} transistor, 3
2, 35.3B, 38, 41.42; N channel MOS
}Transistor, RI to R6; Resistor, Ct s C2
;capacity

Claims (1)

[Claims] (1) A pair of gate circuits that generates two-phase clock signals by changing the output state of one of them in response to input of a single-phase clock signal, and changing the output state of the other in accordance with the change in this output state. A clock generation circuit consisting of a clock generation circuit, a detection circuit that detects a power supply voltage, and a timing adjustment circuit that adjusts the output inversion timing of the two-phase clock signal according to the detection result of the detection circuit. Clock signal generation circuit.