JP3093254B2 - Clock driver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a clock driver suitable for driving a dynamic latch circuit.

[Prior Art] In a conventional semiconductor integrated circuit, a clock driver that outputs first and second clock signals having different phases from each other based on a clock signal has been configured, for example, as shown in FIG. The clock driver 61 in FIG.
It has an inverter circuit 62, a first buffer circuit 63, a first delay circuit 64, a second delay circuit 65, and a second buffer circuit 66. The first buffer circuit 63 has a clock signal and an output signal of the second delay circuit 65 as input signals, the first inverter circuit 62 has a clock signal as an input signal, and the second buffer circuit 66 has a first inverter circuit. The output signal of the circuit 62 and the output signal of the first delay circuit 64 are input signals, the first delay circuit 64 is the input signal of the output signal of the first buffer circuit 63, and the second delay circuit 65 is the input signal. The output signal of the second buffer circuit 66 is used as an input signal.

Next, the operation of the clock driver 61 in FIG. 4 will be described.

A clock signal φ1 which is an output signal of a clock driver
And φ2 are used, for example, as latch signals of a dynamic latch circuit 75 as shown in FIG.

First, the dynamic latch circuit 75 will be described.
The dynamic latch circuit 75 is composed of two N-channel type MOs.
SFETs 71 and 72 and these N-channel MOSFETs 71 and 72
And inverter circuits 73 and 74 respectively connected to the output side.

The operation of the dynamic latch circuit 75 will be described with reference to the timing chart shown in FIG. When a data signal is input to the dynamic latch circuit 75, the clock signal φ1 = "LOW (low level)" and the clock signal φ
2 = clock signal φ1 during “HIGH (high level)”
Is turned off, and the second N-channel MOSFET 71 that receives the clock signal φ2 as an input signal is turned on. Therefore, the data signal is taken into the node 76 of the dynamic latch circuit 75. . Next, when the clock signal φ1 = “HIGH” and the clock signal φ
When 2 = “LOW”, the first N-channel MOSFET 72 is turned on, and the second N-channel MOSFET 71 is turned off. Therefore, the dynamic latch circuit 75 does not accept any data signal input and takes in the node 76. The output data is output as an output signal. That is, since a period for capturing data and a period for outputting data are separately provided, it is not allowed that the clock signals φ1 and φ2 become “HIGH” at the same time.

Therefore, in the clock driver 61 shown in FIG. 4, as shown in the timing chart of FIG. 5, the clock signals φ1 and φ2 have the first and second delay circuits 64 and 65 having the same delay time value t _D , respectively. The signals delayed by the delay circuits 64 and 65 are supplied to first and second buffer circuits 63 and 66, respectively.
By making the outputs of these buffer circuits 63 and 64 clock signals φ1 and φ2, respectively, a delay circuit 64 is provided between the clock signals φ1 and φ2 as shown in FIG.
And the gap amount corresponding "HIGH" period of the delay time values t _D 65 is formed.

[Problems to be Solved by the Invention] In the above-described conventional clock driver, the waveforms of the clock signals φ1 and φ2 far from the clock driver 61 have a capacitance 67 and a capacitance 67 such as a wiring capacitance caused by wiring routing. Under the influence of 68, the clock signals become 信号 1 'and ２2' shown in FIG. If the values of the capacitors 67 and 68 are large, the clock signals φ1 ′ and φ2 ′ overlap as shown by the hatched portions in FIG. FIG. 9 shows a timing chart when such clock signals .phi.1 'and .phi.2' are used for a latch signal of a dynamic latch circuit 75 similar to that shown in FIG. Clock signals φ1 ′ and φ shown in FIG.
The overlap width V _OVER with 2 ′ is a first N-channel MOSFET 72 that receives clock signal φ1 ′ as an input signal and a second N-channel MOSFET that receives clock signal φ2 ′ as an input signal.
If the threshold voltage (V _TN ) of the SFET 71 is exceeded, there is a moment or period when the first N-channel MOSFET 72 and the second N-channel MOSFET 71 are simultaneously turned on. At this moment or period, data penetrates from the data input side to the data output side, and the output signal of the latch circuit 75 becomes an intermediate level or an inverted voltage value as shown by a broken line in FIG. There is a problem that the circuit malfunctions.

The period during which the clock signals φ1 and φ2 are “HIGH” (hereinafter, this period is referred to as “HIGH width”)
Since it determined by the delay time value t _D of the waveform and the delay circuit 64 and 65 of the clock signal input to the clock driver 61, a variation in the manufacturing conditions, such as during the diffusion in the preparation, (e.g., the threshold voltage of the MOSFET When a high eye becomes like) become completed as the speed of the device becomes slow, delay time value t _D becomes larger than necessary, hIGH width of the clock signal φ1 and φ2 can no longer sufficiently taken. Considering the case of the dynamic latch circuit 75 as shown in FIGS. 6 and 8, when the HIGH width of the clock signals φ1 and φ2 is short as described above, when the input data signal comes later, There was a problem that the latch could not be completed.

The present invention has been made in view of such a problem, and controls an overlap width and a HIGH width of two clock output signals to appropriate values to effectively prevent a malfunction of a circuit to which these two clock signals are supplied. It is an object of the present invention to provide a clock driver capable of preventing the above.

Means for Solving the Problems A clock driver according to the present invention receives a clock signal and outputs first and second clock signals having different phases from each other. ,
A first delay variable circuit having a variable delay time to which a first clock signal output from the first buffer circuit is input and which provides an output obtained by delaying the first clock signal to the second buffer circuit; A second delay variable circuit having a variable delay time to which a second clock signal output from the second buffer circuit is input and which provides an output obtained by delaying the second clock signal to the first buffer circuit; The first and second clock signals are directly input to the first and second transistors, respectively, and the output signals of the circuit in which the first and second transistors are connected in series are integrated as delay time control signals to the first and second delay variable circuits. A clock overlap detection circuit to be inputted.

[Operation] In the clock driver of the present invention, a clock overlap detection circuit for detecting the overlap of clocks of two clock signals and a delay variable circuit capable of changing the delay time value are provided in the clock driver, and the clocks having different phases are provided. The overlap width of the two clock output signals is suppressed to a certain value or less, and the gap between the two clock output signals is prevented from being unnecessarily widened and the HIGH width is reduced. Therefore, a circuit to which two clock output signals are supplied does not malfunction.

Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a configuration of a clock driver according to a first embodiment of the present invention.

The first buffer circuit includes a NAND circuit 1 and an inverter circuit 3, and the second buffer circuit includes a NAND circuit 2 and an inverter circuit 5. The input clock signal φ is
The signal is input to one input terminal of the NAND circuit 1 and inverted by the inverter circuit 4 and input to one input terminal of the NAND circuit 2. Outputs of the first and second buffer circuits, that is, output signals of the inverter circuits 3 and 5, become clock signals φ1 and φ2 having different phases from each other. In this case, the clock signal φ1 is passed through a delay element composed of, for example, two inverter circuits 6 and 7 connected in series, through P-channel MOSFETs 10 to 12 and N-channel MOSFETs 16 to
It is input to a delay variable circuit composed of 18. The output of the variable delay circuit is input to the other input terminal of the NAND circuit 2 of the buffer circuit composed of the NAND circuit 2 and the inverter circuit 5. In this case, the clock signal φ2 is supplied to the P-channel type MOSFETs 13 to 15 and N through a delay element comprising inverter circuits 8 and 9 connected in series.
It is input to a variable delay circuit composed of channel type MOSFETs 19-21. The output of this delay variable circuit is NAND
The signal is input to the other input terminal of the NAND circuit of the buffer circuit including the circuit 1 and the inverter circuit 3. Also, N
The clock overlap detection circuit composed of the channel type MOSFETs 22 and 23, the resistance elements 35 and 36, and the capacitance element 37 receives clock signals φ1 and φ2 as input signals, and outputs the signals to the two delay variable circuits. . Power supply 24 ~
A power supply voltage is supplied from 28, and grounds 29 to 34 are connected to a ground potential point.

FIG. 2 shows a timing chart of the circuit of the first embodiment shown in FIG. The waveforms of the clock signals φ1 and φ2 are affected by the capacitance due to wiring routing and the like, and their waveforms are rounded, and clocks overlap between the clock signals φ1 and φ2. When the overlap width V _OVER reaches the threshold voltage (V _TN ) of the N-channel MOSFETs 22 and 23 constituting the clock overlap detection circuit, the N-channel MOSFET 22
And 23 are both turned on, and the potential at the node A fluctuates as shown in FIG. If this phenomenon continues,
The potential at the node B, which is the output point of the clock overlap detection circuit, gradually decreases as shown in FIG.

Next, the operation of the variable delay circuit will be described. When there is no overlap between the clock signals φ1 and φ2, the delay time until the clock signals φ1 and φ2 are input to the respective buffers via the respective delay elements and the respective variable delay circuits is constant. When the potential of the node B decreases due to the overlap between the clock signals φ1 and φ2, the N-channel MOSFETs 17 and 18 constituting each delay variable circuit and
Since the input voltages of 20 and 21 decrease, the current driving capabilities of these N-channel MOSFETs 17 and 18 and 20 and 21 decrease, and further, the P-channel MOSFET 10 and the N-channel MOSFET
ET18, P-channel MOSFET13 and N-channel MO
Since the output voltage of each ratio-type inverter circuit including the SFET 21 increases, the driving capability of the P-channel MOSFETs 11 and 14 also decreases. Accordingly, the delay time between the input and output of the variable delay circuit increases, the gap between the clock signals φ1 and φ2 widens, and the width V _OVER of the overlap between the clock signals φ1 and φ2 is reduced by the N-channel MOSFETs 22 and 23. V _TN or less. As a result, the clock signal φ1
And the circuit to which φ2 is supplied does not malfunction.

If the delay time value of the delay circuit is too large, the overlap between the clock signals φ1 and φ2 becomes small or disappears. At this time, however, the potential at the node B in FIG. The delay time value of the variable circuit becomes small, and the HI level of the clock signals φ1 and φ2 becomes high.
The GH width can be prevented from becoming smaller than necessary.

FIG. 3 is a circuit diagram showing a configuration of a clock driver according to a second embodiment of the present invention.

The difference between the circuit of the second embodiment shown in FIG. 3 and the circuit of the first embodiment shown in FIG. 1 is that the circuit of the second embodiment has one delay variable. Circuit is P
Channel type MOSFET 43, capacitive element 47 and inverter circuit
41, and the other variable delay circuit comprises a P-channel MOSFET 44, a capacitor 48, and an inverter circuit 42. A power supply voltage is supplied from the power supplies 45 and 46.

As in the first embodiment, when the clock signals φ1 and φ2 overlap, the potential of the node B starts to decrease,
The potential at this point B changes from the power supply voltage to the P-channel MOSFET 43.
And when lowered by the threshold voltage of 44 (V _TP) fraction, P-channel type MOSFET43 and 44 are turned on, the inverter circuit
The capacitance values of the capacitance elements 47 and 48 are added to the output sides of 41 and 42, the delay time value of the delay variable circuit increases, and the overlap width V _OVER of the clock signals φ1 and φ2 is increased by the N-channel MOSFETs 22 and 23. It can be kept below the threshold voltage.

Further, similarly to the first embodiment, it is possible to prevent the HIGH width of the clock signals φ1 and φ2 from becoming unnecessarily narrow.

[Effects of the Invention] As described above, according to the present invention, the clock driver is provided with the clock overlap detection circuit that detects the overlap of the clocks of the two clock signals and the delay variable circuit that can change the delay time value. Thereby, the overlap width of the two clock output signals having different phases can be suppressed to a certain value or less, and the gap between the two clock output signals can be prevented from being unnecessarily widened and the HIGH width can be reduced, Therefore, it is possible to provide a clock driver capable of effectively preventing a malfunction of a circuit to which these two clock signals are supplied.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. 1, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a block diagram showing an example of a conventional clock driver, FIG. 5 is a timing chart for explaining the operation of the circuit of FIG. 4, and FIG. FIG. 7 is a circuit diagram showing a dynamic shift register which is an example of a circuit to which two output signals of the driver are supplied, FIG. 7 is a timing chart for explaining the operation of the circuit of FIG. 6, and FIG. FIG. 9 is a circuit diagram showing an example of a case where two output signals of a clock driver supplied to the same dynamic shift register overlap with each other, and FIG. 9 is a timing chart for explaining the operation in the case of FIG. 1,2; NAND circuit, 3 ~ 9,41,42; Inverter circuit, 10 ~ 15,4
3,44; P-channel MOSFET, 16-23; N-channel MOSFET
ET, 35, 36; resistance, 37, 43, 44; capacity

Claims (1)

(57) [Claims] 1. A clock driver to which a clock signal is input and outputs first and second clock signals having different phases from each other, wherein the first and second buffer circuits are output from the first buffer circuit. A first clock signal is input, and a first delay variable circuit that has a variable delay time and provides an output obtained by delaying the first clock signal to the second buffer circuit, and is output from the second buffer circuit. A second delay variable circuit that receives a second clock signal, provides a delayed output of the second clock signal to the first buffer circuit, and has a variable delay time, and the first and second clock signals are The first and second delays are integrated as output signals of a circuit in which first and second transistors, which are directly input, are connected in series, respectively, and are integrated as delay time control signals. Clock driver, characterized by comprising a clock overlap detection circuit is input to the variable circuit.