JPH03166813A - Clock duty correcting circuit - Google Patents

Abstract

PURPOSE:To adjust variation in clock duty automatically by converting the duty of a clock output into a voltage level and monitoring it, and varying the delay quantity of a clock input signal inputted to an S-RFF according to the potential. CONSTITUTION:When a clock with 50% duty is outputted, the output voltages of smoothing circuits 5 and 6 are at the same potentials, so the delay times t1 and t2 of delay circuits 2 and 3 are equal to each other. When the duty of a clock output becomes narrow, the potential of the smoothing circuit 6 drops and the delay quantity t2, of the delay circuit becomes longer than its last delay quantity t2. The potential of the circuit 5 rises to the contrary, so the delay quantity t'1 of the circuit 2 becomes shorter than its t1. Consequently, the duty of the clock output increases automatically. When the clock duty further increases, the delay quantity of the circuit 2 becomes larger and the delay quantity of the circuit 3 becomes smaller, so the duty of the clock output is adjusted automatically in a direction of narrowing. Namely, the duty of the clock output is adjusted automatically to an equal value at all times.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to a duty correction circuit that automatically adjusts the duty of a clock signal. Conventional technology Conventionally, in this type of clock duty correction circuit, the second
As shown in the figure, a portion of the signals of the clock driver 8.14 which receives the clock signal 1 as input is outputted to the outside of the semiconductor integrated circuit via the output pads 9, 10, and the external load capacitor 11.
Adjustments were made by changing 12. Problems to be Solved by the Invention The conventional clock duty correction circuit described above requires an external load capacitance, and the external load capacitance must be changed in accordance with process fluctuations, duty fluctuations of externally input clock signals, etc. The drawback was that it required a lot of man-hours to make the adjustments. The present invention has been made in view of the above-mentioned conventional situation,
Therefore, an object of the present invention is to provide a novel clock duty correction that eliminates the above-mentioned drawbacks inherent in the conventional technology and makes it possible to automatically adjust clock duty fluctuations without adjusting using an external capacitor or the like. The purpose is to provide circuits. Means for Solving the Problems In order to achieve the above object, the clock duty correction circuit according to the present invention includes an S-R flip-flop, two smoothing circuits, a first and a second smoothing circuit, and a low voltage input voltage. It has two delay circuits, a first and a second delay circuit, which increase the delay amount when the voltage is applied, and the non-inverting output of the S-R flip-flop is connected to the delay amount control terminal of the first delay circuit through the first smoothing circuit. , the clock signal is input to the first delay circuit through the inverter circuit, the output of the first delay circuit is connected to the reset terminal of the S-R flip-flop, and the inverted output of the S-R flip-flop is input to the second smoothing circuit. is connected to the delay amount control terminal of the second delay circuit through S-, the clock signal is input to the second delay circuit, and the output of the second delay circuit is connected to S-
It is connected to the set terminal of the R flip-flop. Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1, the clock signal 1 and its inverted signal obtained through the inverter 7 are respectively input to delay circuits 2.3 whose delay amount changes depending on the voltage, and their outputs are sent to the S-R flip-flop 4. The output of the delay circuit 2 is connected to the set terminal S, and the output of the delay circuit 3 is connected to the reset terminal R. As a circuit for realizing the delay circuits 2 and 3, for example, as shown in FIG.
is input to an inverter 16, the output of which is connected to a P-channel transistor l7 and two N-channel transistors 18.
The signal is input to the buffer 2l through a voltage-controlled delay element 20 consisting of 19 elements. Further, the output of the buffer 2l is input to an inverter 27 through a voltage-controlled delay element 25 consisting of a P-channel transistor 22 and two N-channel transistors 23 and 24. Here, as a characteristic of the voltage-controlled delay elements 20 and 25, when the potential of the voltage-controlled signal 26 is low, the current flowing through the N-channel transistors 19 and 24 is suppressed;
The fall time of the output becomes longer. the result,
As a whole of the delay circuit shown in FIG. 3, the input signal 15 is delayed by the amount that the potential of the voltage control signal 26 is lowered and is output as an output signal 28. In FIG. 1, the output of the S-R flip 7 rotor 4 is smoothed and used as a signal source for voltage control signals for these delay circuits 2.3. The voltage control signal for the delay circuit 2 is generated by passing the inverted output of the S-R flip-flop 4 through the smoothing circuit 5, and the voltage control signal for the delay circuit 3 is generated by passing the normal output of the S-R flip-flop 4 through the smoothing circuit 6. Made. A specific circuit for the smoothing circuits 5 and 6 is realized, for example, by loading a large capacity capacitor 30 onto the output of a buffer 29, as shown in FIG. Next, the operation of the present invention shown in FIG. 1 will be explained.
Figures 5 and 6 are time charts for explaining the movements in Figure 1. FIG. 5 is a time chart showing a state in which a clock with a duty of 50% is output. At this time, since the output voltages of smoothing circuits 5 and 6 are at the same potential, the delay time of delay circuits 2 and 3 is t1 and t2 are equal. FIG. 6 is a time chart when the duty of the clock output becomes narrow. At this time, the potential of the smoothing circuit 6 becomes lower than that in the state shown in FIG. This is longer than the delay amount t2 in the state shown in the figure. Conversely, since the potential of the smoothing circuit 5 is higher than the state shown in FIG.
The delay amount t1 in the state shown in FIG. 5 is shorter than the delay amount L1 in the state shown in FIG. For this reason, the duty of the clock output automatically changes in the direction of expansion. On the other hand, when the duty of the clock output changes in the direction of further widening, the delay amount of delay circuit 2 increases, and the delay amount of delay circuit 3 decreases, so that the duty of the clock output automatically decreases. be adjusted.

In other words, the duty of the clock output is automatically adjusted so that it is always equal. Effects of the Invention As explained above, according to the present invention, the duty of the clock output is converted into a voltage level and monitored, and the amount of delay of the clock input signal input to the S-R flip-flop is determined according to the voltage level. By changing this, it is possible to automatically adjust clock duty fluctuations without adjusting using external capacitors, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the clock duty correction circuit according to the present invention, FIG. 2 is a block diagram of a conventional clock duty correction circuit, and FIG. 3 is a block diagram showing an embodiment of the clock duty correction circuit according to the present invention. FIG. 4 is a circuit diagram showing an embodiment of the voltage-controlled delay circuit used; FIG. 4 is a circuit diagram showing an embodiment of the smoothing circuit used in the clock duty correction circuit according to the present invention; FIGS. The figure is a timing chart explaining the operation of the present invention. 1... Clock signal, 2, 3... Voltage controlled delay circuit, 4... S
-R flip-flop, 5.6... smoothing circuit, 7,
8, 14. 16. 27...Inverter, 9.1
0...Output pad, 11. 12... External capacitor, 13... Clock output signal, 15... Input signal, 17. 22...P channel transistor, 1g,
19. 23. 24...N channel transistor, 21. 29...buffer, 20. 25... Voltage control delay element, 26... Voltage control signal, 28...
Delayed output signal, 30... capacitor

Claims (1)

[Claims] In a semiconductor integrated circuit, an S-R flip-flop, two first and second smoothing circuits, two first and second delay circuits whose delay increases when a lower voltage is applied to the input voltage, and an inverter circuit. The non-inverting output of the S-R flip-flop is connected to the delay amount control terminal of the first delay circuit through the first smoothing circuit, and the clock signal is connected to the delay amount control terminal of the first delay circuit through the inverter circuit. the output of the first delay circuit is connected to the reset terminal of the S-R flip-flop, and the inverted output of the S-R flip-flop passes through the second smoothing circuit to the second delay circuit. A clock signal is input to the second delay circuit, and the output of the second delay circuit is connected to the set terminal of the S-R flip-flop. A clock duty correction circuit characterized in that a normal rotation output of the clock output signal is used as a clock output signal.