JPS6139651A - Clock phase fine adjusting circuit - Google Patents

Abstract

PURPOSE:To finely adjust clock phase by providing an RC circuit and a comparator in a repeater of digital communication and using an emitter follower for resistance of the RC circuit. CONSTITUTION:When a clock signal of a waveform (1) is inputted to the RC circuit and an input of RC, rise and fall parts are made dull as shown by a waveform (2). This is compared with reference voltage Vref by a comparator COMP and a signal of a waveform (3) is outputted. By adjusting current ie of a transistor Q that acts as an emitter follower, the time constant due to internal resistance and capacity C can be changed, and accordingly, its phase difference can be adjusted. Thus, as the phase of the clock can be adjusted finely, clock signals can be adjusted most suitably in a superhigh-speed repeating circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for finely adjusting the phase of a clock signal in a repeater circuit for digital communication.

[Conventional technology]

In a digital communication device, it is necessary to set the clock extracted by a timing circuit at an optimal point in order to reliably identify "1" and "0" signals from the received waveform. For this reason, it is necessary to finely adjust the phase of the clock signal, and conventionally this has been done by varying the length of the coaxial line in order to finely adjust the phase of the clock signal.

[Problem that the invention seeks to solve]

However, in the case of ultra-high speeds of several gigahertz, the method of adjusting by changing the length of the coaxial line has the disadvantage that fine adjustment is difficult.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the conventional circuit and provide a circuit that can finely adjust the phase more accurately.

[Means for solving problems]

A means to solve the problem is to configure a phase fine adjustment circuit with an RC circuit and a comparator, use an emitter follower as the resistance of the RC circuit, and adjust the resistance value of the current flowing through the emitter follower to adjust the current flowing through the emitter follower. This is achieved by a clock phase fine adjustment circuit that finely adjusts the phase by changing internal resistance.

[Effect]

According to the present invention, a clock phase fine adjustment circuit in an integrated timing circuit is configured with an emitter follower, an RC circuit using a capacitance, and a comparator, and utilizes the fact that the internal resistance of the transistor changes depending on the current flowing through the emitter follower transistor. Since the time constant of the RC circuit is changed to adjust the phase, extremely fine adjustments can be made easily.

This creates an I-key effect.

〔Example〕

FIG. 1 is a diagram showing the configuration of a clock phase fine adjustment circuit according to the present invention.

FIG. 2 is a diagram showing waveforms at various parts in FIG. 1.

FIG. 3 is a diagram showing the principle of the present invention.

In the figure, RC is an RC circuit, COMP is a comparator, Q is a transistor, C is a capacitor, A is a current source, IN is an input terminal, and OUT is an output terminal.

The same symbols represent the same objects throughout all the figures below.

An extracted clock signal as shown in (2) in FIG. 2 is applied to the input of the RC circuit RC in FIG. The clock signal is R
In the C circuit RC, the rising and falling portions are slowed down, resulting in a waveform not shown in (■) in FIG. Input this waveform ■ to the comparator COMP. It is compared with the reference voltage Vref in the comparator COMP, and when the waveform (2) becomes larger than the reference voltage Vref, the comparator COMP outputs an output signal, and when the waveform (2) becomes smaller than the reference voltage Vref, there is no output signal. 2 in FIG. 2 shows the output waveform of this comparator COMP.

In this case, the time difference between the waveform shown in ■ in Figure 2 and the waveform shown in ■ in Figure 2 is 1. is the phase difference between both pulses, and this phase difference t1 is determined by the time constant of the RC circuit RC. Therefore, by changing this time constant, the phase difference can be reduced to 1. can be adjusted.

FIG. 3 is a diagram showing the principle of the present invention. FIG. 3 (al is a kind of RC circuit, and FIG. 3 fbl is an equivalent circuit.

FIG. 3 ta+ is an RC circuit composed of an internal resistance Re and a capacitor C of a transistor Q that operates as an emitter follower.

That is, since the internal resistance Re of this transistor Q depends on the current 18 flowing through the transistor Q, by adjusting the current iQ flowing through the transistor Q that operates as an emitter follower, the RC composed of the internal resistance Re and the capacitance C can be adjusted. The phase difference t1 can be adjusted by changing the time constant of the circuit. Therefore, it can be expressed by the equivalent circuit shown in FIG. 3 fb).

FIG. 4 is a diagram showing an embodiment of a clock phase fine adjustment circuit according to the present invention.

In the figure, Q1 to Q7 are transistors, R1 to R7 are resistors, VCC% Vee is the power supply voltage, Vbl, V
b2 is the control voltage, V ref is the reference voltage, and R
V is an external variable resistor.

The detailed circuit of the present invention will be explained below with reference to FIG. The part surrounded by the dotted line is the ICII circuit.

The circuit of transistors Q5 and 06 is a differential circuit, and transistor Q7 is its current supply circuit. Also transistor Q
3 and transistor Q4 are in a current mirror relationship,
Transistor Q2 is a current source for transistor Q1.

The pulse (■ in FIG. 2) input to the input terminal IN is applied to the base of the transistor Q1.

When the external variable resistor RV is changed, the current 2 flowing through the transistor Q4 changes, and therefore the current I3 flowing through the transistor Q3, which is in a current mirror relationship, also changes. Therefore, the current 11, which is the sum of the current ■3 and the current flowing through the transistor Q2, also changes, so the internal resistance of the transistor Q1, which operates as an emitter follower, changes, and the voltage applied to the base of the transistor Q5 changes from ■ in Figure 2. Become.

As mentioned above, the circuit of transistors Q5 and Q6 is a differential circuit, and the base of transistor Q6 has a reference voltage V r
Since ef is applied, it is possible to obtain the output waveform shown in FIG. 2 at the output terminal OUT, and the phase can be finely adjusted by changing the external variable resistor RV.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the phase of the clock can be finely adjusted by changing the variable resistor external to the IC and varying the emitter current inside the IC circuit. This has the great effect that the clock signal can be adjusted to the optimum point in the circuit as well.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a clock phase fine adjustment circuit according to the present invention. FIG. 2 is a diagram showing waveforms at various parts in FIG. 1. FIG. 3 is a diagram showing the principle of the present invention. FIG. 4 is a diagram showing an embodiment of a clock phase fine adjustment circuit according to the present invention. In the figure, RC is an RC circuit, COMP is a comparator, Q is a transistor, C is a capacitor, A is a current source, IN is an input terminal, ○tJT is an output terminal, 01 to Q7 are transistors, R1 to R7 are resistors, Vcc and Vee are the power supply voltages, Vbl and Vb2 are the control voltages, and Vref
is a reference voltage, and RV is an external variable resistor. Child 1st 3rd (α) (b)

Claims (1)

[Claims] The phase fine adjustment circuit is composed of an RC circuit and a comparator,
A clock phase fine adjustment circuit characterized in that an emitter follower is used as a resistor of the RC circuit, and the internal resistance of the emitter follower is changed by adjusting the resistance value of the current flowing through the emitter follower to finely adjust the phase.