JPH0347609B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an electronic device including a sequential circuit such as a flip-flop or a shift register.
The present invention relates to a circuit for resetting the sequential circuit to a predetermined state when the power is turned on.

For electronic devices that include sequential circuits such as flip-flops and shift registers, it may be necessary to reset each of the sequential circuits to a predetermined state at the same time as power is turned on, and this reset is performed by generating a reset pulse. This is done by a reset pulse output from the circuit.

Conventional reset pulse generation circuit 1 shown in Fig. 1
is constructed by connecting a capacitor 4 and a resistor 5 in series between power supply terminals 2 (VDD) and 3 (VSS), and connecting these connection points 6 to the input terminal of an inverter 7. For example, the clear terminal 9 of the flip-flop circuit 8 is connected to the output terminal of the flip-flop circuit 8.

Generally, there is a so-called rise time before the power supply voltage output from a power supply device reaches a predetermined voltage. In the reset pulse generating circuit 1, as the rise time of the power supply becomes longer, the width of the reset pulse outputted from the inverter 7 becomes smaller, and eventually the reset pulse generating circuit 1 no longer outputs the reset pulse.
In order to improve this problem, measures are generally taken to select large values for the capacitor 4 and the resistor 5 of the reset pulse generating circuit 1 and to increase the time constant determined by these values.

However, these capacitors 4 and resistors 5
If the value of is increased, reset pulses are generated due to fluctuations in the power supply voltage and noise, causing malfunctions, so this method has its limitations.

The present invention eliminates the above drawbacks and reduces the influence of the rise time of the power supply voltage by using the capacitor 4.
Another object of the present invention is to make it difficult for malfunctions to occur due to fluctuations in power supply voltage or noise even if the value of the resistor 5 is made sufficiently large.

The present invention will be explained in detail below with reference to FIGS. 2, 3, and 4.

Figure 2 is a principle diagram of the power-on reset circuit of the present invention, where power supply terminals 10 (VDD) and 11 (VSS)
A capacitor 12 and a resistor 13 are connected in series between the capacitor 12 and the resistor 13, the input terminal of the inverter 15 is connected to the connection point 14 of these, and a MOS transistor is connected in parallel with the resistor 13.
The drain or source of the transistor 16 is connected, and the output terminal of the inverter 15 is connected to the gate of the MOS transistor 16.

Next, the operation of the present invention will be explained with reference to FIG. When a power supply voltage is applied between the power supply terminals 10 (VDD) and 11 (VSS), the capacitor 12
As shown in FIG. 4a, the connection point 14 between the resistor 13 and the resistor 13 first approaches the VDD level from the VSS level as the power supply voltage rises, and then gradually decreases again.
Although it approaches the VSS level, the above inverter 15
When reaching the inversion level V _T , the output terminal of the inverter 15 is inverted from the VSS level to the VDD level as shown in FIG. 4b, and the MOS transistor 16, which has a relatively low on-resistance, is turned on. and the connection point 14 and the power supply terminal 11
(VSS) decreases, and the level at the connection point 14 quickly reaches the VSS level. Here, the time t ₁ until the inverter 15 is reversed is:
It is determined by the capacitor 12 and the resistor 13, and after a single reset pulse is output and the inverter 15 is inverted, the connection point 14 is brought to the VSS level by the MOS transistor 16, which has a relatively low on-resistance. It is maintained.

In addition, Fig. 3 shows an embodiment of the present invention, in which the resistor is
This is a replacement for a MOS transistor. The operation is similar to that shown in FIG.

In the above description, an N-channel transistor was used as the MOS transistor, but it is clear that the present invention is not limited to this and that a P-channel transistor can also be applied.

As described above, according to the present invention, even if the values of the capacitor and resistor are sufficiently large in order to reduce the influence of the rise time of the power supply voltage, stability can be maintained against fluctuations in the power supply voltage and noise. In the embodiment of FIG. 3, by using a MOS transistor instead of a resistor, the same effect as that of FIG. 2 or a better effect can be obtained with a smaller area.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional power-on reset circuit, Fig. 2 is a principle diagram of a power-on reset circuit of the present invention, Fig. 3 is a circuit diagram of an embodiment of the present invention, and Fig. 4 is a circuit diagram of a conventional power-on reset circuit.
Figures a and b are time charts showing the voltage at the connection point 14 and the output voltage of the inverter 15 shown in FIG. 2, respectively. 10, 11...Power terminal, 12...Capacitor, 13...Resistor, 15...Inverter, 16
...MOS transistor.

Claims (1)

[Claims] 1 a capacitor having one end connected to one voltage supply line; a first MOS transistor having a drain and gate connected to the other end of the capacitor and a source connected to the other voltage supply line; A power-on reset circuit consisting of an inverter having an input terminal connected to its other end, and a second MOS transistor having its drain and gate connected to the input terminal and output terminal of the inverter, respectively, and its source connected to the other voltage supply line. circuit.