JPH118538A - Repeat signal stop detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the generation/stop of signals, which are generated repeatedly in a prescribed seriod, in a simple configuration. SOLUTION: The waveform of a signal generated from an oscillation circuit 31 is shaped into rectangular wave by a buffer 32. The output from the buffer 32 is divided into two, and one output is delayed by a delay circuit 33. An exclusive OR gate 34 operates the exclusive OR of output signal from the buffer 32 and signal delayed by the delay circuit 33. When the output of the exclusive OR gate 34 is at a low level, an N-channel MOS field effect (NchMOS) transistor 35 is turned off, and a capacitor 36 is charged. When that output is at a high level, the NchMOS transistor 35 is turned on, and the capacitor 36 is discharged. A comparator circuit 38 compares the charging voltage of the capacitor 36 with a reference voltage, and when the charging voltage exceeds the reference voltage, the generation/stop signal of the repeat signal is derived.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repetitive signal stop detection circuit for detecting that the generation of a signal repeatedly generated at a predetermined cycle has stopped.

[0002]

2. Description of the Related Art Conventionally, in a device such as a clock, a camera, a personal computer, or a PDA device, a repetitive signal, such as a watchdog timer, which is periodically generated in response to the operation state of various circuits is stopped. To detect
A circuit that performs a predetermined operation when a stop is detected is generally used. Of the repetitive signals, the clock signal is a time reference for the operation of the device and has a significant effect on the accuracy of the device. As a conventional technique for detecting the occurrence stop of the repetitive signal, particularly regarding the detection of the stop of the oscillation of the clock signal, for example, a method using an oscillation stop detection circuit disclosed in Japanese Patent Application Laid-Open Nos. 5-120232 and 2-2205513 is known. I have.

FIG. 9 is a drawing of FIG. 1 from Japanese Patent Laid-Open Publication No. Hei 5-122032. This oscillation stop detection device according to the prior art has six stages of D flip-flop circuits 1 to 6. Output Q of the preceding flip-flop circuits 1 to 5
Are sequentially input to the inputs D of the flip-flop circuits 2 to 6 at the subsequent stage. The input D of the first-stage flip-flop circuit 1 includes a clock signal CL which is a detection target of oscillation stop.
K1 is input. A clock signal CLK2 not to be detected is commonly input to a clock input CLOCK of each of the flip-flop circuits 1 to 6. An output Q of each of the flip-flop circuits 1 to 6 is input to a 6-input AND circuit 7 for calculating a logical product and a 6-input NOR circuit 8 for calculating a logical negation. Input OR
Input to the circuit 9.

When the oscillation of the clock signal CLK1 is stopped, all the output levels of the flip-flop circuits 1 to 6 become equal to one of the high level and the low level at the sixth rising of the clock signal CLK2. For this reason, AND
Either the circuit 7 or the NOR circuit 8 outputs a high level, and the OR circuit 9 outputs a high level. OR circuit 9
, The oscillation stop of the clock signal CLK1 is detected.

FIG. 10 shows a simplified version of FIG. 1 described in Japanese Patent Application Laid-Open No. H2-220513. In this oscillation stop detection circuit according to the prior art, a clock signal generated from an oscillator 11 is supplied to a buffer 12 and an inverter 13. Each output is divided by one of the counters 14 and 15
The signals are input to four pulse detection circuits 20 via delay circuits 16 and 17. The pulse detection circuit 20 detects a rising or falling pulse edge of the clock signal for two cycles. The output of the pulse detection circuit 20 is input to each of the four integration comparison circuits 21. When the oscillation of the oscillator 11 stops, any one of the integration and comparison circuits 21 outputs a high level. The output of each integration / comparison circuit 21 is input to a four-input OR circuit 22. When the OR circuit 22 outputs a high level, oscillation stop is detected.

[0006]

The oscillation stop detecting device shown in FIG. 9 does not consider a case where the oscillation of the independent clock signal CLK2 which is not a detection target of the oscillation stop is stopped.
When the clock signal CLK2 stops oscillating, it becomes impossible to detect the oscillation stop of the clock signal CLK1 to be detected. In the configuration of the related art using a clock signal irrelevant to the clock signal to be detected, a plurality of types of clock signals are required, which increases the cost of the system. In addition, there are many devices that cannot use an independent clock signal that is not a detection target of oscillation stop.

In the oscillation stop detecting circuit shown in FIG. 10, an independent clock signal is not required, so that the above-mentioned problem is solved. However, since the circuit configuration requires four integration / comparison circuits and two delay circuits, the circuit scale becomes large. As the circuit scale increases, it becomes difficult to reduce the size of the oscillation stop detection circuit, and the manufacturing cost also increases.

An object of the present invention is to provide a repetitive signal stop detection circuit capable of detecting, with a simple configuration, the stop of generation of a signal that is repeatedly generated at a predetermined cycle.

[0009]

SUMMARY OF THE INVENTION The present invention relates to a circuit for detecting a stop of generation of a signal that is repeatedly generated at a predetermined cycle, and a change detection circuit for detecting a level change accompanying the generation of the signal, and a change detection circuit. In response to a change in the level of the signal detected by the switching element, the switching element is in a conductive state during a period in which the signal level changes, and is in a blocking state during a period in which the signal level does not change, and a capacitor connected in parallel to the output side of the switching element And a resistor connected between the DC power supply and one end of the capacitor to charge the capacitor, and a signal representing stop of generation of a repetitive signal when the charging voltage of the capacitor exceeds a preset reference voltage. And a comparing circuit for detecting a repetitive signal stop.

According to the present invention, the change detection circuit detects a level change accompanying the generation of a repetitive signal. The switching element becomes conductive during a period in which the signal level changes in response to a level change of the signal detected by the change detection circuit,
During a period in which the signal level does not change, it is in a cutoff state. A capacitor is connected in parallel to the output side of the switching element. A resistor is connected between the DC power supply and one end of the capacitor to charge the capacitor. The comparison circuit is
The charging voltage of the capacitor is compared with a preset reference voltage. When the repetitive signal stops and the signal level stops changing, the switching element is turned off, and the charging voltage of the capacitor increases. When the charging voltage exceeds the reference voltage, it is detected by a comparator circuit, which derives a signal indicating that the repetitive signal has stopped generating. Therefore, it is possible to detect the stop of the generation of the repetitive signal even with a simple configuration. If a repetition signal to be detected to stop occurrence is input, a repetition signal not to be detected is not required, so that there is no need to provide a circuit for generating a non-detection repetition signal, and the cost can be greatly reduced. . Further, it is possible to avoid a situation in which detection is not possible due to the stop of the repetitive signal itself that is not a detection target, so that reliability can be improved.

In the present invention, the repetition signal is an output signal of an oscillation circuit.

According to the present invention, since the repetitive signal is the output signal of the oscillation circuit, it is possible to detect the stop of the generation of a signal such as a clock signal which serves as a time reference for the operation of the device.

[0013] In the present invention, the change detection circuit may include a buffer for shaping the waveform of the repetitive signal to convert it into a rectangular wave, a delay circuit for delaying the output of the buffer, and an exclusive control of the output of the delay circuit and the output of the buffer. An exclusive-OR gate for calculating a logical sum, wherein the switching element is a MOS transistor.

According to the present invention, the change detection circuit includes a buffer for shaping the waveform of the repetitive signal to convert it into a rectangular wave, a delay circuit for delaying the output of the buffer, and an exclusive control of the output of the delay circuit and the output of the buffer. An exclusive-OR gate for calculating a logical sum. The switching element is MO
Since the transistor is an S transistor, a change in resistance value between when the transistor is on and when the transistor is off can be made large. Even if there is a variation in the cycle of the generation of the repetitive signal, the stop of the generation of the repetitive signal can be detected within a certain range of the variation.

In the present invention, the change detection circuit, the switching element, and the comparison circuit are formed in a semiconductor integrated circuit chip, and the capacitor and the resistor
It is characterized in that it is formed as an integrating circuit outside the semiconductor integrated circuit chip.

According to the present invention, the change detection circuit, the switching element, and the comparison circuit are formed in a semiconductor integrated circuit chip. On the other hand, the capacitor and the resistor are formed as an integrating circuit outside the semiconductor integrated circuit chip. Therefore, if the resistance value of the resistor is increased and the capacitance value of the capacitor is also increased, it is easy to set a large time constant of the integration circuit. By increasing the time constant and lengthening the time required to detect the stop of the signal generation, it is possible to detect the stop of the signal generation irrespective of the generation cycle even for a repetitive signal having a large cycle.

Further, in the present invention, the repetition signal is a clock signal serving as a reference for operation as a clock.

According to the present invention, the repetition signal is a clock signal which is a reference for the operation as a clock. For example, when the generation of the clock signal is stopped and the signal is generated again thereafter, the repetition signal appears to be apparent. Nothing happens to the operation of the watch. The signal indicating the stop of generation of the repetition signal derived by the comparison circuit can be used as a flag indicating that the clock is stopped at least temporarily.

[0019]

FIG. 1 shows a basic configuration of a repetitive signal stop detection circuit according to an embodiment of the present invention. The signal generated from the oscillation circuit 31 is shaped into a rectangular wave by the buffer 32. Buffer 3 as a logic circuit
2 amplifies the input signal until the output is saturated,
Even an input signal having a small amplitude can be amplified and converted into a rectangular wave. The rectangular wave output from the buffer 32 is branched into two, one of which is delayed by the delay circuit 33. The two-input exclusive OR gate 34 includes:
An output signal from the buffer 32 and a signal delayed by the delay circuit 33 are input. Exclusive OR gate 34
Are high levels during the period when the levels of the two input signals are different, and are low levels during the same period.

N-channel MOS field effect transistor (hereinafter abbreviated as “NchMOS transistor”) 3
The output signal of the exclusive OR gate 34 is input to the fifth gate. The source of the NchMOS transistor 35 is grounded. For example, a capacitor 36 having a capacitance value C such as 0.1 μF is connected in parallel between the source and the drain of the NchMOS transistor 35. Resistance 3 with resistance R
7 is connected between a positive DC power supply of the voltage Vcc and a connection point between the drain of the NchMOS transistor 35 and the capacitor 36. The comparison circuit 38 includes a capacitor 36
Is compared with a preset reference voltage. When the charging voltage of the capacitor 36 exceeds the reference voltage, the comparing circuit 38 derives a signal indicating that the generation of the repetitive signal has stopped.

FIG. 2 shows an equivalent circuit when the NchMOS transistor 35 of the embodiment shown in FIG. When the exclusive OR gate 34 outputs a low level, the NchMOS transistor 35 is turned off. In this state, the resistance between the source and the drain of the NchMOS transistor 35 becomes sufficiently large, for example, several hundred MΩ, which can be regarded as equivalent to the open state. At this time, the capacitor 36
Is charged via the resistor 37 by the voltage Vcc of the DC power supply.

FIG. 3 shows an equivalent circuit when the NchMOS transistor 35 of the embodiment of FIG. 1 is turned on.
When the exclusive OR gate 34 outputs a high level, N
The chMOS transistor 35 is turned on. In this state, the resistance value r between the source and the drain of NchMOS transistor 35 is, for example, several tens Ω to several tens
0Ω, and the resistance value R of the resistor 37 is changed from several MΩ to several tens M
If it is Ω, it is sufficiently smaller than the resistance value R. At this time, the capacitor 36 is connected to the NchMOS transistor 3
5 is discharged through the source / drain.

FIG. 4 is a timing chart for points a, b, c, and d in FIGS. 1 to 3 and the output OUT of the comparison circuit 38 when a repetitive signal is normally generated. . The signal generated from the oscillation circuit 31 is shaped in the buffer 32 into a rectangular wave as shown in the timing chart at the point a. The output from the buffer 32 is branched into two, one of which is a delay circuit 33.
And the waveform becomes as shown in the timing chart at the point b. The degree of delay can be reduced compared to the signal repetition period. Exclusive OR gate 3
4, a signal as shown in the timing chart at point a and a signal as shown in the timing chart at point b are input. The exclusive OR gate 34 outputs a high level during the period when the levels of the two input signals are different, and outputs a low level during the period when the levels are the same. The period in which the levels are the same corresponds to the rising and falling edges of the original waveform at point a. As a result, the output of the exclusive OR gate 34 has a spike waveform as shown in the timing chart at the point c, and an edge at which the logic level of the original signal changes is detected.

The NchMOS transistor 35 uses a spike waveform signal as shown in the timing chart at the point c as a gate voltage. When the gate voltage is at a low level, the NchMOS transistor 35 is turned off, and the resistance value in the cutoff state is much larger than the resistance value R. Therefore, in FIG. 4, the capacitor 36 can be considered to be charged with the time constant CR as shown in the period T1 of the timing chart at the point d representing the charging voltage of the capacitor 36. When the gate voltage is at a high level, Nc
The hMOS transistor 35 is turned on, and the resistance value r in the conductive state is r << R. Accordingly, as shown in the period T2 of the timing chart at the point d, the capacitor 36 is discharged with the time constant Cr. Here, the period T1
Is a time constant C related to the period T2.
r is sufficiently larger than r. Capacitor 36
The circuit constant and the delay circuit 33 are set so that the electric charge charged in the period T1 can be sufficiently discharged in the period T2.
The delay time etc. is set.

The voltage at point d when the capacitor 36 is charged to the maximum is VF, and d based on the maximum charge amount of the capacitor 36 when the oscillation circuit 31 normally generates a signal.
Assuming that the maximum voltage at the point is V0, the range of the voltage V at the point d at the time of normal occurrence is 0 <V <V0 <VF. Comparison circuit 38
Are set so as to satisfy 0 <V0 <VR <VF. The comparison circuit 38 outputs a low-level signal if the comparison target voltage is smaller than the reference voltage VR,
When the comparison target voltage is equal to or higher than the reference voltage VR, a high-level signal is output. When the signal is normally generated from the oscillation circuit 31, 0 <V0 <VR <VF is always satisfied. Therefore, as shown in the timing chart of the output OUT in FIG. Is output. When the generation of the signal from the oscillation circuit 31 stops, FIG.
Is fixed at either the high level or the low level because of passing through the buffer 32.

FIG. 5 is a timing chart for points a, b, c, and d in FIG. 1 and the output OUT of the comparison circuit 38 when the output of the buffer 32 is fixed at a high level. Is shown. When point a is fixed at a high level,
The point b is also fixed at a high level with a delay of T2 time. As a result, two high-level signals are input to the exclusive OR gate 34, and as shown in the timing chart at the point c,
The exclusive OR gate 34 always outputs a low level. N
The chMOS transistor 35 is always off,
As shown in the timing chart at point d, continuous charging of the capacitor 36 is started with a delay of the delay time T2 of the delay circuit 33 from the last output level change of the buffer 32. When the time t when the voltage V at the point d becomes equal to or higher than the reference voltage VR of the comparison circuit 38 (hereinafter referred to as “stop detection time”) t from the start of charging, the comparison circuit 38 outputs a high-level signal OUT.

FIG. 6 is a timing chart for points a, b, c, and d in FIG. 1 and the output OUT of the comparison circuit 38 when the output of the buffer 32 is fixed at a low level. Is shown. When point a is fixed at a low level,
Point b is also fixed at a low level with a delay of T2 time. As a result, two low-level signals are input to the exclusive OR gate 34, and as shown in the timing chart at the point c,
The exclusive OR gate 34 always outputs a low level. N
The chMOS transistor 35 is always off,
Continuous charging of the capacitor 36 is started. When the stop detection time t has elapsed from the start of charging, the voltage V at the point d becomes equal to or higher than the reference voltage VR of the comparison circuit 38, and the comparison circuit 38 outputs a high-level signal.

In the embodiment shown in FIG. 1, when the subsequent signal is generated within a period shorter than the stop detection time t shown in FIGS. 5 and 6 from the generation of the preceding signal, the charging voltage of the capacitor 36 becomes It does not exceed the reference voltage VR of the comparison circuit 38. For this reason, in the embodiment of FIG. 1, by appropriately setting the stop detection time t of the integration circuit signal, the occurrence stop can be detected even in a repetitive signal in which the time interval of occurrence is not constant.

FIG. 7 shows a MOS-LSI according to the embodiment of FIG.
An example of a circuit in the case of realizing this is shown below. Oscillation circuit 31
Is a feedback resistor 42 externally connected to the LSI 41, a capacitor 43, a vibrator 44 such as a crystal vibrator,
1 Inverting amplifier 45 constituted by an internal inverter
It is composed of Such an oscillation circuit has a generally known configuration. It is assumed that the oscillation circuit 31 generates a clock signal for a clock. The resonance frequency of the vibrator 44 is, for example, about 32 kHz.

As a method of forming the delay circuit 33 inside the LSI 41, the delay time in this embodiment is several n.
Since it may be in the order of tens of nanoseconds, a method is used in which the inverters are connected in series in even-number stages using the delay between the input and output of the inverter. This method is the simplest and can reduce the circuit scale. The delay circuit 33 includes an inverter 46 and an inverter 47.

As a simple method of configuring the comparison circuit 38 inside the LSI 41, an inverter having input / output characteristics as shown in FIG. A method realized by an inverter group is used. The comparison circuit 38 shown in FIG.
And an inverter 49 for phase matching, and the threshold value VR is used as a reference voltage.

The integration circuit formed by the capacitor 36 and the resistor 37 is externally connected to the LSI 41,
The time constant can be increased as compared with the case where it is realized inside the SI 41. For example, the function of a clock or the like generally has an oscillation cycle of about 31 μs, so that the time constant of the integrating circuit is relatively large. In the prior art shown in FIG. 9, since it is necessary to use four integration / comparing circuits 21 having a large time constant, the circuit becomes large and the manufacturing cost increases. In the present embodiment, since only one integrating circuit is required, the size and cost of the circuit can be reduced. The time constant of the integrating circuit is set in accordance with the cycle of the clock signal, and if there is even one stop of oscillation, it is detected. Abnormalities can be easily confirmed. Even if the oscillation stop is detected once, if the oscillation is restarted, the capacitor 36 is discharged, and the stop detection function can be restarted.

In the case of a timepiece, even if the oscillation is stopped several times, the oscillation may not cause a functional problem if the oscillation is normally performed again. In such a case, the repetitive signal stop detection circuit having the configuration as shown in FIG. 7 sets the time constant to be large and increases the stop detection time t of the generation of the repetitive signal shown in FIGS. It is also possible not to detect the stop when the signal stops for a short period of time. That is, if the time constant is selected to be large, it is possible to detect the stop of the signal generation in a wide range of the repetition signal generation cycle.

The clock signal, which is a reference for the operation of a clock or the like, cannot determine whether or not the clock has stopped even if the signal is generated again normally after the generation of a signal longer than a minute is stopped. In such a case, the output signal of the comparison circuit 38 can be used as a flag indicating that the clock may have stopped in the past.

In the above description, although the repetitive signal is generated from the oscillation circuit, the stop can be similarly detected even if the signal is generated at a predetermined cycle from a series of operations according to a computer program. . Therefore, the present invention can be applied to a watchdog timer or the like.

In the above description, the MO of the switching element is
Although the S-transistor is an N-channel, it can also be realized with a P-channel by changing the circuit configuration. Further, not only MOS transistors but also other switching elements such as bipolar transistors and thyristors can be used similarly.

[0037]

As described above, according to the present invention, the switching element is turned on in response to the level change accompanying the generation of the repetitive signal detected by the change detection circuit, while the level changes, and the switching element is turned on. During a period in which no change is made, the state is a cutoff state. On the output side of the switching element, a capacitor connected in parallel and a resistor for charging the capacitor are provided. When the charging voltage of the capacitor exceeds a preset reference voltage, the comparison circuit derives a signal indicating stoppage of generation of the repetitive signal, so that the repetitive signal can be detected with a simple configuration. As the repetitive signal, only the signal of the detection target of the occurrence stop need be input, and the repetition signal other than the detection target is not required, so that the cost can be significantly reduced. If a repetitive signal not to be detected is used, the signal itself may be stopped. However, since such a signal need not be used, the reliability of detection can be improved.

Further, according to the present invention, since the repetitive signal is an output signal of the oscillation circuit, it is possible to reliably detect the stop of the generation of the clock signal or the like generated at a constant cycle.

According to the present invention, the change detecting circuit includes a buffer for converting the repetitive signal into a rectangular wave, a delay circuit for delaying the output of the buffer, and an exclusive OR of the output of the delay circuit and the output of the buffer. An exclusive OR gate for performing an operation is included, and the configuration can be simplified.
Since the switching element is a MOS transistor, a large change in resistance value can be caused between the conducting state and the blocking state, and the switching element can be easily driven by a logical output from the detection circuit.

According to the present invention, since the change detection circuit, the switching element, and the comparison circuit are formed in the semiconductor integrated circuit chip, they can be mounted in a small size.
Since the integration circuit including the capacitor and the resistor is connected outside the semiconductor integrated circuit chip, the time constant can be easily increased. Further, by adjusting the time constant, it is possible to easily adjust the signal generation stop detection time.

Further, according to the present invention, the repetition signal is a clock signal which is a reference for the operation as a clock. For example, when the generation of the clock signal is stopped and then the signal is generated again, the comparison signal is output. The signal derived by the circuit is
It can be used as a flag indicating that the clock may have stopped in the past.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a repetitive signal stop detection circuit according to an embodiment of the present invention.

2 is an NchMOS transistor 3 according to the embodiment shown in FIG.
It is a block diagram which shows the equivalent circuit when 5 is in an OFF state.

FIG. 3 is an NchMOS transistor 3 according to the embodiment of FIG. 1;
It is a block diagram which shows the equivalent circuit when 5 is in an ON state.

FIG. 4 is a timing chart when a repetitive signal is normally generated in the embodiment of FIG. 1;

FIG. 5 is a timing chart when the output of a buffer 32 is fixed at a high level in the embodiment of FIG. 1;

FIG. 6 is a timing chart when the output of a buffer 32 is fixed at a low level in the embodiment of FIG. 1;

FIG. 7 is an equivalent electric circuit diagram showing a circuit configuration when the embodiment of FIG. 1 is realized by a MOS-LSI.

8 is a graph showing input / output characteristics of the inverter 48 of FIG.

FIG. 9 is a block diagram showing a logical configuration of a related art.

FIG. 10 is a block diagram showing a logical configuration of another prior art.

[Explanation of symbols]

 31 Oscillation Circuit 32 Buffer 33 Delay Circuit 34 Exclusive OR Gate 35 NchMOS Transistor 36 Capacitor 37 Resistance 38 Comparison Circuit 41 LSI

Claims (5)

[Claims] 1. A circuit for detecting a stop of generation of a signal that is repeatedly generated at a predetermined cycle, comprising: a change detection circuit for detecting a level change accompanying the generation of a signal; and a circuit for detecting a level change of a signal detected by the change detection circuit. pls respond,
A switching element that is in a conductive state during a period in which the signal level changes, and is in a non-conductive state during a period in which the signal level does not change, a capacitor connected in parallel to the output side of the switching element, and a DC power supply to charge the capacitor. A resistor connected between one end of the capacitor and a comparison circuit for deriving a signal indicating stop of generation of the repetitive signal when the charged voltage of the capacitor exceeds a preset reference voltage. Signal stop detection circuit. 2. The circuit according to claim 1, wherein the repetition signal is an output signal of an oscillation circuit. 3. A change detection circuit, comprising: a buffer for shaping a repetitive signal into a waveform by converting the waveform to a rectangular wave; a delay circuit for delaying an output of the buffer; and an exclusive OR of an output of the delay circuit and an output of the buffer. The repetitive signal stop detection circuit according to claim 1 or 2, further comprising an exclusive OR gate for performing an operation, wherein the switching element is a MOS transistor. 4. The semiconductor device according to claim 1, wherein the change detection circuit, the switching element, and the comparison circuit are formed in a semiconductor integrated circuit chip, and the capacitor and the resistor are formed as an integration circuit outside the semiconductor integrated circuit chip. Claim 1
4. The repetitive signal stop detection circuit according to any one of claims 1 to 3. 5. The repetitive signal stop detection circuit according to claim 1, wherein the repetitive signal is a clock signal serving as a reference for operation as a clock.