JP2020167548A - Discharge circuit - Google Patents

Abstract

To provide a discharge circuit, for preventing a circuit scale and power consumption from increasing, having good responsiveness, capable of performing discharge.SOLUTION: A bias unit 30 energizes a differential amplifier unit 10 to amplify when an external voltage VDD becomes less than an internal voltage VDDL. In addition, the differential amplifier 10 applies a voltage for causing discharge to take place in a discharge unit 20 when a voltage difference between the external voltage VDD and the internal voltage VDDL becomes greater than a predetermined voltage difference. This causes discharge of stored charge due to the internal voltage VDDL to begin in the discharge unit 20.SELECTED DRAWING: Figure 1

Description

The present invention relates to a discharge circuit.

The following technologies are known as technologies related to the discharge circuit. For example, the discharge circuit described in Patent Document 1 has a function of releasing residual charges.

JP-A-2015-097443

In relation to the above-mentioned functions, the discharge circuit is provided in, for example, a microcomputer circuit that receives power (power supply voltage VDD) from the power supply circuit. When the power circuit is cut off, the voltage in the microcomputer circuit (circuit internal voltage VDDL generated from the power supply voltage VDD) is theoretically similar to the rate of decrease of the power supply voltage VDD, as shown in FIG. Decrease in speed. The circuit internal voltage VDDL continues to decrease and falls below the reset threshold voltage VRST. After that, when the power supply circuit is turned on again, as described above, since the circuit internal voltage VDDL is lower than the reset threshold voltage VRST, the reinitialization of the entire system including the microcomputer circuit is normally performed.

However, the circuit internal voltage VDDL actually decreases gradually as compared with the rate of decrease of the power supply voltage VDD, as shown in FIG. 8, due to the stabilizing capacity and wiring capacity in the microcomputer circuit. .. Therefore, as shown in FIG. 8, if the power supply circuit is turned on again before the circuit internal voltage VDDL falls below the reset threshold voltage VRST, the above-mentioned system reinitialization setting may not be performed normally. There is.

In order to avoid the above situation, in the above-mentioned microcomputer circuit, the activation unit activates the detection unit by detecting that the power supply voltage VDD has started to decrease. Further, the detection unit activates the discharge unit by detecting that the circuit internal voltage VDDL has fallen below a predetermined threshold voltage. The discharge circuit discharges the electric charge already accumulated by the circuit internal voltage VDDL in order to reduce the circuit internal voltage VDDL at high speed. Thereby, as shown in FIG. 7, it is possible to ensure that the circuit internal voltage VDDL is lower than the reset threshold voltage VRST.

However, since the above-mentioned microcomputer circuit requires the above-mentioned start-up part and detection part in addition to the discharge part, the circuit scale and power consumption are large, and the circuit is operated with low current consumption. As a result, there is a problem that the time required for the above-mentioned activation becomes long, that is, the responsiveness deteriorates.

An object of the present invention is to provide a discharge circuit which does not increase the circuit scale and power consumption, has good responsiveness, and can perform discharge.

In order to solve the above-mentioned problems, the discharge circuit according to the present invention
A discharge unit that discharges the accumulated charge due to the second voltage generated from the first voltage when a control voltage higher than a predetermined voltage is supplied.
When a control current larger than a predetermined current is supplied, the differential amplification unit supplies the voltage obtained by amplifying the voltage difference between the first voltage and the second voltage to the discharge unit as the control voltage. When,
A bias portion that supplies the control current larger than the predetermined current to the differential amplifier when the first voltage becomes lower than the second voltage.
including.

According to the discharge circuit according to the present invention, the bias portion supplies the differential amplifier with the control current larger than the predetermined current when the first voltage becomes lower than the second voltage. When the differential amplification unit receives the supply of the control current larger than the predetermined current, the differential amplification unit uses the voltage obtained by amplifying the voltage difference between the first voltage and the second voltage as the control voltage. It is supplied to the discharge unit, and the discharge unit discharges the charge accumulated due to the second voltage generated from the first voltage when the control voltage higher than the predetermined voltage is supplied. To do. As a result, the discharge circuit according to the present invention can perform the discharge without using the conventional drive unit and detection unit, and as a result, the circuit scale and power consumption of the discharge circuit are reduced as compared with the conventional one. At the same time, it is possible to improve the responsiveness as compared with the conventional case.

The configuration of the differential amplification unit according to the embodiment of the present invention is shown. The configuration of the discharge circuit according to the embodiment of the present invention is shown. The operation of the discharge circuit according to the embodiment of the present invention is shown. The configuration of the differential amplification unit according to the embodiment of the present invention is shown. The configuration of the differential amplification unit according to the first modification of the present invention is shown. The configuration of the differential amplification unit according to the second modification of the present invention is shown. The theoretical waveforms of the power supply voltage and the circuit internal voltage when the power supply circuit is cut off and turned on again are shown. The actual waveforms of the power supply voltage and the circuit internal voltage when the power supply circuit is cut off and turned on again are shown.

<Embodiment>
Hereinafter, the discharge circuit according to the embodiment of the present invention will be described with reference to the drawings.

<Structure of Embodiment>
FIG. 1 shows the configuration of the differential amplification unit according to the embodiment. FIG. 2 shows the configuration of the discharge circuit according to the embodiment. As shown in FIG. 2, the discharge circuit 1 of the embodiment monitors the external voltage VDD applied from the outside, and the external voltage VDD is based on the internal voltage VDDL (voltage generated by the regulator 40 described later from the external voltage VDD). The basic concept is to start discharging the electric charge already accumulated in the capacitor 50 by the internal voltage VDDL when the voltage becomes low. Under this concept, the discharge circuit 1 includes a differential amplification unit 10, a discharge unit 20, a bias unit 30, a regulator 40, and a capacitor 50, as shown in FIG. Here, the external voltage VDD corresponds to the "first voltage", and the internal voltage VDDL corresponds to the "second voltage".

The current-driven differential amplification unit 10 and the discharge unit 20 are schematically represented integrally as one differential amplification unit 100, as shown in FIG. The differential amplifier unit 100 has two input terminals in + and in−, one output terminal Vout, two power supply terminals VDD and GND (grounded), and two control terminals pgnb and ibp.

The differential amplification unit 100 amplifies the voltage difference between the voltage input to the input terminal in + (same as VDD) and the voltage input to the input terminal in− (same as voltage VDDL), and increases the voltage after amplification. Depending on the size, discharge or stop.

The control terminal pgnb is used to determine a monitoring point for monitoring fluctuations in the external voltage VDD. The control terminal ibp is used to control the operation (started state, near non-started state) of the differential amplification unit 100 by an electric current.

Moving to FIG. 2, in the differential amplification unit 10, the input terminal in + is connected to the control terminal pgnb, whereby the voltage VDD supplied to the control terminal pgnb is applied to the input terminal in +. As described above, the voltage of the output terminal Vout (same as the internal voltage VDDL) is applied to the input terminal in−. The control terminal ibp is connected to the bias unit 30, and the current from the bias unit 30 is large enough to allow the differential amplification unit 10 to operate sufficiently, or the size is such that the operation does not stop. Is supplied with current. The output terminal of the differential amplification unit 10 is connected to the discharge unit 20, and more specifically, it is connected to the gate of the MOS transistor in the discharge unit 20, for example.

When a voltage large enough to activate the discharge unit 20 (more accurately, a MOS transistor) is applied from the differential amplification unit 10 to the capacitor 50 due to the internal voltage VDDL. It has a function to discharge the accumulated charge. In order to fulfill this function, in the MOS transistor of the discharge unit 20, its drain is connected to one electrode of the output end of the regulator 40 and the capacitor 50, and its source and its back gate are the ground potential and the capacitor. It is connected to the other electrode of 50. Here, the voltage output by the differential amplification unit 10 corresponds to the "control voltage".

The bias unit 30 receives inputs of voltage Vref1 (same as external voltage VDD) and voltage Vref2 (same as internal voltage VDDL), and outputs current ibp. The bias unit 30 supplies the differential amplification unit 10 with a current ibp having a magnitude such that the operation of the differential amplification unit 10 does not stop in a normal state, that is, when the external voltage VDD is larger than the internal voltage VDDL. On the other hand, the bias unit 30 sufficiently operates the differential amplification unit 10 when the power supply circuit (not shown) for supplying the external voltage VDD is cut off, that is, when the external voltage VDD is smaller than the internal voltage VDDL. A current ibp having a magnitude that can be generated is supplied to the differential amplification unit 10. Here, the current ibp corresponds to the "control current".

As described above, the regulator 40 generates the internal voltage VDDL from the external voltage VDD, and outputs the generated internal voltage VDDL from the terminal Vout.

The capacitor 50 is connected between the output end of the regulator 40 and the ground potential in order to smooth the internal voltage VDDL output from the regulator 40.

<Structure of Embodiment>
FIG. 3 shows the operation of the discharge circuit according to the embodiment. The operation of the discharge circuit of the embodiment will be described below with reference to FIG. In the following, it is assumed that the external voltage VDD is initially larger than the internal voltage VDDL and then starts to decrease at time t1. Further, it is assumed that the discharge unit 20 is initially in a non-started state (off state).

Since the external voltage VDD is larger than the internal voltage VDDL until the time t1, the bias unit 30 does not drive the differential amplification unit 10 by using the current ibp. More specifically, the bias unit 30 supplies the differential amplifier unit 10 with a current ibp having a size that does not stop the operation of the differential amplifier unit 10.

At time t1, the external voltage VDD begins to decrease. After time t1, the internal voltage VDDL also begins to decrease due to the influence of the external voltage VDD.

At time t2, the external voltage VDD becomes smaller than the internal voltage VDDL. As a result, the bias unit 30 supplies the differential amplifier unit 10 with a current ibp having a size that allows the differential amplifier unit 10 to operate sufficiently. When the current ibp is supplied, the differential amplification unit 10 starts the operation of the differential amplification.

After time t2, the external voltage VDD continues to decrease. As a result, the voltage difference between the external voltage VDD and the internal voltage VDDL becomes larger than the predetermined voltage difference. Here, the "predetermined voltage difference" means, for example, that if the predetermined voltage difference is amplified, the amplified voltage can activate the MOS transistor in the discharge unit 20. Refers to the voltage difference that will have. At this point, the differential amplification unit 10 outputs a voltage capable of activating the MOS transistor to the gate of the MOS transistor in the discharge unit 20. In response to this voltage, the discharge unit 20 starts the discharge operation by entering the activated state (on state), that is, starts discharging the electric charge accumulated in the capacitor 50 by that time. ..

At time t3, the internal voltage VDDL falls below the voltage at which each part in the discharge circuit 1 can operate. As a result, for example, the differential amplification unit 10 cannot output a voltage large enough to drive (on the state) the discharge unit 20. As a result, the discharge unit 20 is in a non-started state (off state), that is, the discharge is stopped.

<Effect of embodiment>
As described above, in the discharge circuit 1 according to the embodiment, when the external voltage VDD becomes smaller than the internal voltage VDDL, the bias unit 30 transmits a current ibp large enough to allow the differential amplification unit 10 to operate sufficiently. The dynamic amplification unit 10 is energized. Further, when the voltage difference between the external voltage VDD and the internal voltage VDDL becomes larger than the predetermined voltage, the differential amplification unit 10 outputs a voltage large enough for the discharge unit 20 to operate to the discharge unit 20. .. As a result, the discharge unit 20 can start discharging the charges accumulated in the capacitor 50 up to that point due to the internal voltage VDDL. In other words, the discharge unit 20 does not require the drive unit and the detection unit required for the conventional discharge circuit, that is, the circuit scale and power consumption are smaller than those of the conventional one, and the responsiveness is good. Below, the discharge can be started.

<Concrete example>
FIG. 4 is an equivalent circuit diagram showing a specific configuration of the differential amplification unit. Hereinafter, a specific configuration of the differential amplification unit will be described with reference to FIG.

<Structure of specific example>
The differential amplification unit 100A shown in FIG. 4 is a P-channel type MOS as shown in FIG. 4 in order to realize the differential amplification unit 100 shown in FIG. 1 with a circuit element (transistor, capacitor, etc.). (Metal Oxide Semiconductor) Transistors P1 to P7 (hereinafter, abbreviated as "transistor P1"), N-channel MOS transistors N1 to N7 (hereinafter, abbreviated as "transistor N1"), and a capacitor C1. , C2 and.

The transistors P1 and N4 have a source grounded configuration in order to perform inverting amplification, and are connected in series between the external voltage VDD and the ground potential.

Regarding the transistor P1, the source and the back gate are connected to the external voltage VDD, the gate is connected to the drain of the transistor P2 and the drain of the transistor N1, and the drain is the control terminal ibp (bias portion 30 (FIG. 2). The output end) and the drain of the transistor N4 are connected, and the capacitor C1 is connected between the gate and the drain.

For transistor N4, the gate is connected to the gate of transistor N5, the drain and gate are connected to each other, and the source and back gate are connected to the ground potential.

The transistors P2, P4, N1 and N3 have a first differential amplification function. Further, the transistors P3, P4, N2 and N3 have a second differential amplification function. For example, regarding the relationship between the transistor P2 and the transistor N1, the source and the back gate of the transistor P2 are connected to the external voltage VDD, the gate is connected to the gate of the transistor P3 and the gate of the transistor P4, and the drain. Is connected to the drain of the transistor N1, the source of the transistor N1, the source of the transistor N2, and the source of the transistor N3 are connected to each other and are connected to the drain of the transistor N5.

The relationship between the transistor P3 and the transistor N2, the relationship between the transistor P4 and the transistor N3, and the like are the same as the relationship with the transistor P2 and the transistor N1 described above.

Further, the gate of the transistor N1 and the gate of the transistor N2 are connected to the terminal in−, the gate of the transistor N3 is connected to the terminal in +, and the back gate of the transistor N2 and the back gate of the transistor N3 are grounded. It is connected to the electric potential.

The gates of the transistors P3 and P4, the drains of the transistors P4 and N3, the gate of the transistor P5, and the terminal pgnb are connected to each other. Here, the terminal pgnb and the terminal in + are connected to each other as shown in FIG. 2 (not shown in FIG. 4).

For the transistor P5, the source and backgate are connected to the external voltage VDD, and the drain is connected to the drain of the transistor N6.

For the transistor P6, the gate is connected to each of the drains of the transistors P3 and N2, the source and the back gate are connected to the power supply voltage VDD, and the drains are the drain of the transistor N7, the gate of the transistor N8, and the drain. , Is connected to one electrode of the capacitor C2.

The transistor N6 and the transistor N7 have a function of a current sink. For transistor N6, the gate and drain are connected to each other, the gate is connected to the gate of transistor N7, and the source and back gate are connected to the ground potential.

For transistor N7, the source and backgate are connected to the ground potential. Here, regarding the characteristics of the transistor N7, the threshold voltage thereof is smaller than the threshold voltage of the other transistors.

For transistor P7, the gate is connected to an external voltage VDD, the source and backgate are connected to the output terminal Vout, the other electrode of capacitor C2, and the drain of transistor N8, and the drain is grounded. It is connected to the electric potential.

For transistor N8, the source and backgate are connected to the ground potential.

<Operation of specific example>
The operation of the differential amplification unit according to the embodiment will be described.

1. 1. When the external voltage VDD is higher than the internal voltage VDDL (when the voltage at terminal in + is higher than the voltage at terminal in−)
The transistor P5 is in the cutoff state, and therefore the transistors N6 and N7 are also in the cutoff state. As a result, the transistor N8 is in the cutoff state, that is, the drain of the transistor N8 is in the open state. As a result, as shown in FIG. 2, an internal voltage VDDL, which is a voltage output by the regulator 40, is applied to the output terminal Vout.

2. When the external voltage VDD becomes lower than the internal voltage VDDL (when the voltage at the terminal in + becomes lower than the voltage at the terminal in−)
When the external voltage VDD becomes lower than the internal voltage VDDL, the transistors P2 and P3 are brought into a conductive state. Due to the continuity of the former transistor P2, the transistor P1 is brought into a conductive state. On the other hand, the conduction of the latter transistor P3 puts the transistor P6 in a conductive state, and the conduction of the transistor P6 puts the transistor N8 in a conductive state.

In addition to the above, when the external voltage VDD becomes lower than the internal voltage VDDL, the transistors N1 and N2 are brought into a conductive state, and the transistors P7 are brought into a conductive state.

Due to the continuity of the transistor N8 and the continuity of the transistor P7 described above, the transistors N8 and N7 start to discharge the electric charge accumulated in the capacitor 50 (shown in FIG. 2). In addition, since the threshold voltage of the transistor P7 is lower than the threshold voltage of the other transistor, the internal voltage VDDL has dropped to such an extent that the other transistor cannot operate after the time t3 (shown in FIG. 3). Even after that, the discharge operation can be continued.

As for the power source of the current-driven differential amplification unit 100A, since a small amount of current ibp continues to flow, the voltage of each gate of the transistors N4 and N5 becomes high, and as a result, the transistors N4, N5 becomes a conductive state. Due to the continuity of the transistors N4 and N5, a large current flows through the paths passing through the transistors P1 and N4 and the paths passing through the transistors P2, N1 and N5.

<Modification example 1>
FIG. 5 shows the configuration of the differential amplification unit according to the first modification. Hereinafter, the differential amplification unit of the first modification will be described with reference to FIG.

The differential amplification unit 100B of the first modification basically has the same configuration as the differential amplification unit 100A of the specific example. On the other hand, the differential amplification unit 100B of the first modification, unlike the differential amplification unit 100A of the specific example, further includes three resistors R2, R3, and R4. The resistors R2, R3 and R4 have resistance values r2Ω, r3Ω and r4Ω. Further, in order to facilitate the explanation and understanding of the modified example 1, the threshold voltage of the transistor will not be considered. Here, the three resistors R2, R3, and R4 correspond to the "voltage drop portion".

The resistor R4 is provided between the drain of the transistor P4 and the drain of the transistor N3. Since the differential amplification unit 100B also has two differential amplification functions like the differential amplification unit 100A of the specific example, the resistor R2 is provided between the drain of the transistor P2 and the drain of the transistor N1. Further, a resistor R3 is provided between the drain of the transistor P3 and the drain of the transistor N2.

Assuming that the current Ids4 flows through the transistor P4 by providing the resistor R4, the voltage of the terminal pgnb is obtained by subtracting the voltage dropped by the resistor R4, that is, r4 × Ids4 from the external voltage VDD. The voltage becomes [VDD-r4 × Ids4].

The terminal in + and the terminal pgnb are connected to each other as shown in FIG. Therefore, in the differential amplification unit 100A of the specific example, the voltage of the drain of the transistor P4, which is the voltage applied to the terminal pgnb, that is, the power supply voltage VDD is applied to the terminal in + with the same magnitude. In contrast, in the differential amplification unit 100B of the first modification, a voltage [VDD-R4 × Ids4] smaller than the power supply voltage VDD is applied to the terminal in + instead of the power supply voltage VDD in the specific example. As a result, the timing at which the discharge is started, which is the time when the power supply voltage VDD falls below the internal voltage VDDL, can be accelerated. Further, by changing the resistance values of the resistors R4, R2, and R3, the above timing can be adjusted. More specifically, if the resistance value is increased, the above-mentioned timing can be greatly accelerated, and conversely, if the resistance value is decreased, the above-mentioned timing can be shortened. The resistors R2, R3, and R4 may be configured by using a variable resistor having a variable resistance value.
<Modification 2>
FIG. 6 shows the configuration of the differential amplification unit according to the second modification. Hereinafter, the differential amplification unit of the second modification will be described with reference to FIG.

The differential amplification unit 100C of the second modification basically has a configuration common to the differential amplification unit 100A of the specific example and the differential amplification unit 100B of the first modification. On the other hand, the differential amplification unit 100C of the modification 2 is different from the differential amplification unit 100B of the modification 1, and instead of the three resistors R2, R3, R4, the transistors P2-1 to P2-3, Includes transistors P3-1 to P3-3 and transistors P4-1 to P4-3. Here, the transistors P2-1 to P2-3, the transistors P3-1 to P3-3, and the transistors P4-1 to P4-3 correspond to the "voltage drop section".

Transistors P4-1 to P4-3 are provided between the drain of the transistor P4 and the drain of the transistor N3, and are cascode-connected (longitudinal connection) to each other, similarly to the resistor R4 in the first modification. .. Further, the back gates of the transistors P4 and P4-1 to P4-3 are connected to each other and are connected to the external voltage VDD.

Since the differential amplification unit 100C also has two differential amplification functions, the transistors P2-1 to P2-3 are provided between the drain of the transistor P2 and the drain of the transistor N1, and are cascode-connected to each other. There is. Further, the back gates of the transistors P2 and P2-1 to P2-3 are connected to each other and are connected to the external voltage VDD. Similarly, the transistors P3-1 to P3-3 are provided between the drain of the transistor P3 and the drain of the transistor N2, and are cascode-connected to each other. Further, the back gates of the transistors P3 and P3-1 to P3-3 are connected to each other and are connected to the external voltage VDD.

By providing the cascode-connected transistors P4-1 to P4-3, the voltage applied to the terminal pgnb, that is, the terminal in + is set to the transistors P4-1 to P4 rather than the external voltage VDD, as in the first modification. It can be set lower by the sum of the threshold voltages of -3. As a result, it is possible to advance the timing of starting the discharge as in the modification example 1. In addition, by changing the number of transistors connected in cascade, it is possible to adjust the timing at which the discharge is started as described above. More specifically, if the number of cascade-connected transistors is increased, the above-mentioned timing can be greatly accelerated, and conversely, if the number of cascade-connected transistors is reduced, the above-mentioned timing can be greatly accelerated.

<Other inventions>
The other discharge circuit according to the present invention is
A discharge unit that discharges the electric charge accumulated due to the internal voltage used internally, which is generated from an external voltage applied from the outside, and for controlling the permission or prohibition of the discharge of the discharge unit. The discharge unit that receives the control voltage of
The control voltage is generated by receiving the input of the external voltage and the internal voltage and amplifying the voltage difference between the external voltage and the internal voltage, and the voltage difference becomes larger than a predetermined voltage difference. At that time, the differential amplification unit that applies the control voltage that allows the discharge by the discharge unit to the discharge unit, and the control current for controlling the permission or prohibition of the amplification of the differential amplification unit. The differential amplification unit that receives energization and
When the external voltage becomes smaller than the internal voltage, the bias unit that energizes the differential amplifier unit with the control current that allows the amplification by the differential amplifier unit.
including.

According to another discharge circuit according to the present invention, when the external voltage becomes smaller than the internal voltage, the bias unit applies the control current that allows the amplification by the differential amplification unit to the differential amplification unit. When the voltage difference between the external voltage and the internal voltage becomes larger than a predetermined voltage difference, the differential amplification unit permits the discharge by the discharge unit. A voltage is applied to the discharge unit. As a result, the discharge unit starts to discharge the electric charge accumulated due to the internal voltage. Therefore, unlike the conventional discharge circuit, the discharge circuit according to the present invention can perform the discharge without using the drive unit and the detection unit, and as a result, the circuit scale and power consumption of the discharge circuit are compared with those of the conventional one. It is possible to make the size smaller, and at the same time, it is possible to improve the responsiveness as compared with the conventional case.

1 Discharge circuit, 10 differential amplifier, 20 discharge, 30 bias, 40 regulator, 50 capacitor, 100 differential amplifier unit

Claims (4)

A discharge unit that discharges the accumulated charge due to the second voltage generated from the first voltage when a control voltage higher than a predetermined voltage is supplied.
When a control current larger than a predetermined current is supplied, the differential amplification unit supplies the voltage obtained by amplifying the voltage difference between the first voltage and the second voltage to the discharge unit as the control voltage. When,
A bias portion that supplies the control current larger than the predetermined current to the differential amplifier when the first voltage becomes lower than the second voltage.
Discharge circuit including. The differential amplification unit has a voltage drop unit that lowers the first voltage, and controls the voltage obtained by amplifying the voltage difference between the first voltage and the second voltage dropped by the voltage drop unit. The discharge circuit according to claim 1, which outputs a voltage. The discharge circuit according to claim 2, wherein the voltage drop portion includes a resistor. The discharge circuit according to claim 2, wherein the voltage drop portion includes a plurality of transistors connected in cascade.