JP6079184B2 - Regulator circuit - Google Patents

Description

  The present invention relates to a regulator circuit that outputs a predetermined voltage.

  FIG. 5 shows a circuit configuration diagram of an example of a conventional regulator circuit. This regulator circuit is a semiconductor integrated circuit and is a low current consumption circuit with a current consumption of about 1 μA.

  In FIG. 5, the power supply terminal 2 is connected to one end of an external DC power supply 1 and one end of a capacitor C1, and the other end of the DC power supply 1 and the capacitor C1 is grounded. A control signal for switching on / off of the regulator circuit is supplied to the control terminal 3 from the outside, and this control signal is supplied to the constant current circuit 5. The ground terminal 4 is grounded.

  One end of the constant current circuit 5 is connected to the power supply terminal 2, and the other end of the constant current circuit 5 is connected to the gate of the n-channel MOS transistor N 1 constituting the error amplifier and one end of the reference voltage circuit 6. The other end of the reference voltage circuit 6 is connected to the ground terminal 4. The sources of the n-channel MOS transistors N 1 and N 2 are connected in common and connected to one end of the constant current circuit 7, and the other end of the constant current circuit 7 is connected to the ground terminal 4.

  The drain of the MOS transistor N1 is connected to the drain of the p-channel MOS transistor and the gate of the MOS transistor P3 as the output transistor. The drain of the MOS transistor N2 is connected to the drain of the p-channel MOS transistor P2 and the gates of the MOS transistors P1 and P2. The sources of the MOS transistors P1, P2, P3 are connected to the power supply terminal 2. The p-channel MOS transistors P1 and P2 constitute a current mirror circuit.

  The drain of the MOS transistor P3 is connected to the output terminal 8. The output terminal 8 is connected to one end of an external capacitor C2, and the other end of the capacitor C2 is grounded. The output terminal 8 and the ground terminal 4 are connected by resistors R1 and R2 connected in series. The connection point between the resistors R1 and R2 is connected to the gate of the MOS transistor N2.

  The gate of the MOS transistor N1 is connected to one end of the reference voltage circuit 6 and supplied with a reference voltage, and the gate of the MOS transistor N2 is connected to the connection point of the resistors R1 and R2. The MOS transistors N1 and N2 constitute a differential circuit, which amplifies the difference voltage between the feedback voltage at the connection point of the resistors R1 and R2 and the reference voltage, and amplifies the drain voltage of the MOS transistor N1, that is, the difference voltage. The output voltage is supplied to the output transistor, that is, the gate of the MOS transistor P3 to control the drain current of the MOS transistor P3, thereby maintaining the output terminal voltage at a predetermined voltage.

  By the way, when the regulator circuit is turned on, an overshoot occurs at the output terminal due to the parasitic capacitance at the control electrode (gate or base) of the output transistor, so that the control electrode has a resistor, a capacitor, and A time constant circuit composed of control transistors is connected, and the parasitic capacitance is instantaneously charged by the control transistor when the power is turned on. Thereafter, the control transistor is gradually turned off, so that the output transistor rises when the power is turned on. There is a technique for slowing down and suppressing overshoot (see Patent Document 1).

JP 2004-252891 A

  When the regulator circuit shown in FIG. 5 is off, the control terminal 3 is at low level, the MOS transistor P3 is off, and the output terminal 8 is at ground level. Here, when a high-level control signal is supplied to the control terminal 3 at time t0, the voltage of the power supply terminal 2 rises as shown in FIG. 6A, and the voltage Va at the point A that is the gate of the MOS transistor P3. Rises as shown in FIG.

  During the period from time t0 to time t1, the voltage Va at the point A that is the gate of the MOS transistor P3 is at a low level. Further, after time t1, the voltage Va at the point A, which is the gate of the MOS transistor P3, is at a high level. In order to charge the parasitic capacitance between the gate and the source or back gate of the MOS transistor P3 with a current (bias current) of 1 μA or less of the constant current circuit 7 during the period t1 to t2 when the voltage Va changes from the low level to the high level. The output voltage VOUT exceeds a predetermined voltage set as a regulator circuit, and overshoot occurs. In particular, in the case of a light load, the transition period during which the voltage Va changes from low level to high level becomes long, and the maximum overshoot value becomes large. In such a case, there is a problem that the overshoot exceeds the breakdown voltage of the device connected as a load to the output terminal 8 and the device may be destroyed.

  In addition, the technique described in Patent Document 1 has a problem that the control transistor is turned on when the power supply voltage fluctuates in the normal operation state after the power is turned on, and noise may be mixed into the output voltage or oscillation may occur. .

  The present invention has been made in view of the above points, and an object thereof is to provide a regulator circuit that suppresses the occurrence of overshoot.

A regulator circuit according to an embodiment of the present invention includes a reference voltage unit ( 16) that is supplied with power and generates a reference voltage;
A differential amplifying unit (P11, P12, N11, N12, 17) for amplifying the difference voltage between the voltage according to the output voltage and the reference voltage;
In a regulator circuit having an output transistor (P13) that varies the output voltage in accordance with the voltage of the difference supplied with the power and amplified by the differential amplifier.
A comparator (21) to which the reference voltage is supplied to one input terminal and a voltage corresponding to the output voltage is supplied to the other input terminal;
A capacitor (C21) having one terminal connected to the output terminal of the comparator and the other terminal connected to the power supply via a current supply circuit (P21, P22);
Have
The comparator, when the voltage according to the output voltage is lower than the reference voltage, when the output is low level, the charging current flows through the capacitor,
The current supply circuit supplies a current corresponding to the charging current flowing through the capacitor to a control terminal of the output transistor.

Preferably, the current supply circuit includes a first transistor (P21) through which a charging current of the capacitor flows,
It is a current mirror circuit composed of a second transistor (P22) through which a current corresponding to the charging current of the capacitor flows.

Preferably, the current supply circuit includes a first resistor (R21) through which a charging current of the capacitor flows,
A second transistor (P22) through which a current corresponding to a voltage drop of the first resistor flows is formed.

Preferably, the current supply circuit causes a charging current of the capacitor to flow through the first transistor (P21) when a voltage corresponding to the output voltage is lower than the reference voltage, and a voltage corresponding to the output voltage is A third transistor (P23) is further bypassed so that the charging current of the capacitor does not flow through the first transistor except when it is lower than the reference voltage .

  Note that the reference numerals in the parentheses are given for ease of understanding, are merely examples, and are not limited to the illustrated modes.

  According to the present invention, the occurrence of overshoot can be suppressed.

It is a circuit block diagram of one Embodiment of the regulator circuit of this invention. FIG. 2 is a signal waveform diagram of each part of the circuit in FIG. 1. It is a circuit block diagram of the 1st modification of one Embodiment of the regulator circuit of this invention. It is a circuit block diagram of the 2nd modification of one Embodiment of the regulator circuit of this invention. It is a circuit block diagram of an example of the conventional regulator circuit. FIG. 6 is a signal waveform diagram of each part of the circuit in FIG. 5.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Embodiment>
FIG. 1 shows a circuit configuration diagram of an embodiment of a regulator circuit of the present invention. This regulator circuit is a semiconductor integrated circuit and is a low current consumption circuit with a current consumption of about 1 μA.

  In FIG. 1, the power supply terminal 12 is connected to one end of an external DC power supply 11 and one end of a capacitor C11, and the other end of the DC power supply 11 and the capacitor C11 is grounded. A control signal for switching on / off of the regulator circuit is supplied to the control terminal 13 from the outside, and this control signal is supplied to the constant current circuit 15. The ground terminal 14 is grounded.

  One end of the constant current circuit 15 is connected to the power supply terminal 12, and the other end of the constant current circuit 15 is the gate of the n-channel MOS transistor N11 constituting the error amplifier, one end of the reference voltage circuit 16, and the comparator constituting the current compensation circuit 20A. 21 is connected to the inverting input terminal. The other end of the reference voltage circuit 16 is connected to the ground terminal 14. The sources of the n-channel MOS transistors N11 and N12 are connected in common and connected to one end of the constant current circuit 17, and the other end of the constant current circuit 17 is connected to the ground terminal 14.

  The drain of the MOS transistor N11 is connected to the drain of the p-channel MOS transistor P11 and the gate which is the control terminal of the MOS transistor P13 as an output transistor. The drain of the MOS transistor N12 is connected to the drain of the p-channel MOS transistor P12 and the gates of the MOS transistors P11 and P12. The sources of the MOS transistors P11, P12, P13 are connected to the power supply terminal 12. The p-channel MOS transistors P11 and P12 constitute a current mirror circuit.

  The drain of the MOS transistor P13 is connected to the output terminal 18. The output terminal 18 is connected to one end of an external capacitor C12, and the other end of the capacitor C12 is grounded. The output terminal 18 and the ground terminal 14 are connected by resistors R11 and R12 connected in series. The connection point of the resistors R11 and R12 is connected to the gate of the MOS transistor N12. That is, the resistors R11 and R12 divide the output voltage of the output terminal 18 and supply it to the gate of the MOS transistor N12.

  The gate of the MOS transistor N11 is connected to one end of the reference voltage circuit 16 and supplied with the reference voltage Vref, and the gate of the MOS transistor N12 is connected to the connection point of the resistors R11 and R12. The MOS transistors N11 and N12 constitute a differential circuit, which amplifies the difference voltage between the feedback voltage Vfb at the connection point of the resistors R11 and R12 and the reference voltage Vref, and thus the drain voltage of the MOS transistor N11, that is, the difference voltage. Is supplied to the gate of the MOS transistor P13, that is, the control terminal of the output transistor, and the drain current of the MOS transistor P13 is controlled to maintain the output terminal voltage at a predetermined voltage.

  The current compensation circuit 20A includes a comparator 21, a capacitor C21, and p-channel MOS transistors P21 and P22 that constitute a current mirror circuit as a current supply circuit. The comparator 21 is a comparator with an offset. The comparator 21 has its inverting input terminal connected to the gate of the MOS transistor N11 and supplied with the reference voltage Vref, and its non-inverting input terminal connected to the connection point of the resistors R11 and R12 and supplied with the feedback voltage Vfb. The comparator 21 outputs a low level signal when the feedback voltage Vfb is less than a voltage lower than the reference voltage Vref by the offset voltage Voff (Vfb <Vref−Voff), and outputs a high level signal when the feedback voltage Vfb is above (Vfb> Vref−Voff). To do.

  The output terminal of the comparator 21 is connected to one end of the capacitor C21, and the other end of the capacitor C21 is connected to the gate and drain of the p-channel MOS transistor P21 and to the gate of the p-channel MOS transistor P22.

  The sources of the MOS transistors P21 and P22 are connected to the power supply terminal 12, and the drain of the MOS transistor P22 is connected to the gate of the MOS transistor P13. When the output of the comparator 21 is at a low level, a charging current for the capacitor C21 flows. A current corresponding to the charging current is supplied from the drain of the MOS transistor P22 to the point A which is the gate of the MOS transistor P13.

  When the regulator circuit is off, the control terminal 3 is at low level, the MOS transistor P13 is off, and the output terminal 18 is at ground level. Here, when a high-level control signal is supplied to the control terminal 13 at time t10 and power supply is started, the voltage at the power supply terminal 12 changes as shown in FIG. 2A, and the voltage at the gate of the MOS transistor P3 changes. The voltage Va at a certain point A changes as shown in FIG. 2C, and the voltage Vb output from the comparator 21 changes as shown in FIG. Further, FIG. 2D shows changes in the reference voltage Vref and the feedback voltage Vfb.

  During the period from time t10 to time t11, a relationship of Vfb <Vref−Voff is established, the output of the comparator 21 is at a low level, and the capacitor C21 is charged with the current supplied from the MOS transistor P21. A current corresponding to the charging current of the capacitor C21 flows from the drain of the MOS transistor P22 to the gate of the MOS transistor P13. The drain current of the MOS transistor P22 is added to a current (bias current) of 1 μA or less in the constant current circuit 17, and the parasitic capacitance between the gate and the source or back gate of the MOS transistor P13 is rapidly charged.

  After time t11, a relationship of Vfb> Vref−Voff is established, the output of the comparator 21 is at a high level, and charging of the capacitor C21 is stopped. Then, after a slight delay in response from time t11, charging of the parasitic capacitance of the MOS transistor P13 ends at time t12.

  For this reason, the period during which overshoot occurs and increases in the output voltage VOUT can be suppressed to a very short period from time t11 to time t12, and the maximum value of overshoot can be reduced. Therefore, it is possible to prevent the overshoot maximum value from exceeding the breakdown voltage of the device connected to the output terminal 18 as a load. Thereby, destruction of the device can be prevented. Note that by changing the setting of the offset voltage Voff of the comparator 21, it is possible to adjust the minute period from time t11 to time t12.

  Further, when the output of the comparator 21 becomes high level after the power is turned on, the voltage across the capacitor C21 becomes VDD and charging of the capacitor C21 is stopped, so that no current is supplied from the MOS transistor 22 to the point A. There is no risk of noise mixing or oscillation in the output voltage.

<First Modification>
FIG. 3 shows a circuit configuration diagram of a first modification of one embodiment of the regulator circuit of the present invention. In FIG. 3, the power supply terminal 12 is connected to one end of an external DC power supply 11 and one end of a capacitor C11, and the other end of the DC power supply 11 and the capacitor C11 is grounded. A control signal for switching on / off of the regulator circuit is supplied to the control terminal 13 from the outside, and this control signal is supplied to the constant current circuit 15. The ground terminal 14 is grounded.

  One end of the constant current circuit 15 is connected to the power supply terminal 12, and the other end of the constant current circuit 15 is the gate of the n-channel MOS transistor N11 constituting the error amplifier, one end of the reference voltage circuit 16, and a comparator constituting the current compensation circuit 20B. 21 is connected to the inverting input terminal. The other end of the reference voltage circuit 16 is connected to the ground terminal 14. The sources of the n-channel MOS transistors N11 and N12 are connected in common and connected to one end of the constant current circuit 17, and the other end of the constant current circuit 17 is connected to the ground terminal 14.

  The drain of the MOS transistor N11 is connected to the drain of the p-channel MOS transistor P11 and the gate of the MOS transistor P13 as an output transistor. The drain of the MOS transistor N12 is connected to the drain of the p-channel MOS transistor P12 and the gates of the MOS transistors P11 and P12. The sources of the MOS transistors P11, P12, P13 are connected to the power supply terminal 12. The p-channel MOS transistors P11 and P12 constitute a current mirror circuit.

  The drain of the MOS transistor P13 is connected to the output terminal 18. The output terminal 18 is connected to one end of an external capacitor C12, and the other end of the capacitor C12 is grounded. The output terminal 18 and the ground terminal 14 are connected by resistors R11 and R12 connected in series. The connection point of the resistors R11 and R12 is connected to the gate of the MOS transistor N12.

  The gate of the MOS transistor N11 is connected to one end of the reference voltage circuit 16 and supplied with the reference voltage Vref, and the gate of the MOS transistor N12 is connected to the connection point of the resistors R11 and R12. The MOS transistors N11 and N12 constitute a differential circuit, which amplifies the difference voltage between the feedback voltage Vfb at the connection point of the resistors R11 and R12 and the reference voltage Vref, and thus the drain voltage of the MOS transistor N11, that is, the difference voltage. Is supplied to the output transistor, that is, the gate of the MOS transistor P13 to control the drain current of the MOS transistor P13, thereby maintaining the output terminal voltage at a predetermined voltage.

  The current compensation circuit 20B includes a comparator 21, a capacitor C21, a resistor R21, and a p-channel MOS transistor P22. The comparator 21 is a comparator with an offset. The comparator 21 has its inverting input terminal connected to the gate of the MOS transistor N11 and supplied with the reference voltage Vref, and its non-inverting input terminal connected to the connection point of the resistors R11 and R12 and supplied with the feedback voltage Vfb. The comparator 21 outputs a low level signal when the feedback voltage Vfb is less than a voltage lower than the reference voltage Vref by the offset voltage Voff (Vfb <Vref−Voff), and outputs a high level signal when the feedback voltage Vfb is above (Vfb> Vref−Voff). To do.

  The output terminal of the comparator 21 is connected to one end of the capacitor C21, and the other end of the capacitor C21 is connected to the power supply terminal 12 via the resistor R21 and to the gate of the MOS transistor P22. The source of the MOS transistor P22 is connected to the power supply terminal 12, and the drain of the MOS transistor P22 is connected to the gate of the MOS transistor P13.

  Also in the first modification, the charging current of the capacitor C21 flows when the output of the comparator 21 is at a low level. The drain current of the MOS transistor P22 is supplied to the point A which is the gate of the MOS transistor P13 in accordance with the voltage drop caused by the charging current flowing through the resistor R21.

<Second Modification>
FIG. 4 shows a circuit configuration diagram of a second modification of the embodiment of the regulator circuit of the present invention. In FIG. 4, the power supply terminal 12 is connected to one end of an external DC power supply 11 and one end of a capacitor C11, and the other end of the DC power supply 11 and the capacitor C11 is grounded. A control signal for switching on / off of the regulator circuit is supplied to the control terminal 13 from the outside, and this control signal is supplied to the constant current circuit 15. The ground terminal 14 is grounded.

  One end of the constant current circuit 15 is connected to the power supply terminal 12, and the other end of the constant current circuit 15 is the gate of the n-channel MOS transistor N11 constituting the error amplifier, one end of the reference voltage circuit 16, and the comparator constituting the current compensation circuit 20C. 21 is connected to the inverting input terminal. The other end of the reference voltage circuit 16 is connected to the ground terminal 14. The sources of the n-channel MOS transistors N11 and N12 are connected in common and connected to one end of the constant current circuit 17, and the other end of the constant current circuit 17 is connected to the ground terminal 14.

  The drain of the MOS transistor N11 is connected to the drain of the p-channel MOS transistor P11 and the gate of the MOS transistor P13 as an output transistor. The drain of the MOS transistor N12 is connected to the drain of the p-channel MOS transistor P12 and the gates of the MOS transistors P11 and P12. The sources of the MOS transistors P11, P12, P13 are connected to the power supply terminal 12. The p-channel MOS transistors P11 and P12 constitute a current mirror circuit.

  The drain of the MOS transistor P13 is connected to the output terminal 18. The output terminal 18 is connected to one end of an external capacitor C12, and the other end of the capacitor C12 is grounded. The output terminal 18 and the ground terminal 14 are connected by resistors R11 and R12 connected in series. The connection point of the resistors R11 and R12 is connected to the gate of the MOS transistor N12.

  The gate of the MOS transistor N11 is connected to one end of the reference voltage circuit 16 and supplied with the reference voltage Vref, and the gate of the MOS transistor N12 is connected to the connection point of the resistors R11 and R12. The MOS transistors N11 and N12 constitute a differential circuit, which amplifies the difference voltage between the feedback voltage Vfb at the connection point of the resistors R11 and R12 and the reference voltage Vref, and thus the drain voltage of the MOS transistor N11, that is, the difference voltage. Is supplied to the output transistor, that is, the gate of the MOS transistor P13 to control the drain current of the MOS transistor P13, thereby maintaining the output terminal voltage at a predetermined voltage.

  The current compensation circuit 20C includes a comparator 21, a capacitor C21, p-channel MOS transistors P21 and P22 constituting a current mirror circuit, and a p-channel MOS transistor P23. The comparator 21 is a comparator with an offset. The comparator 21 has a non-inverting input terminal connected to the gate of the MOS transistor N11 and supplied with a reference voltage Vref, and an inverting input terminal connected to a connection point between the resistors R11 and R12 and supplied with a feedback voltage Vfb. The comparator 21 outputs a high level signal when the feedback voltage Vfb is less than a voltage lower than the reference voltage Vref by the offset voltage Voff (Vfb <Vref−Voff), and outputs a low level signal when the feedback voltage Vfb is above (Vfb> Vref−Voff). To do.

  The output terminal of the comparator 21 is connected to the gate of the p-channel MOS transistor P23. The source of the MOS transistor P23 is connected to the power supply terminal 12, and the drain of the MOS transistor P23 is connected to the other end of the capacitor C21 having one end connected to the ground terminal 14. The other end of capacitor C21 is connected to the gate and drain of p-channel MOS transistor P21 and to the gate of p-channel MOS transistor P22. The sources of the MOS transistors P21 and P22 are connected to the power supply terminal 12, and the drain of the MOS transistor P22 is connected to the gate of the MOS transistor P13.

  In this second modification, when the output of the comparator 21 is at a high level, the MOS transistor P23 is turned off, the charging current of the capacitor C21 flows through the MOS transistor P21, and the current corresponding to this charging current is the drain of the MOS transistor P22. To point A which is the gate of the MOS transistor P13. When the output of the comparator 21 becomes low level, the MOS transistor P23 is turned on, and the capacitor C21 is bypassed so that the charging current does not flow through the MOS transistor P21.

DESCRIPTION OF SYMBOLS 11 DC power supply 12 Power supply terminal 13 Control terminal 14 Ground terminal 15 Constant current circuit 16 Reference voltage circuit 17 Constant current circuit 18 Output terminal 20A, 20B, 20C Current compensation circuit C11-C21 Capacitor P11-P23 p channel MOS transistor R11-R21 Resistance N11 to N12 n-channel MOS transistors

Claims (4)

A reference voltage unit that is supplied with power and generates a reference voltage;
A differential amplifier for amplifying the voltage of the difference between the voltage according to the output voltage and the reference voltage;
In a regulator circuit having an output transistor that varies the output voltage according to the voltage of the difference supplied with the power source and amplified by the differential amplification unit,
A comparator supplied with the reference voltage to one input terminal and a voltage corresponding to the output voltage to the other input terminal;
A capacitor having one terminal connected to the output terminal of the comparator and the other terminal connected to the power source via a current supply circuit;
Have
The comparator, when the voltage according to the output voltage is lower than the reference voltage, when the output is low level, the charging current flows through the capacitor,
The regulator circuit , wherein the current supply circuit supplies a current corresponding to the charging current flowing through the capacitor to a control terminal of the output transistor . The regulator circuit according to claim 1,
The current supply circuit includes a first transistor through which a charging current of the capacitor flows;
A regulator circuit, characterized in that it is a current mirror circuit composed of a second transistor through which a current corresponding to a charging current of the capacitor flows. The regulator circuit according to claim 1,
The current supply circuit includes a first resistor through which a charging current of the capacitor flows;
A regulator circuit comprising a second transistor through which a current corresponding to a voltage drop of the first resistor flows. The regulator circuit according to claim 2, wherein
Said current supply circuit, a voltage corresponding to the output voltage flowing a charging current of the capacitor to the first transistor when lower than the reference voltage, a voltage corresponding to the output voltage is lower than the reference voltage A regulator circuit, further comprising a third transistor that bypasses the charging current of the capacitor so that it does not flow through the first transistor except when .

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