JP6510165B2 - Operational amplifier - Google Patents

Description

The present invention relates to an operational amplifier , and more particularly to an operational amplifier including a differential amplification circuit controller suitable for stabilizing the operation of a differential amplification circuit.

  In an operational amplifier and a voltage regulator including a differential amplification circuit, the response speed (transient response) of the output signal is reduced, the output settling time (output settling time) to output load fluctuation is prolonged, and the output overshoot and undershoot As a countermeasure against the problem of occurrence, conventionally, the current of the entire circuit, in particular, the operating current of the differential amplifier circuit has been increased to accelerate the circuit operation.

  However, with the recent demand for lower power consumption in society, lower current consumption is also required for operational amplifiers and voltage regulators that are semiconductor integrated circuits. If the current consumption is reduced in response to such a requirement, the operating speed of the op amp itself becomes slower, the response speed of output signal (transient response) decreases, and the output settling time against output load fluctuation (output set) There is a problem that the ring time) is prolonged and the output overshoot and undershoot become large.

  As described above, the countermeasure to increase the current consumption contradicts to the recent reduction in power consumption, and it is difficult to reduce the current consumption based on these.

  Patent Document 1 describes a technique for improving the response characteristic by increasing the current consumption of the constant voltage circuit only when necessary. In the technology of Patent Document 1, in the constant voltage circuit using the error amplification circuit, when the output voltage rises and the divided voltage exceeds the threshold, the bias current of the operational amplifier is increased to increase the operating speed of the operational amplifier. The rise in output voltage can be quickly returned to the original rated output voltage.

  However, the technology of Patent Document 1 only copes with the overshoot of the output voltage, shortening the rise time of the constant voltage circuit, and suddenly increasing the load current or decreasing the input voltage. Can not cope with the undershoot of the output voltage that occurs when

  A technique for solving such a problem of Patent Document 1 is described in Patent Document 2 below. In the technique of Patent Document 2, in a constant voltage circuit using an error amplification circuit, a capacitor is provided between the output terminal and the ground, a resistor is provided between the capacitor and the ground, and a connection point between the capacitor and the resistor is provided. The first comparator with the plus terminal connected and the minus terminal connected to the ground side of the resistor, and the minus terminal connected to the connection point between the capacitor and the resistor and the plus terminal connected to the ground side of the resistor A comparator 2 is provided to increase or decrease the bias current of the error amplification circuit according to the outputs of the first and second comparators.

  For example, when the output voltage is stable and the power supply voltage rises or the load current decreases to cause the output voltage to rise and charge current flows in the capacitor, the output of the first comparator becomes high level, If the bias current of the error amplification circuit is increased and returned to the original rated output voltage in a short time, or if the power supply voltage drops or the load current increases and the output voltage drops and the capacitor discharge current flows, The output of the second comparator becomes high level, the bias current of the error amplification circuit can be increased, and the original rated output voltage can be restored in a short time, and overshoot and undershoot can be suppressed.

JP, 2004-164411, A Japanese Patent Application Publication No. 2007-310521

  However, the technique of Patent Document 2 is configured to detect the potential difference between both ends of the resistance associated with the charging current and the discharging current of the capacitor with the first and second comparators. The output of any of the second comparators becomes high level, and the state where the bias current of the error amplification circuit is increased frequently occurs, and the operation is not stable. As a result, power consumption can not be stably suppressed.

  The present invention has been made to solve the above problems, and the transient response of the output signal to the input signal, the output to the output load fluctuation without increasing the consumption current at the time of output stabilization in the voltage regulator and the operational amplifier. It is an object of the present invention to provide a differential amplifier circuit control device capable of stably improving settling time, overshoot and undershoot.

To achieve the above object, the operational amplifier of the present invention, the non-inverting input terminal is connected to one input terminal for inputting an external signal of the main differential amplifier, the other for inputting an external signal of the main differential amplifier circuit A first comparator including a first differential amplifier circuit having an inverting input terminal connected to the input terminal of the first differential amplifier circuit and outputting a voltage according to an input difference caused by a decrease in output voltage of the main differential amplifier circuit; is connected to the inverting input terminal said to one input terminal of the main differential amplifier, the main differential non-inverting input terminal the other input terminal of the amplifier circuit is connected, the output of the main Sadozo width circuit According to a second comparator including a second differential amplifier circuit that outputs a voltage corresponding to an input difference accompanying a rise in voltage, and a voltage output from each of the first comparator and the second comparator the main differential amplifier circuit according Increasing the current flowing through the current source transistor, and high-speed function unit to increase the operating speed of the main differential amplifier circuit, the resistance value by trimming a load of both of the main differential amplifier circuit is adjustable, the output and adjustment circuit of the offset voltage with respect to said first differential amplifier circuit resistance by trimming a both load adjustable in an adjustment circuit of the offset voltage for the undershoot detection, said second differential amplifier An offset voltage adjustment circuit for overshoot detection, which is both loads of the circuit and whose resistance value can be adjusted by trimming.

According to the present invention, the first comparator comprising a first differential amplifier circuit has a non-inverting input terminal is connected to one input terminal for inputting an external signal of the main differential amplifier, the main differential amplifier An inverting input terminal is connected to the other input terminal for inputting an external signal of the circuit, and a voltage corresponding to an input difference accompanying a drop in the output voltage of the main differential amplifier circuit is output, and a second differential amplifier circuit In the second comparator, the inverting input terminal is connected to the one input terminal of the differential amplifier circuit, and the non-inverting input terminal is connected to the other input terminal of the main differential amplifier circuit, The high speed functional unit outputs a voltage according to the voltage output from each of the first comparator and the second comparator according to the input difference according to the increase in the output voltage of the main differential amplifier circuit. current source transistor of the main differential amplifier circuit Increasing the current flowing in, so to increase the operating speed of the main differential amplifier circuit, without increasing the current consumption during the stable output at op amp, transient response of the output signal to the input signal, to the output load change It is possible to stably improve the output settling time, and overshoot and undershoot.
Further, the adjustment circuit of the offset voltage to the output is the load of both of the main differential amplifier circuits, the resistance value can be adjusted by trimming, and the adjustment circuit of the offset voltage to undershoot detection is the first difference a possible resistance adjusting a both load dynamic amplifier circuit by trimming adjustment circuit of the offset voltage for the overshoot detection resistance value by both a load trimming of the second differential amplifier circuit Can be adjusted so that each offset adjustment can be done independently.

FIG. 1 is a circuit diagram showing a configuration example (first embodiment) of a voltage regulator provided with a differential amplifier circuit control device according to the present invention. It is a time chart which shows the operation example of the differential amplifier circuit control apparatus in FIG. It is a circuit diagram showing an example of composition of the conventional voltage regulator. It is a circuit diagram which shows the example of a structure of the reference voltage circuit in FIG. FIG. 2 is a circuit diagram showing a configuration example of a bias generation circuit in FIG. It is a timing chart which shows the operation example of the voltage regulator in FIG. It is a circuit diagram showing an example of composition of a voltage regulator which reduced undershoot. It is a timing chart which shows the operation example of the voltage regulator which reduced the undershoot in FIG. FIG. 8 is a circuit diagram showing a configuration example in which a circuit for offset voltage adjustment is provided to the voltage regulator in which the undershoot in FIG. 7 is reduced. FIG. 7 is a circuit diagram showing a configuration example (second embodiment) in which an offset voltage adjustment circuit is provided in the voltage regulator in FIG. 1. FIG. 11 is a circuit diagram showing a configuration example of an offset adjustment circuit for overshoot and undershoot detection in FIG. 10. It is a circuit diagram which shows the example of a structure of the offset adjustment circuit of the regulator output in FIG. FIG. 6 is a circuit diagram showing a configuration example of a conventional class A amplification Pch + Nch input operational amplifier. It is a circuit diagram showing an example of composition of the conventional class A amplification Pch input operational amplifier. It is a circuit diagram showing an example of composition (3rd embodiment) of class A amplification Pch + Nch input operational amplifier provided with a differential amplifier circuit control device concerning the present invention. FIG. 7 is a circuit diagram showing a configuration example (fourth embodiment) of a class A amplification Pch input operational amplifier including a differential amplifier circuit control device according to the present invention. FIG. 17 is a circuit diagram showing a configuration example of an offset adjustment circuit in FIG. FIG. 16 is a circuit diagram showing a configuration example in which a phase compensation circuit is provided to the class A amplification Pch + Nch input operational amplifier in FIG. 15. It is a circuit diagram showing an example of connection composition of a voltage follower circuit for current consumption measurement. It is a circuit diagram showing an example of connection composition of a voltage follower circuit for pulse response and Sin wave response measurement. It is a circuit diagram showing an example of connection composition of a voltage follower circuit for load transient response measurement. FIG. 16 is a diagram showing an example of current consumption characteristics of the class A amplification Pch + Nch input operational amplifier in FIG. 15; FIG. 16 is a diagram showing an example of pulse response characteristics of the class A amplification Pch + Nch input operational amplifier in FIG. 15; FIG. 16 is a diagram showing an example of load transient response characteristics of the class A amplification Pch + Nch input operational amplifier in FIG. 15; FIG. 17 is a diagram showing an example of current consumption characteristics of each of a class A amplification Pch input operational amplifier and a conventional class A amplification Pch input operational amplifier in FIG. 16; FIG. 17 is a diagram showing an example of pulse response characteristics of each of a class A amplification Pch input operational amplifier and a conventional class A amplification Pch input operational amplifier in FIG. 16; It is a circuit diagram showing an example of composition of the conventional class A amplification Nch input operational amplifier. FIG. 10 is a circuit diagram showing a configuration example (fifth embodiment) of a class A amplification Nch input operational amplifier including a differential amplifier circuit control device according to the present invention. FIG. 29 is a diagram showing an example of current consumption characteristics of each of a class A amplified Nch input operational amplifier and a conventional class A amplified Nch input operational amplifier in FIG. 28. FIG. 29 is a diagram showing an example of pulse response characteristics of each of a class A amplification Nch input operational amplifier and a conventional class A amplification Nch input operational amplifier in FIG. 28. It is a circuit diagram showing a configuration example (sixth embodiment) of a class AB operational amplifier provided with a differential amplifier circuit control device according to the present invention. FIG. 32 is a diagram showing an example of current consumption characteristics of each of the class AB operational amplifier and the conventional class AB operational amplifier in FIG. 31. It is a figure which shows the Sin wave response characteristic example of each of a class AB operational amplifier in FIG. 31, and the conventional class AB operational amplifier. FIG. 32 is a diagram showing an example of pulse response characteristics of each of a class AB operational amplifier and a conventional class AB operational amplifier in FIG. 31.

  Hereinafter, embodiments according to the present invention will be described using the drawings. First, a voltage regulator used for comparison with a voltage regulator provided with a differential amplifier circuit control device according to the present invention will be described with reference to FIG.

  The voltage regulator 300 in FIG. 3 includes a differential amplifier circuit 10, a reference voltage circuit (also described as “VREF”) 11, an output circuit 12 including a driver transistor PH1, and a voltage dividing circuit 13.

  The differential amplifier circuit 10 includes a bias generation circuit (also described as "BIAS") 14, NMOS transistors NH1, NH2 and NH3 of differential stages, PMOS transistors PH2 and PH7, PMOS transistors PH3 and PH8 of output stages, and NMOS transistor NH5. Etc. The MOS transistor is a MOSFET.

  A configuration example of the reference voltage circuit 11 is shown in FIG. In the reference voltage circuit 11, the resistor R41 constitutes a constant current source for supplying a constant current. Further, since the NMOS transistor NH41 is diode-connected, when a constant current flows, a constant voltage is generated at both ends, and acts as a constant voltage source. A constant voltage generated by the reference voltage circuit 11 is input to the non-inverting input terminal of the differential amplifier circuit 10 as a positive input VR.

  FIG. 5 shows an example of the configuration of the bias generation circuit 14. The PMOS transistors PH51 and PH52 and the NMOS transistors NH51 and NH52 form a current mirror circuit. The current mirror circuit operates in the saturation region and has low sensitivity to changes in drain-source voltage, and thus acts as a constant voltage source and constant current source that is less dependent on the power supply voltage.

  Further, since the NMOS transistor NH52 of the bias generation circuit 14 and the NMOS transistor NH3 of the differential stage in the differential amplifier circuit 10 of FIG. 3 constitute a current mirror circuit, bias is applied to the NMOS transistor NH3 of the differential stage. A constant current equal to the current flowing to the NMOS transistor NH52 of the generation circuit 14 can flow.

  The differential amplifier circuit 10 of FIG. 3 constitutes a negative feedback amplifier circuit, and the output thereof passes through the driver transistor PH1 of the output circuit 12 and the voltage dividing circuit 13 and is again output to the inverting input terminal of the differential amplifier circuit 10. It is input as a negative input FB. In the negative feedback amplifier circuit, the non-inverted input terminal and the inverted input terminal become virtual ground, and the positive input VR of the non-inverted input terminal and the negative input FB of the inverted input terminal act to have the same potential.

  As described above, in the differential amplifier circuit 10, the voltage of the reference voltage (positive input VR) of the reference voltage circuit 11 acts so as to be the voltage of the negative input FB. A voltage is generated which is "(R1 + R2) / R1" that is the reciprocal of the voltage division ratio of the circuit 13.

  For example, when the voltage of the reference voltage (positive input VR) of the reference voltage circuit 11 is “0.933 V”, “0.933 V × (933 Ω + 267 Ω) / 933 Ω = 1.2 V” is obtained in the present voltage regulator 300, and 1.2 V is obtained. Voltage can be supplied.

  The driver transistor PH1 of the output circuit 12 is a transistor of a sufficiently large size so as to have a large driving capability, and the voltage regulator 300 stably supplies a voltage of 1.2 V even with a load current of 0 mA to 150 mA. It is a circuit that can

  However, as shown in the time chart of FIG. 6, in the present voltage regulator 300, when the load current changes rapidly during operation, large overshoot and undershoot occur in the regulator output.

  Since the load current fluctuates according to the operation rate of the circuit using the regulator output as the power supply voltage, a change in the load current is unavoidable. For example, a large current such as a CPU (Central Processing Unit) or DSP (Digital signal Processing) When the circuit on the side of the load that requires the signal turns on and off, a particularly rapid change occurs.

  Overshoot and undershoot of the regulator output cause a malfunction of the circuit that uses the regulator output as the power supply voltage, so it is necessary to perform processing / waiting such as invalidating the operation result until the regulator output becomes stable. There has been a problem of increased complexity and unnecessary waiting time.

  Further, overshoot and undershoot can be improved by increasing the current consumption of the voltage regulator, but this is contrary to recent power saving.

  For example, a power supply regulator with reduced undershoot is realized by using a differential amplifier circuit (multi-input differential amplifier circuit) with reduced idling current disclosed in Japanese Patent Laid-Open No. 2003-8369.

  FIG. 7 shows the configuration of voltage regulator 700 with such undershoot reduced. An inverter 20 having a PMOS transistor PH6 and an NMOS transistor NH4 is added to form a multi-input differential amplifier circuit in which one negative input is increased in the differential stage of the differential amplifier circuit.

  In addition, a current conversion circuit 21 (PMOS transistor PH10) to which the output of the added negative input (inverter 20) is input is added, the source of the PMOS transistor PH10 is connected to the VDD power supply, and the drain is a differential amplifier circuit It is connected to the gate of the stage current source transistor NH3.

  In such a configuration, for example, when the load current rapidly increases, the current flowing through driver transistor PH1 rapidly increases, but the gate-source voltage of driver transistor PH1 corresponds to the amount of the current. A voltage drop occurs at the regulator output VOUT until it reaches a voltage. In addition, the potential of the negative input FB of the differential amplifier circuit is similarly lowered because the voltage is divided by the voltage dividing circuit (R1, R2).

  As a result, an input difference | VR−FB | occurs in the differential amplifier circuit, and the amplified voltage increases the drive current of the added current conversion circuit 21 (PMOS transistor PH10), and the differential of the differential amplifier circuit Increase the supply current of the stage current source NH3.

  As a result, the differential amplifier circuit operates at a primary speed, and the undershoot is reduced by changing the gate-source voltage of the driver transistor PH1 faster to a voltage corresponding to the load current, thereby reducing the load current fluctuation. It has low current consumption at the time of no idling and is suitable for power saving in recent years.

  However, in the voltage regulator 700 in which the undershoot is reduced in this way, when the load current decreases rapidly, the current flowing to the driver transistor PH1 decreases rapidly. However, the voltage between the gate and source of the driver transistor PH1 However, a voltage rise occurs at the regulator output VOUT until the voltage corresponds to the amount of current. Accordingly, the potential of the negative input FB of the differential amplifier circuit is also increased by the amount divided by the voltage dividing circuit.

  In this manner, an input difference | VR−FB | occurs in the differential amplifier circuit, and the amplified voltage does not increase the drive current of the added current conversion circuit 21 (PMOS transistor PH10). There is a problem that the operating speed of the amplifier circuit can not be increased and overshoot can not be reduced.

  FIG. 8 is a time chart showing an operation example of the voltage regulator 700 in which the undershoot is reduced as described above, and although the undershoot does not occur, the overshoot occurs.

  Hereinafter, a first embodiment of a differential amplifier circuit controller according to the present invention for solving such a problem will be described.

  As a first embodiment, a voltage regulator provided with a differential amplifier circuit controller according to the present invention will be described with reference to FIG.

  FIG. 1 shows a configuration example of a voltage regulator provided with a differential amplifier circuit control device according to the present invention, and the voltage regulator 100 of the present embodiment relates to the voltage regulator 300 shown in FIG. A differential amplifier circuit controller 15 is added, and the differential amplifier circuit controller 15 includes a comparator 30 as a first comparator according to the present invention, a comparator 31 as a second comparator according to the present invention, and The high-speed functional circuit 32 as a high-speed functional unit according to the present invention for speeding up the operation of the differential amplifier circuit 10 provided in the voltage regulator 300 is provided.

  The comparator 30 includes NMOS transistors NH14, 15, 16 and PMOS transistors PH16, 17 in a differential stage, and the output VR of the reference voltage circuit 11 in the voltage regulator 300 of FIG. 3 is input to the noninverting input terminal as a positive input. Are connected so that the output FB of the voltage dividing circuit 13 is input to the inverting input terminal as a negative input.

  In addition, the comparator 31 includes NMOS transistors NH5, NH6 and NH7 in the differential stage, and PMOS transistors PH11 and PH12. In contrast to the comparator 30, the output FB of the voltage dividing circuit 13 is input as a positive input to the noninverting input terminal And the output VR of the reference voltage circuit 11 is connected as a negative input to the inverting input terminal.

  The speed-up function circuit 32 includes PMOS transistors PH18 and PH6 to which the outputs of the comparators 30 and 31 are input. The sources and drains of the PMOS transistors PH18 and PH6 are VDD power supply and differential amplifier circuit 10 respectively. It is connected to the gate of the current source NH3 of the differential stage.

  With such a configuration, in the voltage regulator 100 according to the present embodiment, the non-inverted input terminal of the comparator 30 is connected to one input terminal of the differential amplifier circuit 10, and the output of the differential amplifier circuit 10 is fed back. The inverting input terminal is connected to the other input terminal, and a voltage corresponding to the input difference due to the drop in the output voltage of the differential amplifier circuit 10 is output, and the comparator 31 is connected to one input terminal of the differential amplifier circuit 10 A non-inverting input terminal is connected to the other input terminal to which the inverting input terminal is connected and the output of the differential amplifier circuit 10 is fed back, and a voltage according to the input difference accompanying the increase of the output voltage of the differential amplifier circuit 10 Output

  Then, the speed-up function circuit 32 increases the gate current of the current source transistor NH3 of the differential amplifier circuit 10 according to the voltage output from the comparators 30 and 31, thereby increasing the operation speed of the differential amplifier circuit 10.

  More specifically, the comparator 30 is output from the output circuit 13 of the voltage regulator 100, receives the output voltage FB divided by the voltage dividing circuit 13 as a negative input, and is output from the reference voltage circuit 11 as a voltage on the input side. The output voltage VR is a positive input, and a voltage obtained by amplifying the input difference is output. The comparator 31 is output from the output circuit 13 of the voltage regulator 100, and the output voltage FB divided by the voltage dividing circuit 13 is a positive input. The output voltage VR output from the reference voltage circuit 11 as the voltage on the side is used as a negative input to output a voltage obtained by amplifying the input difference.

  In the present invention, the gate is connected to the output of the comparator 30, the source is connected to the positive power supply Vdd, and the drain is connected to the gate of the NMOS transistor NH3 which is the current source transistor of the differential amplifier circuit 10. A PMOS transistor PH18 as the first transistor, and a PMOS transistor PH6 as the second transistor whose gate is connected to the output of the comparator 31, whose source is connected to the positive power supply Vdd, and whose drain is connected to the gate of the NMOS transistor NH3. The drive current of the PMOS transistor PH18 is increased by the voltage output from the comparator 30 as the output voltage of the differential amplifier circuit 10 in the voltage regulator 100 decreases, and the output of the differential amplifier circuit 10 in the voltage regulator 100. Voltage rise The voltage output from with the comparator 31 to increase the drive current of the PMOS transistor PH6, to increase the operating speed of the differential amplifier circuit 10 by increasing the supply current of the NMOS transistor NH3.

  Hereinafter, the operation of the voltage regulator 100 shown in FIG. 1 will be specifically described.

  When the load current rapidly increases, the current flowing to driver transistor PH1 in output circuit 12 rapidly increases, but the gate-source voltage of driver transistor PH1 becomes a voltage corresponding to the increased amount of current. Until then, a voltage drop occurs at the regulator output VOUT. Further, the potential of the negative input FB of the differential amplifier circuit 10 is also lowered by the amount divided by the voltage dividing circuit 13.

  In this state, the input difference | VR−FB | is generated in the comparator 30, and the voltage amplified by the comparator 30 increases the drive current of the PMOS transistor PH18 of the speed-up function circuit 32, and the differential of the differential amplifier circuit 10 is generated. Since the gate potential of the NMOS transistor NH3 which is a stage current source is raised, the supply current of the NMOS transistor NH3 as a current source is increased.

  As a result, the differential amplifier circuit 10 has an operation speed primarily increased, and the voltage between the gate and the source of the driver transistor PH1 can be made faster according to the load current to reduce undershoot. it can.

  Similarly, when the load current sharply decreases, the current flowing to driver transistor PH1 in output circuit 12 rapidly decreases, but the voltage between the gate and the source of driver transistor PH1 corresponds to the voltage corresponding to the amount of the current. Until then, a voltage rise occurs at the regulator output VOUT. Further, the potential of the negative input FB of the differential amplifier circuit 10 is also increased by the amount divided by the voltage dividing circuit 13.

  In this state, an input difference | VR−FB | is generated in the comparator 31, and the voltage amplified by the comparator 31 increases the drive current of the PMOS transistor PH6 of the speed-up function circuit 32, and the differential of the differential amplifier circuit 10 is generated. Since the gate potential of the NMOS transistor NH3 which is a stage current source is raised, the supply current of the NMOS transistor NH3 as a current source is increased.

  As a result, the differential amplifier circuit 10 has an operation speed primarily increased, and the voltage between the gate and the source of the driver transistor PH1 can be made faster according to the load current, thereby reducing the overshoot. it can.

  The NMOS transistor NH10 of the speed-up function circuit 32 is for suppressing excessive fluctuation of the bias voltage VB when the PMOS transistors PH18 and PH6 are switched. Depending on the configuration of the bias circuit 14 of the differential amplifier circuit 10, it may be better to add it.

  In the example of FIG. 1, the source is connected to the negative power supply Vss between the drain of the PMOS transistor PH18 and the PMOS transistor PH6 and the negative power supply Vss of the high speed functional circuit 32, and the drain and gate are drains of the PMOS transistors PH18 and PH6. And an NMOS transistor NH10 connected to the gate of the NMOS transistor NH3 as a current source.

  In the voltage regulator 100 according to the first embodiment, the NMOS transistor NH3 that is the current source of the differential stage of the differential amplifier circuit 10 is selected only when the divided voltage FB becomes higher or lower than the reference voltage VR. By raising the gate potential, the operation of the differential amplifier circuit 10 is temporarily accelerated.

  As a result, the problem of Patent Document 2 mentioned above (even if the potential difference is small, the output of either the first or second comparator becomes high level and the state where the bias current of the error amplification circuit is increased frequently Operation can not be stabilized), power consumption can be reduced, and overshoot and undershoot can be reduced stably.

  As described above, according to the first embodiment, the effect of stably reducing the overshoot and the undershoot of the regulator output when the load current changes rapidly can be obtained. In addition, at the time of idling where there is no change in load current, current consumption is low, which is suitable for power saving in recent years.

  The time chart of FIG. 2 shows the operation of the voltage regulator 100 of the first embodiment. In the voltage regulator 100 provided with the operation amplification circuit control device according to the present invention, it is shown that both the undershoot and the overshoot are suppressed.

  Next, as a second embodiment, a configuration provided with an adjustment function of offset voltage which is an important parameter in the differential amplifier circuit will be described.

  In a differential amplifier circuit, it is necessary to perform an offset voltage adjustment function, and the offset voltage adjustment generally uses a laser trimming technique using a fuse.

  FIG. 9 shows a circuit for performing offset adjustment of the regulator output and offset adjustment for detecting undershoot, in the power supply regulator with reduced undershoot shown in FIG.

  In the power supply regulator 900 shown in FIG. 9, when the fuse in the offset voltage adjustment circuit for adjusting the offset voltage for detecting the undershoot connected to the source of the PMOS transistor PH7 of the differential amplifier circuit is cut, the regulator output VOUT Affect

  Therefore, the offset adjustment of the regulator output needs to take into account the offset adjustment of the circuit that detects undershoot. In addition, in the LSI manufacturing process, the undershoot detection test process, the laser trimming process of the offset adjustment circuit that detects the undershoot, the test process of the regulator output, and the laser trimming process of the offset adjustment circuit of the regulator output are required. It is necessary to divide the laser trimming process into two.

  Alternatively, in order not to increase the number of processes, it may be necessary to compromise the accuracy of the offset adjustment, which may lead to a spec down of the regulator specification or a drop in yield.

  In order to cope with such a problem, in the power supply regulator of the second embodiment, the offset voltage with respect to the output is adjusted in the output circuit 13 of the differential amplifier circuit 10 as in the power supply regulator 1000 shown in FIG. Offset voltage adjustment circuit 111 for adjusting the offset voltage for adjusting the offset voltage for overshoot detection in comparator 30 with offset voltage adjustment circuits 112 and 113 for adjusting the offset voltage for undershoot detection. Offset voltage adjustment circuits 114 and 115 are provided.

  FIG. 11 shows an example of the configuration of an offset voltage adjustment circuit for adjusting the offset voltage for overshoot detection and undershoot detection, provided in the comparator 30 and the comparator 31. In FIG. The configuration of an offset voltage adjustment circuit for adjusting an offset voltage with respect to an output is provided.

  The offset voltage adjustment circuit for overshoot / undershoot detection shown in FIG. 11 is composed of a resistor and a fuse for laser trimming. Since the current flowing to the PMOS transistor of the differential stage flows to the resistor, the resistance value may be determined so that the potential changes in several tens of MV steps.

  The adjustment circuit of the offset voltage of the regulator output shown in FIG. 12 may be incorporated in the resistor portion of the voltage dividing circuit, and the resistance value may be determined so that the output FB of the voltage dividing circuit changes in several tens of MV steps.

  In the voltage regulator 1000 shown in FIG. 10, cutting any fuse to adjust each offset adjustment circuit for detecting overshoot and undershoot does not affect the regulator output, and each offset adjustment (regulator Output offset adjustment, offset adjustment for detecting undershoot, and offset adjustment for detecting overshoot can be performed independently.

  Therefore, each offset adjustment can be easily implemented, and the LSI manufacturing process is an offset adjustment circuit that detects overshoot / undershoot detection test process / regulator output test process / overshoot / undershoot. The laser trimming process and the laser trimming process and the laser trimming process of the offset adjustment circuit of the regulator output can be performed collectively as before.

  Generally, in the test process and the laser trimming process, the processing apparatus is different from the LSI tester and the laser trimmer, and it is necessary to set the LSI wafer to be manufactured in the apparatus. Test process, laser trimming process, test process, laser trimming When the process is repeated, the number of steps is greatly increased.

  In the voltage regulator 1000 of the second embodiment, the offset adjustment of the regulator output, and the offset adjustment for detecting an undershoot and the offset adjustment for detecting an overshoot can be performed independently, so the number of man-hours required for the manufacturing process. Can be suppressed and each offset adjustment can be easily implemented.

  Such a technology can be used for circuits, LSIs, etc. that are desired to reduce overshoot and undershoot of the regulator output voltage and to reduce current consumption when the load current changes.

  Next, as a third embodiment, an operational amplifier provided with a differential amplifier circuit control device according to the present invention will be described.

  First, a conventional operational amplifier will be described with reference to FIGS. 13 and 14.

  The operational amplifier shown in FIG. 13 is a class A amplification operational amplifier (hereinafter also referred to as a class A PN input amplifier) 1300 configured of a conventional Pch input differential amplifier circuit and an Nch input differential amplifier circuit. Hereinafter, the Pch input differential amplifier circuit and the Nch input differential amplifier circuit including the description of FIG. 13 are also referred to as a Pch input differential circuit and an Nch input differential circuit.

  The class A amplification PN input operational amplifier is designed to have a linear relationship (proportional relationship) between the input and the output, and an output with the least distortion compared to class B and class C can be obtained. However, since a constant bias current always flows, power consumption is large, and even when there is no input signal, a direct current flows through the amplification element, which consumes power. By the way, the class B differential amplification circuit is a method of giving a bias so that only one polarity (positive) of the AC input is amplified, and the class C differential amplification circuit has a bias more than a cutoff value. In this method, the output voltage can be obtained only when the voltage of the input signal is sufficiently high, to the side where the signal is turned off.

  The class A PN input amplifier 1300 includes a bias current source circuit 1301 and a main amplifier unit 1302. The main amplifier unit 1302 includes an Nch input differential amplifier circuit 1303, a Pch input differential amplifier circuit 1304, and an output circuit 1305. ing.

  The Pch input differential amplifier circuit 1304 controls the Nch output MOS transistor N5 of the output circuit 1305, and the Nch input differential amplifier circuit 1303 controls the Pch output MOS transistor P5 of the output circuit 1305.

  A wide variety of existing circuits can be applied to the bias current circuit 1301, and the circuit is simplified using an ideal current source.

  The operational amplifier shown in FIG. 14 is a class A amplification operational amplifier (hereinafter, also referred to as a class A P input amplifier) 1400 configured by a conventional Pch input differential amplifier circuit.

  The class A P input amplifier 1400 includes a bias current source circuit 1401 and a main amplifier unit 1402, and the main amplifier unit 1402 includes a Pch input differential amplifier circuit 1404 and an output circuit 1405.

  The Nch output MOS transistor N5 of the output circuit 1405 is controlled by the Pch input differential amplifier circuit 1404, and the Pch output MOS transistor P5 of the output circuit 1405 is supplied with a gate voltage from the bias current source circuit 1401 and a constant current source. Acts as.

  In the conventional operational amplifier, in order to improve the transient response of the output signal to the input signal and the output settling time, overshoot and undershoot to the output load fluctuation, the characteristic is improved by increasing the consumption current .

  However, with the recent trend toward lower power consumption in society, the trend toward lower current consumption has been increasing for operational amplifiers as well as voltage regulators.

  For example, reducing the current means that the operating speed of the operational amplifier itself is slowed, and as a result, the response speed of the output signal decreases and the output settling time (output settling time) against output load fluctuation is required. In addition, problems such as an increase in output overshoot and undershoot occur. As described above, this countermeasure is dealt with by increasing the current of the entire circuit, particularly the current of the differential amplifier circuit, to accelerate the circuit operation.

  As described above, increasing the drive current contradicts with the recent reduction in power consumption because current consumption increases, and it is difficult to reduce the current consumption based on these.

  An operational amplifier provided with a control apparatus for controlling a differential amplifier circuit according to the present invention corresponding to such a problem will be described with reference to FIGS.

  In FIG. 15, as a third embodiment, a circuit of an operational amplifier provided with a differential amplifier circuit controller according to the present invention is shown.

  The operational amplifier shown in FIG. 15 is a class A PN input amplifier 1500 configured of a Pch input differential amplifier circuit and an Nch input differential amplifier circuit.

  A class A PN input amplifier 1500 includes a bias current source circuit 1501 including a bias current source circuit and a bias current adjusting circuit 1501a as a high speed function unit according to the present invention, and a main amplifier unit as a differential amplifier circuit according to the present invention 1502, a high side current control circuit 1510 as a first comparator according to the present invention, and a low side current control circuit 1520 as a second comparator according to the present invention.

  The main amplifier unit 1502 is the same as the class A PN input amplifier 1300 in FIG. 13, and the detailed description thereof will be omitted.

  As described above, the class A PN input amplifier 1500 includes the class A PN input amplifier 1300 shown in FIG. 13 including the high side current control circuit 1510, the low side current control circuit 1520, and the bias current increase / decrease in the bias current source circuit 1501 The circuit 1501a is provided.

  The high side current control circuit 1510 includes an Nch input differential amplifier circuit consisting of Nch MOS transistors N16 and N17, and controls the high level (H) output level (hereinafter also referred to as high side) of the main amplifier unit 1502. The low side current control circuit 1520 includes a Pch input differential amplifier circuit composed of Pch MOS transistors P16 and P17, and controls the low level (L) output level (hereinafter also referred to as low side) of the main amplifier unit 1502. The bias current source circuit 1501 causes the bias current increase / decrease circuit 1501 a to increase the bias current output from the bias current source circuit 1501 according to the outputs from the high side current control circuit 1510 and the low side current control circuit 1520.

  The input terminal of the Nch input differential amplifier circuit of the high side current control circuit 1510 and the input terminal of the Pch input differential amplifier circuit of the low side current control circuit 1520 are each an inversion of the differential amplifier circuit of the main amplifier unit 1502. It is connected to the input terminal and the other is connected to the non-inverting input terminal.

  The output of the high side current control circuit 1510 is connected to the gate and source of the Pch MOS transistors P6 and P7 of the bias current adjusting circuit 1501a. The output of the low side current control circuit 1520 is connected to the gate and drain of the Nch MOS transistor N7 of the bias current source circuit 1501 and the Nch MOS transistor N8 of the bias current increase / decrease circuit 1501a.

  Further, in the class A PN input amplifier 1500, offset voltage adjusting circuits 1502a and 1502b whose configuration examples are shown in FIG. 17 for each of the main amplifier unit 1502, the high side current control circuit 1510, and the low side current control circuit 1520. 1510a and 1520a are provided.

  In the class A PN input amplifier 1500, the main amplifier unit 1502, the high side current control circuit 1510, and the low side current control circuit 1520 have characteristics and specifications in order to prevent output oscillation caused by circuit characteristics. It is also possible to connect a phase compensation circuit according to the requirement. The class A PN input amplifier 1800 shown in FIG. 18 is the class A PN input amplifier 1500 shown in FIG. 15 provided with such phase compensation circuits 1802 a, 1802 b, 1810 a, 1820 a.

  The operation of the class A PN input amplifier 1500 of FIG. 15 will be described below.

  In general, in the operational amplifier (differential amplifier circuit), there is no potential difference between the inverting input terminal (hereinafter also referred to as "IN-") and the non-inverting input terminal (hereinafter also referred to as "IN +") The phenomenon of so-called "virtual short" is observed, which operates or operates so that both terminals have the same voltage with reference to the ground potential.

  In order to clearly explain the operation of the class A PN input amplifier 1500 of FIG. 15, a voltage follower circuit shown in FIGS. 19 to 21 is used as a measurement circuit.

  The voltage follower circuit is a type of inverting amplification circuit in which IN− and OUT are connected. Since “amplification factor = 1”, “VOUT = ViN” holds true for “IN + input (ViN)”. Clearly understand the phenomenon of "virtual short".

  Here, in the output response, when the output rise on the high side is delayed with respect to the input signal, the “virtual short” of the differential amplifier circuit of the high side current control circuit 1510 is not established. The bias current adjusting circuit 1501a operates to increase the circuit current until the output is "virtual short".

  The low side current control circuit 1520 also applies a bias current because the "virtual short" of the differential amplification circuit of the low side current control circuit 1520 is not established this time when the low side output falling is delayed with respect to the input signal. The circuit 1501a operates to increase the circuit current until the output is "virtual short".

  By such an operation, when the output reaches the “virtual short”, the class A PN input amplifier 1500 is stabilized, and as a result, the output can be operated with less current when the output is stabilized.

  Next, a comparison with the prior art will be described using a characteristic example of the class A PN input amplifier 1500.

  FIG. 22 is a graph showing a comparison of current consumption characteristics of the conventional class A PN input amplifier 1300 shown in FIG. 13 and the class A PN input amplifier 1500 according to the present invention shown in FIG.

  FIG. 22 shows an example of comparing the current value of “ViN = 1⁄2 × VDD = 1.5 V”, which is a condition for measuring the consumption current of a general operational amplifier, with the power supply voltage VDD = 3V.

  “Characteristic example 1 (conventional)” in FIG. 22 is an example of current consumption characteristics when the circuit current in the conventional class A PN input amplifier 1300 is increased and the consumption current is 200 μA as voltage (horizontal axis) and current (vertical axis) It shows by).

  “Characteristic example 2 (conventional)” is an example of current consumption characteristics when the circuit current in the conventional class A PN input amplifier 1300 is reduced to 3.88 μA by voltage (horizontal axis) and current (vertical axis). It shows.

  Then, in the “characteristic example 3 (present invention)”, the circuit current in the class A PN input amplifier 1500 according to the present invention is 3.92 μA, and the consumption current equivalent to the “characteristic example 2 (conventional)” is obtained. Shows an example of voltage-current characteristics at the time of

  An example of a pulse response characteristic at a high load such as the output load “CL = 10000 PF” with such a characteristic is shown in FIG.

  In FIG. 23, in the “characteristic example 1 (conventional)”, the circuit operation is quick because the circuit current is large, there is almost no delay between the high side and the low side of the output, and the slew rate characteristics are also good.

  Further, in the “characteristic example 2 (conventional)”, since the circuit current is small, the circuit operation is slow and the delay between the high side and the low side of the output is large. As a result, the slew rate characteristic is degraded.

  On the other hand, in the “characteristic example 3 (the present invention)”, as described above, the circuit current is increased by the high side current control circuit 1510 and the low side current control circuit 1520 at the rise and fall of the output. It has been shown that it has high performance and has good slew rate characteristics that are comparable to those of “Characteristic example 1 (conventional)” with increased circuit current, and that it can operate with less current when the output is stable. ing.

  Next, FIG. 24 shows a comparative example of load transient response characteristics. Output stability (output settling time) when the output load current (40 MA ⇔ 50 MA) is fluctuated when the input is fixed at "ViN = 1.5 V" and the output is "VOUT = 1.5 V" A comparative example of overshoot and undershoot is shown.

  In FIG. 24, in the “characteristic example 1 (conventional)”, the output settling time is 0.76 μS, and the overshoot / undershoot is 340 MV.

  Further, in the “characteristic example 2 (conventional)”, the output settling time is 22 μs, the undershoot / overshoot is 587 MV, and the characteristic of the “characteristic example 2 (conventional)” is obviously deteriorated.

  On the other hand, in “characteristic example 3 (invention)”, the output settling time is 0.67 μS, the overshoot / undershoot is 204 MV, and in the same manner, “characteristic example 1 (conventional)” is also described. It has been shown that good characteristics without any deterioration are obtained, and that it is possible to operate with less current when the output is stable.

  Thus, according to the class A PN input amplifier 1500 according to the present invention shown in FIG. 15, the transient response of the output signal to the input signal and the output set to the output load fluctuation can be obtained without increasing the consumption current at the time of output stabilization. Ring time and output overshoot and undershoot can be improved.

  Although the consumption current is at least about 4 μA in the description of the operation of this embodiment, it is possible to set an nA order, and it is also possible to configure an operational amplifier of ultra-low consumption current.

  The differential amplifier circuit of the main amplifier unit 1502, the differential amplifier circuit of the high side current control circuit 1510, and the differential amplifier circuit of the low side current control circuit 1520 are also independent with respect to the offset voltage of the differential amplifier circuit which causes a problem in the operational amplifier. The offset voltage adjustment circuits 1502a, 1502b, 1510a, and 1520a, which are respectively provided, can be adjusted by trimming the fuses.

  For example, the differential amplifier circuit of the main amplifier unit 1502 adjusts the input offset voltage by trimming the offset voltage adjusting circuits 1502a and 1502b, and the differential amplifier circuit of the high side current control circuit 1510 controls the amount of high side control current and The input offset voltage is adjusted by trimming the offset voltage adjusting circuit 1510a, and the differential amplifier circuit of the low side current control circuit 1520 adjusts the amount of low side control current and the input offset voltage by trimming the offset voltage adjusting circuit 1520a.

  Next, the class A P input amplifier 1600 according to the present invention in FIG. 16 will be described.

  FIG. 16 shows, as a fourth embodiment, a circuit of an operational amplifier provided with a differential amplifier circuit controller according to the present invention.

  The operational amplifier shown in FIG. 16 is a class A P input amplifier 1600 configured of a Pch input differential amplifier circuit.

  The class A P input amplifier 1600 includes a bias current source circuit 1601 including a bias current increase / decrease circuit 1601a as a high speed function unit according to the present invention, a main amplifier unit 1602 as a differential amplifier circuit according to the present invention, The high side current control circuit 1610 as the first comparator and the low side current control circuit 1620 as the second comparator according to the present invention are provided.

  In the class A P input amplifier 1600, the Nch output MOS transistor N5 of the output circuit in the main amplifier unit 1602 is controlled by the bias current source circuit 1601 and the Pch input differential amplifier circuit in the main amplifier unit 1602, and the main amplifier unit The Pch output MOS transistor P5 in 1602 functions as a constant current source whose gate voltage is supplied from the bias current source circuit 1601.

  In the class A P input amplifier 1600, the high side current control circuit 1610 and the low side current control circuit 1620 are formed of Pch input differential amplifier circuits formed of Pch MOS transistors P13, P14, P20 and P21. This is because the differential amplifier circuit of the main amplifier unit 1602 is formed of a Pch input differential amplifier circuit, so it is necessary to match the input range to the in-phase input range, and therefore the high side current control circuit 1610 and the low side The current control circuit 1620 is configured of a Pch input differential amplifier circuit.

  As described above, the present class A P input amplifier 1600 can increase or decrease the bias current in the high side current control circuit 1610, the low side current control circuit 1620, and the bias current source circuit 1601 in addition to the class A P input amplifier 1400 shown in FIG. The circuit 1601a is provided.

  The high side current control circuit 1610 includes a Pch input differential amplifier circuit, and controls the high level (H) output (hereinafter also referred to as high side) of the main amplifier unit 1602. The low side current control circuit 1620 includes a Pch input differential amplifier circuit, and controls the low level (L) output (hereinafter also referred to as low side) of the main amplifier unit 1602.

  In addition, the bias current source circuit 1601 increases the bias current output from the bias current source circuit 1601 according to the outputs from the high side current control circuit 1610 and the low side current control circuit 1620 by the bias current increase / decrease circuit 1601 a.

  The input terminal of the Pch input differential amplifier circuit of the high side current control circuit 1610 and the input terminal of the Pch input differential amplifier circuit of the low side current control circuit 1620 are each an inversion of the differential amplifier circuit of the main amplifier unit 1602 It is connected to the input terminal and the other is connected to the non-inverting input terminal.

  The output of the high side current control circuit 1610 is connected to the gate and source of the Pch MOS transistor P7 in the bias current adjusting circuit 1601a, and to the gate and drain of the Nch MOS transistor N7. The output of the low side current control circuit 1620 is similarly connected to the bias current increase / decrease circuit 1601a.

  Furthermore, in the present class A P input amplifier 1600, offset voltage adjusting circuits 1602a and 1610a whose configuration examples are shown in FIG. 17 for the main amplifier unit 1602, the high side current control circuit 1610, and the low side current control circuit 1620, respectively. , 1620a are provided.

  In the class A P input amplifier 1600 as well as the class A PN input amplifier 1500 in FIG. 15, the main amplifier unit 1602, the high side current control circuit 1610, and the high side current control circuit 1610 are provided to prevent output oscillation caused by circuit characteristics. A phase compensation circuit may be connected to each of the low side current control circuits 1620 according to its characteristics and specifications.

  The operation of the class A P input amplifier 1600 is the same as that of the class A PN input amplifier 1500 in FIG. 15, and the description thereof is not given here. An example of the operation characteristic of will be described.

  FIG. 25 is a graph showing a comparison of current consumption characteristics of the conventional class A P input amplifier 1400 shown in FIG. 14 and the class A P input amplifier 1600 according to the present invention shown in FIG.

  FIG. 25 shows an example of comparing the current value of “ViN = 1⁄2 × VDD = 1.5 V”, which is a condition for measuring the consumption current of a general operational amplifier, with the power supply voltage VDD = 3V.

  The “characteristic example 1 (conventional)” and the “characteristic example 2 (present invention)” in FIG. 25 show the conventional class A P input amplifier 1400 shown in FIG. 14 and FIG. An example of current consumption characteristics of the class A P input amplifier 1600 according to the present invention is shown by voltage (horizontal axis) and current (vertical axis).

  An example of a pulse response characteristic at an output load “CL = 100 PF” in such a consumption current characteristic is shown in FIG.

  FIG. 26 shows that in the “characteristic example 1 (conventional)”, the circuit operation is slow because the circuit current is small, and the delay on the high side / low side of the output is large, resulting in deterioration of the slew rate characteristic. It is done.

  On the other hand, in the “characteristic example 2 (invention)”, the circuit operation is fast because the circuit current is increased by the high side current control circuit 1610 and the low side current control circuit 1620 at the rise and fall of the output. It is shown that the slew rate characteristics are good and that it can operate with less current when the output is stable.

  In addition, it is clear that it improves also about an example of a load excess adaptation characteristic with improvement of such a characteristic.

  Thus, in the class A P input amplifier 1600 shown in FIG. 16 as well as in the class A PN input amplifier 1500 shown in FIG. It is possible to improve response and output settling time and output overshoot and undershoot against output load fluctuation.

  Although the current consumption is at least about 5 μA in the description of the operation of this example, it is possible to set an nA order, and it is also possible to configure an operational amplifier of ultra-low current consumption.

  Further, with regard to the offset voltage of the differential amplifier circuit which causes a problem in the operational amplifier, the differential amplifier circuit of the main amplifier, the differential amplifier circuits of the high side current control circuit and the low side current control circuit are independent offset voltage adjusting circuits. 1602a, 1610a, 1620a can be adjusted individually by trimming or the like.

  Next, a fifth embodiment according to the present invention will be described using FIG. 27 and FIG.

  27 and 28 show the configuration of a class A N input amplifier, FIG. 27 shows the configuration of a conventional class A N input amplifier 2700, and FIG. 28 is provided with a differential amplifier circuit control device according to the present invention. The configuration of the class A N input amplifier 2800 is shown.

  With respect to the configuration shown in each of FIGS. 27 and 28, based on the class A PN input amplifier shown in FIGS. 13 and 15, the Pch input differential amplifier circuit in the class A P input amplifier shown in FIGS. The amplifier is replaced with an amplifier of an Nch input differential amplifier circuit.

  That is, the operational amplifier 2700 shown in FIG. 27 is a class A N input amplifier configured by an Nch input differential amplifier circuit.

  This conventional A-class N-input amplifier 2700 includes a bias current source circuit 2701 and a main amplifier unit 2702, and the main amplifier unit 2702 includes an Nch input differential amplifier circuit 2704 and an output circuit 2705 consisting of Nch MOS transistors N1 and N2. Have.

  The Pch output MOS transistor P5 of the output circuit 2705 is controlled by the Pch input differential amplifier circuit 2704, and the gate voltage is supplied from the bias current source circuit 2701 to the Nch output MOS transistor N5 of the output circuit 2705. Acts as.

  Also in the conventional A-class N-input amplifier 2700, along with the recent trend toward lower power consumption in society, the trend toward lower current consumption is also increasing for operational amplifiers as in voltage regulators.

  However, reducing the current means that the operating speed of the operational amplifier itself is reduced, and as a result, the response speed of the output signal decreases and the output settling time (output settling time) against output load fluctuation is required. In addition, problems such as an increase in output overshoot and undershoot occur. As a countermeasure against this, conventionally, the current of the entire circuit, in particular, the current of the differential amplifier circuit is increased to accelerate the circuit operation.

  However, as described above, increasing the drive current contradicts with the recent reduction in power consumption because current consumption increases, and it is difficult to reduce the current consumption based on these.

  A class A N input amplifier 2800 shown in FIG. 28 will be described as an operational amplifier provided with a differential amplifier circuit control device according to the present invention corresponding to such a problem.

  A class A N input amplifier 2800 in FIG. 28 shows, as a fourth embodiment, a circuit of an operational amplifier provided with a differential amplifier circuit controller according to the present invention.

  The present class A N input amplifier 2800 includes a bias current source circuit 2801 including a bias current increase / decrease circuit 2801a as a high speed function unit according to the present invention, a main amplifier unit 2802 as a differential amplifier circuit according to the present invention, Such a high side current control circuit 2810 as a first comparator and a low side current control circuit 2820 as a second comparator according to the present invention are provided.

  In this A-class N-input amplifier 2800, the Pch output MOS transistor P5 of the output circuit in the main amplifier unit 2802 is formed by the bias current source circuit 2801 and the Nch input differential amplifier circuit consisting of Nch MOS transistors N1 and N2 in the main amplifier unit 2802. The Nch output MOS transistor N5 in the main amplifier unit 2802 functions as a constant current source whose gate voltage is supplied from the bias current source circuit 2801.

  In the present class A N input amplifier 2800, the high side current control circuit 2810 and the low side current control circuit 2820 are formed by Nch input differential amplifier circuits consisting of Nch MOS transistors N13, N14, N20 and N21. This is because the differential amplifier circuit of the main amplifier unit 2802 is configured by an Nch input differential amplifier circuit, so it is necessary to match the input range to the in-phase input range, and therefore the high side current control circuit 2810 and the low side The current control circuit 2820 is composed of an Nch input differential amplifier circuit.

  As described above, the present class A N input amplifier 2800 can increase or decrease the bias current in the high side current control circuit 2810, the low side current control circuit 2820, and the bias current increase / decrease circuit 2801 to the class A N input amplifier 2700 shown in FIG. A circuit 2801a is provided.

  The high side current control circuit 2810 includes an Nch input differential amplification circuit, and controls the high level (H) output (hereinafter also referred to as the high side) of the main amplifier unit 2802. The low side current control circuit 2820 includes an Nch input differential amplification circuit, and controls the low level (L) output (hereinafter, also referred to as low side) of the main amplifier unit 2802.

  Further, the bias current source circuit 2801 increases the bias current output from the bias current source circuit 2801 according to the output from the high side current control circuit 2810 and the low side current control circuit 2820 by the bias current increase / decrease circuit 2801 a.

  The input terminal of the Nch input differential amplifier circuit of the high side current control circuit 2810 and the input terminal of the Nch input differential amplifier circuit of the low side current control circuit 2820 are each an inversion of the differential amplifier circuit of the main amplifier unit 2802 It is connected to the input terminal and the other is connected to the non-inverting input terminal.

  The output of the high side current control circuit 2810 is connected to the source of the Pch MOS transistor P7 of the bias current increase / decrease circuit 2801a and the gate and drain of the Nch MOS transistor N7 via the Pch MOS transistor P15. Similarly, the output of the low side current control circuit 2820 is also connected to the bias current increase / decrease circuit 2801a via the Pch MOS transistor P22.

  Furthermore, in the present A-class N-input amplifier 2800, offset voltage adjusting circuits 2802a and 2810a whose configuration examples are shown in FIG. 17 for each of the main amplifier unit 2802, the high side current control circuit 2810 and the low side current control circuit 2820. , 2820a are provided.

  Also in the present A-class N-input amplifier 2800, as with the A-class PN input amplifier 1500 in FIG. 15 and the A-class P input amplifier 1600 in FIG. A phase compensation circuit may be connected to each of the high side current control circuit 2810 and the low side current control circuit 2820 according to the characteristics and specifications.

  The operation of this class A N input amplifier 2800 is the same as that of the class A PN input amplifier 1500 in FIG. 15 and the class A P input amplifier 1600 in FIG. 16, and will not be described here. An exemplary operation characteristic of the class A N input amplifier 2800 will be described with reference to FIG.

  FIG. 29 shows a graph comparing current consumption characteristics of the conventional class A N input amplifier 2700 shown in FIG. 27 and the class A N input amplifier 2800 according to the present invention shown in FIG.

  FIG. 29 shows an example where the power supply voltage is VDD = 3 V and the current value of “ViN = 1⁄2 × VDD = 1.5 V”, which is the consumption current measurement condition of a general operational amplifier, is compared.

  The “characteristic example 1 (conventional)” and the “characteristic example 2 (present invention)” in FIG. 29 show the conventional class A N input amplifier 2700 shown in FIG. 27 and FIG. An example of current consumption characteristics of the class A N input amplifier 2800 according to the present invention is shown by voltage (horizontal axis) and current (vertical axis).

  An example of a pulse response characteristic at an output load “CL = 100 PF” in such a consumption current characteristic is shown in FIG.

  FIG. 30 shows that in the “characteristic example 1 (conventional)”, since the circuit current is small, the circuit operation is slow, the high side / low side delay of the output is large, and the slew rate characteristic is consequently deteriorated. It is done.

  On the other hand, in the “characteristic example 2 (the present invention)”, the circuit current is increased by increasing the circuit current by the high side current control circuit 2810 and the low side current control circuit 2820 at the rise and fall of the output. It is shown that the slew rate characteristics are good and that it can operate with less current when the output is stable.

  In addition, it is clear that it improves also about an example of a load excess adaptation characteristic with improvement of such a characteristic.

  As described above, also in the class A N input amplifier 2800 shown in FIG. 28, as in the case of the class A PN input amplifier 1500 shown in FIG. 15 and the class A P input amplifier 1600 shown in FIG. It is possible to improve the transient response of the output signal to the input signal and the output settling time and output overshoot and undershoot to the output load fluctuation without causing the problem.

  Although the current consumption is at least about 5 μA in the description of the operation of this example, it is possible to set an nA order, and it is also possible to configure an operational amplifier of ultra-low current consumption.

  Further, with regard to the offset voltage of the differential amplifier circuit which causes a problem in the operational amplifier, the differential amplifier circuit of the main amplifier, the differential amplifier circuits of the high side current control circuit and the low side current control circuit are independent offset voltage adjusting circuits. 2802a, 2810a, 2820a are provided and can be adjusted by trimming or the like.

  Next, a sixth embodiment according to the present invention will be described with reference to FIGS.

  FIG. 31 shows a circuit of a class AB amplified Rail-TO-Rail (registered trademark) input / output operational amplifier (also referred to as a class AB operational amplifier) showing a sixth embodiment according to the present invention.

  A class AB operational amplifier 3100 shown in FIG. 31 includes a bias current source circuit 3101 including a bias current adjusting circuit 3101a as a high speed function unit according to the present invention, a main amplifier unit 3102 as a differential amplifier circuit according to the present invention, A high side current control circuit 3110 as a first comparator according to the present invention and a low side current control circuit 3120 as a second comparator according to the present invention.

  The class AB operational amplifier 3100 is configured as described below, and has a low current consumption, and is a circuit for sufficiently achieving high-speed output responsiveness.

  The differential amplifier circuit is composed of a Pch input differential amplifier circuit and an Nch input differential amplifier circuit in which active loads are diode-connected. It is a known fact that high speed response is a feature of a differential amplifier circuit in which an active load is diode-connected, but it is also a known fact that DC gain is low at only about 20 to 40 dB.

  In order to prevent the drop of the DC gain, the Pch input differential amplifier circuit connects the drain of the Nch MOS transistor whose gate is connected to the active load to the active load of the Nch input differential amplifier circuit.

  On the other hand, the Nch input differential amplifier circuit connects the drain of the Pch MOS transistor whose gate is connected to the active load to the active load of the Pch input differential amplifier circuit.

  And by making it a feedback structure with respect to each differential amplifier circuit, it is effective in raising DC gain to about 30-60 dB, and can prevent the fall of DC gain.

  As a prior art Rail-TO-Rail (registered trademark) differential amplifier circuit, an active load is connected to a current mirror-connected Pch input differential amplifier circuit, and an active Nch input differential amplifier circuit is connected to a diode-connected active load. The drain of the Pch MOS transistor whose gate is connected to the load is connected to the active load of the Pch input differential amplifier circuit.

  Such a circuit example is used in the high side current control circuit 3110 in FIG.

  When the active load connected in a current mirror is an Nch input differential amplifier circuit, the active load of the Pch input differential amplifier circuit is a diode connection, and the configuration of the circuit is the reverse of the above description. Such a circuit example is used in the low side current control circuit 3120 in FIG.

  Next, features of the in-phase input range (VSS to VDD) of the input of the class AB operational amplifier in each circuit configuration of the prior art will be described.

  Here, the differential amplifier circuit in which the active load is current-mirror connected is referred to as a main differential, and the differential amplifier circuit in which the active load is diode-connected is referred to as a sub differential.

  As a known fact, the Pch input differential amplifier circuit has an in-phase input range of "VSS-(VDD-VTP)", and the input on the VDD side can not be input for approximately VTH (VTP) of the Pch MOS transistor.

  Also, the Nch input differential amplifier circuit has a common mode input range of "(VSS-VTN) ~ VDD" as a known fact, and the input on the VSS side can not be input for almost VTH (VTN) of the Nch MOS transistor. .

  When the main differential is a Pch input differential amplifier circuit, the drain of the Pch MOS transistor whose gate is connected to the active load of the sub differential Nch input differential amplifier circuit is connected to the active load of the main differential. And the operation of the so-called "Rail-TO-Rail differential amplifier circuit" in which the in-phase input range is "VSS to VDD".

  When the main differential is an Nch input differential amplifier circuit, the drain of the Nch MOS transistor whose gate is connected to the active load of the sub differential Pch input differential amplifier circuit is connected to the main differential active load. The input on the VSS side is compensated, and the operation of the so-called "Rail-TO-Rail (registered trademark) differential amplifier circuit" in which the in-phase input range is "VSS to VDD" is obtained.

  The differential amplification circuit in the class AB operational amplifier 3100 shown in FIG. 31 has a configuration in which the Pch differential amplification circuit and the Nch differential amplification circuit feed back to each other's differential amplification circuit, and complementally each other's in-phase input range Since it is a structure which supplements, it is the circuit structure of what is called "RAil-TO-RAil (trademark) differential amplifier circuit."

  It is also possible to connect the gate of the active load to the bias circuit instead of diode connection.

  Subsequently, circuits of prebuffers 3102 c and 3102 d in the class AB operational amplifier 3100 will be described.

  A high side pre-buffer 3102c for controlling the Pch MOS transistor P5 which is a high side output has a differential input pair consisting of Pch MOS transistors P29 and P30 whose active loads are connected by current mirror connection and Nch MOS transistors N30 and N31. The Nch input differential amplifier circuit is configured by using the current source as a power supply (VSS).

  In the Nch input differential amplifier circuit of the prior art, since the current source is configured by the Nch MOS transistor, only a finite current set by the current source can flow as a current of the differential amplifier circuit.

  On the other hand, in the Nch differential amplifier circuit of the high side prebuffer 3102c, since the current source is the power supply (VSS), theoretically infinite current can flow.

  In fact, although the current is limited by the ON resistance of the differential input pair, it can take a larger current than prior art differential amplifier circuits. That is, the differential amplifier circuit of the high side prebuffer 3102c has a higher amplification factor than the differential amplifier circuit of the prior art.

  The low side pre-buffer 3102 d for controlling the low side output Nch MOS transistor N 5 has a differential input pair consisting of Nch MOS transistors N 32 and N 33 and Pch MOS transistors P 31 and P 32 configured by current mirror connection of active loads. The Pch input differential amplifier circuit is configured using the current source as a power supply (VDD).

  Similar to the description of the high side prebuffer 3102c described above, the differential amplifier circuit of the low side prebuffer 3102d has a higher amplification factor than the differential amplifier circuit of the prior art.

  Here, the differential amplification circuit will be described again. If DC gain is increased to about 30 to 60 dB with respect to the circuit of the prior art by forming a feedback configuration with the Pch input differential amplification circuit and the Nch input differential amplification circuit However, the main purpose of the differential amplifier circuit is high-speed response because the active load is diode-connected.

  Therefore, a DC gain of 80 dB or more can be obtained as the operational amplifier by compensating for the lack of the DC gain of the differential amplifier circuit with a high amplification prebuffer.

  Further, since the prebuffer of this example has a smaller number of elements and a simpler circuit configuration than the prior art prebuffer, the prebuffer itself is also suitable for high-speed response.

  In the class AB operational amplifier 3100 shown in FIG. 31, a low side current control circuit 3120 and a high side current control circuit 3110 configured by Rail-TO-Rail (registered trademark) differential amplifier circuits are added to such a main amplifier, By providing the bias current increase / decrease circuit 3101 a in the bias current source circuit 3101, a high-speed response class AB operational amplifier is configured.

  As for the offset voltage of the differential amplifier circuit which causes a problem in the operational amplifier, the differential amplifier circuit of the main amplifier 3102, the differential amplifier circuits of the high side current control circuit 3110 and the low side current control circuit 3120 are independent offset voltages. The adjustment circuits 3102 a, 3102 b, 3110 a, 3110 b, 3120 a, and 3120 b are provided, and can be adjusted by trimming or the like.

  Also, in order to take measures against output oscillation caused by circuit characteristics, the phase compensation circuit to which various existing circuits can be applied can be applied to the main amplifier 3101, the high side current control circuit 3110, and the low side current control circuit 3120. Connect according to the characteristics and specifications. In the class AB operational amplifier 3100 of FIG. 31, phase compensation circuits 3102 e, 3102 f, 3110 c, and 3120 c are connected to the main amplifier 3101, the high side current control circuit 3110, and the low side current control circuit 3120 respectively.

  The operation of the class AB operational amplifier 3100 is the same as the operation of each of the operational amplifiers of the third to fifth embodiments, and will not be described here. Hereinafter, the operation of the class AB operational amplifier 3100 will be described using FIGS. An example of the characteristics will be described.

  In FIG. 32, the class-AB operational amplifier 3100 (with current control circuit) consumption current characteristic in FIG. 31 and the high-side current control circuit 3110, low-side current control circuit 3120, and bias current increase / decrease circuit 3101a are eliminated from this class-AB op amp 3100. A comparison with the consumption current characteristic of only the main amplifier 3102 (without the current control circuit) is shown in the graph.

  FIG. 32 shows an example of comparing the current value of “ViN = 1⁄2 × VDD = 1.5 V”, which is a condition for measuring the consumption current of a general operational amplifier, with the power supply voltage VDD = 3V.

  In FIG. 32, “characteristic example 1 (without current control circuit)” shows consumption current characteristics of only the main amplifier 3102 (without current control circuit), and “characteristic example 2 (with current control circuit)” is class AB in FIG. The consumption current characteristics of the operational amplifier 3100 (with current control circuit) are shown by voltage (horizontal axis) and current (vertical axis), and each has a current equivalent to 10 μA.

  FIG. 33 shows an example of the SiN wave response characteristic at no load. The input waveform is “VSS to VDD”, and the output amplitude is “VSS to VDD” in both “characteristic example 1 (without current control circuit)” and “characteristic example 2 (with current control circuit)”. It shows the characteristics of TO-RAil (registered trademark).

  On the other hand, FIG. 34 shows an example of the pulse response characteristic at a high load of output load “CL = 10000 PF”. In FIG. 33, when the respective pulse response characteristics of “characteristic example 1 (without current control circuit)” and “characteristic example 2 (with current control circuit)” are compared, it is apparent from the graph that “characteristic example 2 ( The slew rate characteristics of “current control circuit”) are good.

  In addition, it is clear that it improves also about an example of a load excess adaptation characteristic with improvement of such a characteristic.

  As described above, also in the class AB operational amplifier 3100 in FIG. 31, as in the third to fifth embodiments, the transient response and output of the output signal with respect to the input signal without increasing the consumption current at the time of output stabilization. It is possible to improve output settling time and output overshoot and undershoot against load fluctuation.

  Although the current consumption is at least about 10 μA in the description of the operation of the present embodiment, it is possible to set an nA order, and it is also possible to configure an operational amplifier of ultra-low current consumption.

  As described above with reference to the respective drawings, in the differential amplifier circuit control device of the present embodiment, the noninverting input terminal is connected to one input terminal of the differential amplifier circuit (10), and the differential amplifier circuit A first comparator (30), which has an inverting input terminal connected to the other input terminal to which the output of the output is fed back, and outputs a voltage according to the input difference due to the drop of the output voltage of the differential amplifier circuit The inverting input terminal is connected to one input terminal of the dynamic amplification circuit, and the non-inverting input terminal is connected to the other input terminal to which the output of the differential amplification circuit is fed back, so that the output voltage of the differential amplification circuit rises. A differential amplifier circuit according to a voltage output from each of a second comparator (31) that outputs a voltage according to the accompanying input difference, and the first comparator (30) or the second comparator (31) Current through the current source transistor of the Is provided with a high speed functional unit to increase the operation speed of the differential amplifier circuit (32), the.

  The high-speed functional circuit (32) has a gate connected to the output of the comparator (30), a source connected to the positive power supply Vdd, and a drain connected to the gate of the current source transistor (NH3). Are connected to the output of the comparator (31), the source is connected to the positive power supply Vdd, and the drain is connected to the gate of the current source transistor (NH3).

  In the high-speed functional circuit (32), the source is connected to the negative power supply (Vss) between the drain of the transistor (PH18) and the transistor (PH6) and the negative power supply, and the drain and gate are transistors (PH18, PH6) And an NMOS transistor (NH10) connected to the gate of the current source transistor (NH3).

  And, when the differential amplifier circuit control device according to the present invention is applied to the voltage regulator (100), the differential amplifier circuit serves as a voltage divider (13) for dividing the output voltage and the input voltage The voltage regulator (100) is provided with a reference voltage unit (11) that outputs a reference voltage, and the comparator (30) receives the voltage divided by the voltage dividing unit as a negative input, and outputs the reference voltage output from the reference voltage unit. The comparator (31) uses the positive voltage as a positive input, and the negative voltage as a reference voltage output from the reference voltage unit.

  When the differential amplifier circuit control device according to the present invention is applied to the operational amplifier (1500, 1600, 2800), the operational amplifier is provided with at least one of an Nch operating circuit and a Pch operating circuit as a differential amplifier circuit. Applicable to

  In addition, the differential amplifier circuit (10) is provided with a circuit (offset adjustment circuit for adjusting regulator output) for adjusting the offset voltage with respect to the output, and the circuit for adjusting offset voltage for undershoot detection in the comparator (30) (undershoot detection And the comparator (31) can be provided with a circuit (offset adjustment circuit for overshoot detection) that adjusts the offset voltage for overshoot detection.

  By doing this, when a sudden change (increase or decrease) in load current (output voltage) occurs in the voltage regulator, the output speed can be increased quickly by increasing the operating speed of the differential amplifier circuit. The voltage between the gate and the source of the transistor can be made to correspond to the load current, and undershoot and overshoot can be reduced.

  In addition, by providing an offset voltage adjustment circuit in the comparators (30, 31), the “trimming step” in the manufacturing process for adjusting the offset adjustment circuit for detecting undershoot / overshoot in the differential amplifier circuit By making the implementation feasible, the manufacturing cost can be reduced.

  As described above, in the voltage regulator and the operational amplifier provided with the differential amplifier circuit controller according to the present invention, the transient response of the output signal to the input signal and the output load fluctuation can be obtained without increasing the consumption current when the output is stabilized. Output settling time and output overshoot and undershoot can be improved.

  The present invention is not limited to the embodiment described with reference to the drawings, and various modifications can be made without departing from the scope of the invention. For example, even if it is a class AB Rail-TO-Rail (registered trademark) operational amplifier having a circuit configuration different from that of the class AB operational amplifier 3100 shown in FIG. 31, the in-phase input range (VSS to VDD) equivalent to that of the main amplifier, that is, Rail If a high side current control circuit 3110 and a low side current control circuit 3120 having a differential amplifier circuit of TO-RAil (registered trademark) input can be configured, and if a current increase / decrease circuit can be configured in the bias current source circuit, FIG. It is possible to realize the present invention even with class AB op amps other than the class AB op amp 3100 shown.

  Further, as an embodiment according to the present invention, in the third embodiment, an operational amplifier of a class A amplification PCH · Nch input differential amplification circuit, in a fourth embodiment, an operational amplifier of a class A amplification Pch input differential amplification circuit, In the fifth embodiment, the operational amplifier of a class A amplification Nch input differential amplifier circuit, and in the sixth embodiment, an operational amplifier of a class AB amplification input / output Rail-TO-Rail (registered trademark) differential amplification circuit Although an example to which such a differential amplifier circuit control device is applied has been described, the high side current control circuit, the low side current control circuit, and the bias current increase / decrease circuit according to the present invention can be configured in this embodiment. Other types of differential amplification circuits, such as Rail-TO-Rail (registered trademark) differential amplification circuits, folded cascode differential amplification circuits, telescopic differential amplification circuits, etc. And it can also be applied to the bias current source circuit. Further, the output circuit can be applied to circuits of any kind and configuration such as class A circuits and class AB circuits.

10 differential amplifier circuit 11 reference voltage circuit 12, 1305, 1405, 2705 output circuit 13 voltage dividing circuit 14 bias generation circuit 15 differential amplifier circuit controller 20 inverter 21 current conversion circuit 30 comparator (first comparator)
31 comparator (second comparator)
32 High-speed functional circuits 100, 300, 700, 900, 1000 Voltage regulators 111 to 115, 1502b, 1502b, 1510a, 1520a, 1602a, 1610a, 1620a, 2802a, 2810a, 2820a, 3102a, 3102b, 3110a, 3110b, 3120a, 3120b Offset voltage adjustment circuit 1300, 1500, 1800 Class A amplified Pch + Nch input operational amplifier 1301, 1401, 1501, 1601, 2701, 2801, 3101 Bias current source circuit 1302, 1402, 1502, 1602, 1802, 2702, 2802, 3102 Main Amplifier sections 1303 and 2704 Nch differential amplifier circuits 1304 and 1404 Pch differential amplifier circuits 1400 class A amplification Pch input operational amplifier 150 a, 1601a, 2801a, 3101a Bias current increase / decrease circuit 1510, 1610, 1810, 2810, 3110 High side current control circuit 1520, 1620, 1820, 2820, 3120 Low side current control circuit 1600 Class A amplified Pch input operational amplifier 1801 Bias current source / Current increase / decrease circuit 1802a, 1802b, 1810a, 1820b, 3102e, 3102f, 3110c, 3120c Phase compensation circuit 2700, 2800 Class A amplified Nch input op amp 3100 Class AB op amp 3102c, 3102d Pre-buffer C Capacitors N0 to N33, NH0 to NH16 Nch MOS transistors P0 to P32, PH to PH18 Pch MOS transistor R1 to Resistor Vdd Positive power supply Vss Negative power supply

Claims (4)

A non-inverting input terminal is connected to one input terminal for inputting an external signal of the main differential amplifier circuit, and an inverting input terminal is connected to the other input terminal for inputting an external signal of the main differential amplifier circuit, a first comparator comprising a first differential amplifier circuit which outputs a voltage corresponding to the input difference associated with the drop in the output voltage of the main differential amplifier circuit,
The inverting input terminal said to one input terminal of the main differential amplifier circuit is connected, the non-inverting input terminal connected to the other input terminal of the main differential amplifier circuit, of the main Sadozo width circuit a second comparator comprising a second differential amplifier circuit which outputs a voltage corresponding to the input difference with increasing output voltage,
The operating speed of the main differential amplifier circuit is increased by increasing the current flowing through the current source transistor of the main differential amplifier circuit according to the voltage output from each of the first comparator and the second comparator. High-speed functional unit to make it faster,
An adjustment circuit of an offset voltage to an output, which is a load of both of the main differential amplifier circuits and whose resistance value can be adjusted by trimming;
Said first differential amplifier circuit resistance by trimming a both load adjustable in an adjustment circuit of the offset voltage for the undershoot detection,
Said second differential amplifier circuit both a load by trimming resistance value adjustable in the adjusting circuit of the offset voltage for the overshoot detection,
Operational amplifier with . The high speed functional unit is
A first transistor having a gate connected to the output terminal of the first comparator, a source connected to a positive power supply, and a drain connected to the gate of the current source transistor;
And a second transistor having a gate connected to the output terminal of the second comparator, a source connected to the positive power supply, and a drain connected to the gate of the current source transistor.
The operational amplifier according to claim 1. The high speed functional unit is
A source is connected to the negative power supply between each of the drain of the first transistor and the drain of the second transistor and a negative power supply, and a drain and a gate are connected to the drain of the first transistor and the second An NMOS transistor connected to the drain of each of the transistors and the gate of the current source transistor,
The operational amplifier according to claim 2. The main differential amplifier circuit is a differential amplification type circuit including at least one of an Nch differential circuit and a Pch differential circuit, and each of the first comparator and the second comparator is , operational amplifier according to any one of claims 1 to 3 including a circuit of a differential amplifier type of the same conductivity type as the main differential amplifier circuit.

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