JP5876807B2 - Low dropout voltage regulator circuit - Google Patents

Description

  The present invention relates to a low dropout voltage regulator circuit, and more particularly to a low dropout voltage regulator circuit that is stable against output load variations.

  In recent years, there has been an increasing demand for a system on a chip (SoC) in which many systems are housed in one chip. In order to further promote this, a constant voltage output circuit having high characteristics in items such as accuracy, power efficiency, responsiveness, silicon area, presence / absence of external parts, particularly a low dropout voltage regulator (Low DropOut) Regulator (LDO) circuit development is essential.

In a typical LDO circuit, it is necessary to connect a very large capacitor externally to the output of the LDO circuit to the ground in order to ensure the stability of the system when the output current increases or decreases. In such an LDO circuit, the accuracy and the stability of the system are in a trade-off relationship, and there is a problem that the stability of the system is deteriorated if high accuracy is taken.
Therefore, in order to solve such a problem, an LDO circuit that does not require an external capacitor has been developed (for example, see Patent Document 1).

FIG. 1 is a configuration diagram of a low dropout voltage regulator circuit described in Patent Document 1. In FIG. The low dropout voltage regulator (LDO) circuit includes an operational amplifier A1 having a positive input and a reference voltage Vref, an output of the operational amplifier A1 received at a gate terminal, a source terminal connected to a power supply, and a drain terminal The voltage Va is connected to the negative input of the operational amplifier A1, the voltage M at the drain terminal of the PMOS M1 is connected to the source terminal, the constant current source Ib0 is connected to the voltage Vcon at the drain terminal, the drain terminal and the gate terminal Is connected to the gate terminal of the PMOS Moff, and the constant voltage source Ib1 is connected to the drain terminal voltage Vd and the source terminal voltage Vout is the output of the LDO circuit. The source terminal is connected to the power supply, the drain terminal Is connected to the output Vout of the LDO circuit, the voltage Vc voltage of Vd voltage was DC biased by a DC bias circuit DB to the gate terminal is made of the connected PMOSMpass.
Here, assuming that the size ratio of the PMOS Moff is W0 / L0, the current of the current source Ib0 is Ib0, the size ratio of the PMOSMcon is W1 / L1, and the current of the current source Ib1 is Ib1, these sizes and current amounts have the following relationship: Decide so that the equation holds.

Next, the operation of the LDO circuit will be described.
The operational amplifier A1 is fed back so that the node Va becomes the reference voltage Vref because the reference voltage Vref is input to the positive input and the voltage Va of the drain terminal of the PMOS M1 is input to the negative input. Since PMOSMoff is diode-connected, the voltage Vcon at the gate terminal is expressed by the following equation if the channel length modulation effect is ignored.

Here, μ represents the mobility of the PMOS, Cox represents the unit gate capacitance, and Vth represents the threshold voltage of the PMOS.
The voltage Vout at the source terminal of the PMOS Mcon is expressed by the following equation using Vcon if the channel length modulation effect is ignored.

ここで、

here,

であるから、結局、Ｖｏｕｔは、

Therefore, after all, Vout is

となる。今、Ｖｏｕｔから電流が外部に向かって出力されたとすると、ＰＭＯＳＭｐａｓｓの電圧降下量が大きくなるため、Ｖｏｕｔ電圧はΔＶｏｕｔだけ低下する。すると、ノードＶｄの電圧は、ＰＭＯＳＭｃｏｎのトランスコンダクタンスをｇｍ、Ｉｂ１の出力インピーダンスをＲｂ１とすると、

It becomes. Now, assuming that a current is output from Vout to the outside, the voltage drop amount of the PMOS Mpass increases, and the Vout voltage decreases by ΔVout. Then, the voltage of the node Vd is expressed as follows. The transconductance of the PMOS Mcon is gm, and the output impedance of the Ib1 is Rb1.

倍されて大きく低下し、それが直流バイアス回路ＤＢによってＤＣ的にレベルシフトされてＰＭＯＳＭｐａｓｓのゲートに入力され、その結果、ＰＭＯＳＭｐａｓｓの出力抵抗が低下するため、Ｖｏｕｔを増加させるように働く。このような帰還が働くため、Ｖｏｕｔは出力電流に依らず、常に基準電圧Ｖｒｅｆを出力することが出来る。

It is doubled and greatly reduced, and it is DC-shifted by the DC bias circuit DB and inputted to the gate of the PMOS Mpass. As a result, the output resistance of the PMOS Mpass is lowered, so that Vout is increased. Since such feedback works, Vout can always output the reference voltage Vref regardless of the output current.

Further, for example, the low dropout voltage regulator described in Patent Document 2 is used in, for example, a cellular horn for a storage battery application, and a conventional low dropout regulator (LDO) connected to a load is an operational amplifier. A PMOS transistor, a resistor, and a reference voltage source.
Further, for example, the low dropout voltage regulator described in Patent Document 3 receives an input voltage at an input terminal, supplies a stabilized output voltage from an output terminal, and includes a stabilization circuit and an amplifier. The stabilization circuit has an input terminal for receiving an input voltage signal from the input terminal, an output terminal for supplying a stabilized output voltage level from the output terminal, and a control terminal for receiving a control signal from the output of the amplifier. Yes. The amplifier has its inverting input connected to the input path and receives a reference voltage signal. The reference voltage signal is supplied from a voltage reference source.

US Patent RE42,335 (E) JP-T-2004-504660 JP 2005-276190 A

However, in the conventional LDO circuit shown in FIG. 1, the voltage at the drain terminal of the PMOS Mcon is determined by the PMOS Mpass and the DC bias circuit DB, and is different from the voltage at the drain terminal of the PMOS Moff. Therefore, there is a problem that the voltage of Vout is deviated from the reference voltage Vref due to the channel length modulation effect.
The present invention has been made in view of such problems, and an object of the present invention is to provide a low dropout voltage regulator circuit that is stable against fluctuations in output load.

の関係を有することを特徴とする。 The present invention has been made to achieve such an object, and the invention according to claim 1 is a low dropout voltage regulator circuit that outputs an output voltage corresponding to a reference voltage from an output terminal. A first transistor (a first DC current source (Ib0) connected to the drain terminal (D1), the reference voltage (Vref) applied to the source terminal (S1), and a diode-connected gate terminal (G1)). Moff), the gate terminal (G2) is connected to the gate terminal (G1) of the first transistor (Moff), the drain terminal (D2) is connected to the second DC current source (Ib1), and the source terminal ( A second transistor (Mcon) having the output terminal connected to S2) and gate terminals (G1, G2) of the first and second transistors (Moff, Mcon); The voltage (Vcon) and the voltage (Vd) of the drain terminal (D2) of the second transistor (Mcon) are input, and the gate terminals (G1, G2) of the first and second transistors (Moff, Mcon). A second operational amplifier circuit (A2) that outputs a voltage (Vc) obtained by amplifying a voltage obtained by subtracting the voltage (Vd) of the drain terminal (D2) of the second transistor (Mcon) from the voltage (Vcon) of the second transistor (Mcon) , A third transistor having a gate terminal (G3) connected to the output of the second operational amplifier (A2) and a drain terminal (D3) connected to the output terminal and the source terminal of the second transistor ( and mpass), wherein the first transistor, the second transistor, and each of the channel width to channel length ratio L0 / W0, L1 / W1, respectively bets Current amount Ib0 of the DC current source connected to Njisuta, Ib1 is,

And wherein the Rukoto to have a relationship.

  According to the present invention, a low dropout voltage regulator circuit that is stable against fluctuations in output load can be realized, and a reference voltage can be output with higher accuracy than a conventional low dropout regulator circuit.

1 is a configuration diagram of a low dropout voltage regulator circuit described in Patent Document 1. FIG. 1 is a circuit configuration diagram for explaining a first embodiment of a low dropout voltage regulator circuit according to the present invention; FIG. FIG. 6 is a circuit configuration diagram for explaining Example 2 of the low dropout voltage regulator circuit according to the present invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 is a circuit configuration diagram for explaining the first embodiment of the low dropout voltage regulator circuit according to the present invention. The low dropout voltage regulator (LDO) circuit according to the first embodiment receives a first operational amplifier A1 in which a reference voltage Vref is input to a positive input, and an output of the first operational amplifier A1 at a gate terminal G. The low dropout voltage regulator circuit includes a PMOS M1 having a source terminal S connected to a power source and a voltage Va at the drain terminal D connected to the negative input of the first operational amplifier A1.

  A first transistor PMOSMoff having a first DC current source Ib0 connected to the drain terminal D1, a reference voltage Vref applied to the source terminal S1, a diode-connected gate terminal G1, and a first transistor PMOSMoff connected to the gate terminal G2. A second transistor PMOSMcon having a gate terminal G1 connected thereto, a drain terminal D2 connected to a second DC current source Ib1, and a source terminal S2 connected to an output terminal, and first and second transistors PMOSMoff, PMOSMcon. The voltage Vcon of the gate terminals G1 and G2 of the second transistor and the voltage Vd of the drain terminal D2 of the second transistor PMOSMcon are input, and the second voltage Vcon from the gate terminals G1 and G2 of the first and second transistors PMOSMoff and PMOSMcon The transitions The second operational amplifier circuit A2 that outputs a voltage Vc obtained by amplifying a voltage obtained by subtracting the voltage Vd of the drain terminal D2 of the PMOS Mcon, the gate terminal G3 is connected to the output of the second operational amplifier A2, and the drain terminal D3 is output. A third transistor PMOSMpass connected to the terminal is provided.

  Here, the size ratio of the first transistor PMOSMoff is W0 / L0, the current of the current source Ib0 is Ib0, the size ratio of the second transistor PMOSMcon is W1 / L1, and the current of the current source Ib1 is Ib1. And the amount of current are determined so that the following relational expression is satisfied.

Subsequently, the operation of the LDO circuit of the first embodiment will be described.
The operational amplifier A1 is fed back so that the node Va becomes Vref because the reference voltage Vref is input to the positive input and the drain voltage Va of the PMOS M1 is input to the negative input. Since PMOSMoff is diode-connected, the gate voltage Vcon is expressed by the following relational expression.

Here, μ is the PMOS mobility, Cox is the unit gate capacitance, Vth is the PMOS threshold voltage, and λ is the channel length modulation coefficient.
The source voltage Vout of the PMOS Mcon is expressed by the following relational expression using Vcon.

Here, the operational amplifier A2 controls the gate voltage of the PMOS Mpass, and the feedback works so that Vd becomes equal to Vcon, so Vd = Vcon.
Therefore, if Vd = Vcon is substituted into the above equation,

  Therefore, even if the channel length modulation effect is taken into account, Vo can accurately output the reference voltage Vref, and a more accurate LDO circuit can be realized.

  FIG. 3 is a circuit configuration diagram for explaining Example 2 of the low dropout voltage regulator circuit according to the present invention. In the first embodiment described above, the case where the transistors M1, Moff, Mcon, and Mpass are realized using PMOS has been described. However, NMOS may be used as shown in FIG. Even in such a case, it is clear that the same effect as the case of using PMOS is obtained.

A1, A2 operational amplifier DB DC bias circuit Moff first transistor Mcon second transistor Mpass third transistor

Claims (1)

A low dropout voltage regulator circuit that outputs an output voltage corresponding to a reference voltage from an output terminal,
A first transistor having a drain terminal connected to a first DC current source, a source terminal applied with the reference voltage, and a gate terminal diode-connected;
A second transistor having a gate terminal connected to the gate terminal of the first transistor, a drain terminal connected to a second DC current source, and a source terminal connected to the output terminal;
The voltages of the gate terminals of the first and second transistors and the voltage of the drain terminal of the second transistor are input, and the voltages of the gate terminals of the first and second transistors are used as input. A second operational amplifier circuit for outputting a voltage obtained by amplifying the voltage obtained by subtracting the voltage at the drain terminal;
It provided connected to the output of the gate terminal and the second operational amplifier, a third transistor having a drain terminal connected to the source terminal of the output terminal and the second transistor, and
Channel width and channel length ratios L0 / W0 and L1 / W1 of the first transistor and the second transistor, and current amounts Ib0 and Ib1 of a direct current source connected to each transistor are as follows:

A low dropout voltage regulator circuit characterized by

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