JPH06103784A - Detecting circuit for voltage drop of high potential power supply - Google Patents

Abstract

PURPOSE:To enable detecting voltage drop of a high potential power supply with a simple constitution in a detecting circuit for voltage drop of a high potential power supply which is incorporated in an integrated circuit to which high potential power supply voltage (H level power supply voltage) and low potential power supply voltage (L level power supply voltage) are supplied and used for detecting rapidly voltage drop of the high potential power supply. CONSTITUTION:When high potential power supply voltage is stabilized at the highest voltage, a capacitor 29 is charged at highest voltage-Vth-n. When high potential power supply voltage is started to drop from the highest voltage, a nMOS transistor 27 is turned off, and after that, when high potential power supply voltage is reduced to the lowest voltage-Vth-n-Vth-p, pMOS transistor 28 is turned on, the capacitor 29 is started to discharge, and a detecting signal for reduction of high potential power supply voltage is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a high potential power supply voltage (H level power supply voltage) and a low potential power supply voltage (L level power supply voltage).
The present invention relates to a high-potential power supply voltage drop detection circuit which is built in an integrated circuit to which is supplied and is used for detecting a high-potential power supply voltage drop at high speed.

Some integrated circuits have a high-potential power supply voltage, which is a high-potential power supply voltage or a low-potential power supply voltage supplied from an external power supply, having a different voltage value depending on the type of operation mode.

For example, SRAM which is a semiconductor memory device
In (static random access memory), the voltage value of the high-potential power supply voltage that is supplied in the cell data retention mode is the voltage value of the high-potential power supply voltage that is supplied in the write mode, read mode, and standby mode. There is something to lower.

For example, in such an SRAM, in the write mode, the read mode and the standby mode, a step-down voltage obtained by internally stepping down a high potential power supply voltage supplied from the outside is used as an internal high potential power supply voltage. However, in the cell data holding mode, the high potential power supply voltage supplied from the outside is used as it is as the internal power supply voltage.

In such an SRAM, when the voltage value of the high-potential power supply voltage supplied from the outside drops, that is, when the cell data holding mode is set, this is immediately detected and the internal high-potential power supply voltage is detected. High-speed switching from the step-down voltage to the high-potential power supply voltage is required. For this reason,
There is a need for a high-potential power supply voltage drop detection circuit that detects a high-potential power supply voltage drop at high speed.

[0006]

2. Description of the Related Art Hitherto, a high potential power supply voltage drop detecting circuit which meets such a request has not been proposed. Therefore, for example, it is conceivable to use a signal potential drop detection circuit as shown in FIG.

In the figure, 1 is a high potential power supply voltage input terminal to which a high potential power supply voltage is input from an external power supply, 2 is a low potential power supply voltage input terminal to which a low potential power supply voltage is input from an external power supply, and 3 is A signal input terminal, 4 is a delay circuit, 5 is an inverter, 6 and 7 are pMOS transistors, 8 is a resistor, and 9 is an output terminal.

FIG. 16 is a waveform diagram showing the operation of this signal potential drop detection circuit.
When the signal input to the signal input terminal 3 drops from H level to L level, a signal potential drop detection signal of H level is output to the output terminal 9.

[0009]

Even if the signal input terminal 3 is connected to the high potential power supply voltage input terminal 1 and the signal potential drop detection circuit is used as a high potential power supply voltage drop detection circuit, By doing so, the gate-source voltage VGS of the pMOS transistor 7 is always 0 [V].
Since the pMOS transistor 7 does not become conductive, the output terminal 9 is always at the L level, and the high potential power supply voltage drop detection signal cannot be output.
Hereinafter, the conductive state is referred to as ON and the non-conductive state is referred to as OFF.

Therefore, it is possible to use a signal potential drop detection circuit as shown in FIG. 1 in the figure
0 is a high potential power supply voltage input terminal, 11 is a low potential power supply voltage input terminal, 12 is a signal input terminal, 13 is a capacitor, 1
Reference numerals 4 and 15 are resistors, 16 is a pMOS transistor, and 17 is an output terminal.

FIG. 18 is a waveform diagram showing the operation of this signal potential drop detection circuit.
When the signal input to the signal input terminal 12 drops from the H level to the L level, the signal potential drop detection signal of the H level is output to the output terminal 17.

Even if the signal input terminal 12 is connected to the high-potential power supply voltage input terminal 10 and the signal potential drop detection circuit is to be used as a high potential power supply voltage drop detection circuit, the pMOS transistor is formed by doing so. The gate-source voltage VGS of 16 is always 0 [V], and pM
Since the OS transistor 16 is not turned on, the output terminal 17 is always at the L level, and the high potential power supply voltage drop detection signal cannot be output.

In view of the above points, an object of the present invention is to provide a high-potential power supply voltage drop detection circuit capable of detecting a drop in the high-potential power supply voltage with a simple structure.

[0014]

FIG. 1 is a diagram for explaining the principle of the present invention, in which 18 is a high potential power supply voltage input terminal to which a high potential power supply voltage is input, and 19 is a low potential power supply voltage. Is a low-potential power supply voltage input terminal, 20 and 21 are switch elements, 22 is a capacitor, 23 is a resistor, and 24 is an output terminal.

Here, the switch element 20 is turned on when the high-potential power supply voltage has a first voltage value, and is turned off when the high-potential power supply voltage drops from the first voltage value. It is a thing.

Further, the switch element 21 keeps O until the high-potential power supply voltage drops from the first voltage value to the second voltage value.
FF, which is turned on when the high-potential power supply voltage drops from the first voltage value to the second voltage value.

[0017]

In the present invention, when the high-potential power supply voltage is at the first voltage value, the capacitor 22 is charged via the switch element 20. In this case, since the switch element 21 maintains OFF, the voltage value of the output terminal 24 becomes the same as the voltage value of the low potential power supply voltage.

When the high-potential power supply voltage starts to drop from the first voltage value, the switch element 20 is turned off. In addition, the switching element 21 has a second high-potential power supply voltage.
It remains off until the voltage drops to. Therefore, also in this case, the voltage value of the output terminal 24 becomes the same as the voltage value of the low-potential power supply voltage.

After that, when the high-potential power supply voltage drops to the second voltage, the switch element 21 is turned on. In this way, when the switch element 21 is turned on, the capacitor 22 is turned on.
Is discharged via the switch element 21, and a high-potential power supply voltage drop detection signal having a voltage higher than the voltage value of the low-potential power supply voltage is output to the output terminal 24.

[0020]

EXAMPLES Examples of use of the first, second, third and third examples of the present invention will be described below with reference to FIGS.

First Embodiment ... FIG. 2 and FIG. 3 FIG. 2 is a circuit diagram showing a first embodiment of the present invention, in which 25 is a high-potential power supply to which a high-potential power supply voltage whose maximum voltage is VA is input. Voltage input terminal, 26 is a low potential power supply voltage input terminal to which a low potential power supply voltage is input, 27 is an nMOS transistor, 28 is a pMOS transistor, 29 is a capacitor,
Reference numeral 30 is a resistor, and 31 is an output terminal.

FIG. 3 is a waveform diagram showing the operation of the first embodiment, that is, the high potential power supply voltage, the low potential power supply voltage, and the node 3
2 voltage, high potential power supply voltage drop detection signal (output terminal 31
Voltage).

That is, in the first embodiment, when the high potential power supply voltage is stable at the maximum voltage VA, the voltage of the node 32 becomes VA-Vth-n (threshold voltage of nMOS transistor), The capacitor 32 is V
It is charged to A-Vth-n.

In this case, since the gate voltage of the pMOS transistor 28 is set to VA, the pMOS transistor 28 maintains the gate voltage> source voltage and remains off. Therefore, in this case, the voltage of the output terminal 31 becomes the voltage value of the low potential power supply voltage.

When the high-potential power supply voltage starts to drop from the maximum voltage VA at t (time) = T1, the gate voltage of the nMOS transistor 27 also starts to drop, and in this case, the node 32. Voltage of the capacitor 2
Since it is maintained at VA-Vth-n by 9, the nMOS transistor 27 is turned off because the gate voltage-source voltage <Vth-n.

On the other hand, the gate voltage of the pMOS transistor 28 also begins to drop.
8 is the gate voltage = the voltage of the node 32−Vth-p (pMO
Until it reaches the threshold voltage of the S transistor)
It does not turn on.

Therefore, after the high-potential power supply voltage starts to drop from VA, the output terminal 31 remains until the gate voltage of the pMOS transistor 28 becomes VA-Vth-n-Vth-p.
Continues to maintain the voltage value of the low-potential power supply voltage.

At t = T2, the high potential power supply voltage is
When the voltage drops to VA-Vth-n-Vth-p, the pMOS transistor 28 turns ON and the capacitor 29 starts discharging. In this case, if the resistance 30 is set to a relatively high resistance value, the output terminal 31 receives Outputs a high-potential power supply voltage drop detection signal having a discharge characteristic as shown in FIG. 3 and detects that the high-potential power supply voltage has dropped.

When t = T3 and the drop of the high potential power supply voltage is completed, the voltage of the node 32 <high potential power supply voltage + V
At the time of th-p, pMOS transistor 28 = OF
F, and the voltage of the output terminal 31 again decreases toward the voltage value of the low-potential power supply voltage.

According to the first embodiment, the drop of the high-potential power supply voltage can be detected at high speed with the simple structure of forming the nMOS transistor 27, the pMOS transistor 28, the capacitor 29, and the resistor 30. it can.

Second Embodiment ... FIGS. 4 and 5 FIG. 4 is a circuit diagram showing a second embodiment of the present invention. In this second embodiment, the high potential power supply voltage input terminal 25 is diode-connected. It is connected to the gate of the pMOS transistor 28 via the nMOS transistor 33.

A clamp resistor 34 having a resistance value sufficiently higher than the ON resistance of the nMOS transistor 33 is connected between the gate of the pMOS transistor 28 and the low potential power supply voltage input terminal 26. Others are the same as those of the first embodiment shown in FIG.

FIG. 5 is a waveform diagram showing the operation of the second embodiment, that is, the high potential power supply voltage, the low potential power supply voltage, and the node 3
2 shows the voltage of 2, the voltage of the node 35, and the high-potential power supply voltage drop detection signal (voltage of the output terminal 31).

That is, in the second embodiment, when the high potential power supply voltage is stable at the maximum voltage VA, the voltage of the node 32 becomes VA-Vth-n, and the capacitor 29 has VA-Vth.
-charged to n. Further, in this case, the voltage of the node 35 becomes VA-Vth-n.

Here, at t = T1, the high potential power supply voltage is V
When the voltage starts to drop from A, the gate voltage of the nMOS transistor 27 also starts to drop, but in this case, the voltage of the node 32 is maintained at VA-Vth-n by the capacitor 29. The source-to-source voltage becomes <Vth-n, and the source is turned off.

On the other hand, the gate voltage of the pMOS transistor 28 also begins to drop.
8 is not turned on until the gate voltage = the voltage of the node 32-Vth-p.

Therefore, after the high-potential power supply voltage starts to drop from VA, until the gate voltage of the pMOS transistor 28 becomes VA-Vth-n-Vth-p, that is, the high-potential power supply voltage is VA-Vth-p. The voltage of the output terminal 31 continues to maintain the voltage value of the low-potential power supply voltage until it becomes.

When the voltage of the node 35 becomes VA-Vth-n-Vth-p at t = T4, the pMOS transistor 28 becomes ON and the capacitor 29 starts discharging. A high-potential power supply voltage drop detection signal having a discharge characteristic as shown in FIG. 5 is output, and it is detected that the high-potential power supply voltage has dropped.

When the drop of the high potential power supply voltage is completed at t = T5, the voltage of the node 32 <high potential power supply voltage −V
When th-n + Vth-p, the pMOS transistor 2
8 = OFF, and the voltage of the output terminal 31 drops again toward the voltage value of the low-potential power supply voltage.

According to the second embodiment, the nMOS transistors 27 and 33, the pMOS transistor 28, the capacitor 29, and the resistors 30 and 34 are simply formed to quickly drop the high-potential power supply voltage. Can be detected.

Further, according to this second embodiment, the node 3
When the voltage of 5 becomes VA-Vth-n-Vth-p, that is, when the high-potential power supply voltage drops to VA-Vth-p,
Since a high-potential power supply voltage drop detection signal can be obtained,
The high-potential power supply voltage drops faster than in the first embodiment configured so that the high-potential power supply voltage drop detection signal can be obtained when the high-potential power supply voltage drops to VA-Vth-n-Vth-p. Can be detected.

Third Embodiment FIG. 6 to FIG. 8 FIG. 6 is a circuit diagram showing a third embodiment of the present invention. In the third embodiment, a high potential power supply voltage input terminal 25 and a node 35 are provided. A capacitor 36 having a capacitance value larger than the parasitic capacitance of the node 35 is connected between the two, and the other parts are configured similarly to the second embodiment.

Here, in the second embodiment, the clamp resistor 3
Idling current flows through 4. To suppress this idling current to a minimum, clamp resistor 3
It is better to increase the resistance value of 4, but if you do this,
It takes time to discharge the capacitance parasitic on the node 35, and the reaction is delayed with respect to a sharp drop of the high-potential power supply voltage.

FIG. 7 is a waveform diagram showing the operation of the second embodiment when the resistance value of the clamp resistor 34 is increased and the idling current flowing through the clamp resistor 34 is reduced. The low potential power supply voltage, the voltage of the node 32, the voltage of the node 35, and the high potential power supply voltage drop detection signal (voltage of the output terminal 31) are shown.

On the other hand, FIG. 8 is a diagram showing the operation of the third embodiment. In the third embodiment, when the high-potential power supply voltage is stable at the maximum voltage VA, the node 32 has a high voltage. The voltage is VA-Vth-n, and the capacitor 29 is VA-V.
Charged to th-n. Further, in this case, the voltage of the node 35 becomes VA-Vth-n.

Here, at t = T1, the high potential power supply voltage is V
When the voltage starts to drop from A, the gate voltage of the nMOS transistor 27 also starts to drop, but in this case, the voltage of the node 32 is maintained at VA-Vth-n by the capacitor 29. The voltage between them becomes <Vth, and it becomes OFF.

A capacitor 36 having a larger capacitance value than the parasitic capacitance of the node 35 is connected between the high-potential power supply voltage input terminal 25 and the node 35. , Node 35
Will drop following the high potential power supply voltage.

Therefore, according to the third embodiment, similarly to the second embodiment, at t = T3, that is, when the high potential power supply voltage drops to VA-Vth-p, the high potential power supply voltage drops. A detection signal can be obtained.

According to the third embodiment, the nMOS transistors 27 and 33, the pMOS transistor 28, the capacitors 29 and 36, and the resistors 30 and 34 are simply formed to reduce the high-potential power supply voltage. It can be detected at high speed.

Further, according to the third embodiment, since the high-potential power supply voltage drop detection signal can be obtained when the high-potential power supply voltage drops to VA-Vth-p, the high-potential power supply voltage is VA. It is possible to detect the drop of the high-potential power supply voltage faster than in the first embodiment configured so that the high-potential power-supply voltage drop detection signal can be obtained when the voltage drops to -Vth-n-Vth-p. .

Further, according to the third embodiment, the resistance value of the clamp resistor 34 can be increased, and the idling current flowing through the clamp resistor 34 can be suppressed to be smaller than that in the second embodiment.

Example of Use of Third Embodiment FIG. 9 to FIG. 12 FIG. 9 is a diagram showing an example of use of the third embodiment of the present invention.
RAM is shown. In this SRAM, in the write mode, the read mode, and the standby mode, the step-down voltage obtained by internally stepping down the high potential power supply voltage VCC supplied from the outside is used as the internal high potential power supply voltage VDD, and the cell data is retained. In the mode, the lowered external high potential power supply voltage VCC supplied from the outside is used as it is as the internal high potential power supply voltage VDD.

In the figure, 37 is a chip body, and 38 is a high-potential power supply voltage drop detection circuit according to the third embodiment, which is used to detect a drop in the high-potential power supply voltage VCC supplied from an external power supply. .

Further, 39 is a high-potential power supply voltage detection circuit for detecting the high-potential power supply voltage VCC, and 40 to 44 are nM.
OS transistors, 45, 46 are clamp resistors, 47,
Reference numeral 48 is an inverter, and 49 is a pMOS transistor.

Reference numeral 50 is an internal high-potential power supply voltage supply circuit for supplying the internal high-potential power supply voltage VDD to the internal circuit, 51 is a pMOS transistor, and 52 is an nMOS transistor.

That is, the internal high potential power supply voltage supply circuit 5
When the pMOS transistor 51 is turned off, 0 is the step-down voltage VC as the internal high potential power supply voltage VDD.
Supply C-Vth-n, pMOS transistor 51 = ON
In this case, the high potential power supply voltage VCC supplied from the outside is directly supplied as the internal high potential power supply voltage VDD.

53 and 54 are row address signals A
Row address signal input terminal for inputting 0 and A1,
Reference numeral 55 waveform-shapes the row address signal input through the row address signal input terminal, and outputs internal row address signals a0, / a0, a1, and / a1 obtained by converting these row address signals A0 and A1 into complementary signals. It is a row address buffer.

Reference numeral 56 is a row decoder for decoding the row address signals A0, A1 input via the row address buffer 55 using the internal row address signals a0, / a0, a1, / a1, and 57 is a cell. It is an array of cell arrays.

Here, the row address buffer 55, the row decoder 56, and the cell array section 57 are specifically configured, for example, as shown in FIG. In the figure, WL
0 to WL3 are word lines, and BL0 to / BL3 are bit lines.

Further, in FIG. 9, 58 and 59 are column address signal input terminals for inputting the column address signals A2 and A3, and 60 is a waveform shaping of the column address signal input through the column address signal input terminal. , Internal column address signals a2, / a2, a3, / a3 obtained by converting these column address signals A2, A3 into complementary signals.
Is a column address buffer that outputs

Further, 61 is a column address buffer 60.
A column decoder for decoding the column address signals A2 and A3 input via the internal column address signals a2, / a2, a3 and / a3.

CL0 to CL3 are column decoders 6
1 is a column selection signal line derived from 1, and 62 is a column selection circuit for selecting a column in accordance with the column selection signal output from the column decoder 61.

Here, the column address buffer 60, the column decoder 61 and the column selection circuit 62 are specifically constructed as shown in FIG. 11, for example. DB to / DB are data buses.

Further, in FIG. 9, 63 is a data input terminal for inputting the data DI to be written in the cell array portion, and 64 is a data input buffer for waveform-shaping the data DI input via the data input terminal 63. is there.

Reference numeral 65 is a write amplifier for writing the data DI output from the data input buffer 64 into the cells designated by the row address signals A0 and A1 and the column address signals A2 and A3.

Further, 66 is a chip selection signal input terminal for inputting the chip selection signal / CS, and 67 is a chip selection signal / CS input through the chip selection signal input terminal 66.
It is a chip selection signal input buffer that shapes the waveform of CS.

Further, 68 is a write control signal input terminal for inputting a write control signal / WE, and 69 is a write control signal / input via the write control signal input terminal 68.
It is a write control signal input buffer that shapes the waveform of WE.

Further, 70 is a sense amplifier for amplifying the data read from the cell array section 57, 71 is a data output buffer for outputting the data amplified by the sense amplifier 70 to the outside, and 72 is a data output buffer 7.
1 is a data output terminal to which the output data DO from 1 is output.

Here, the data input buffer 64, the write amplifier 65, the chip selection signal input buffer 67, the write control signal input buffer 69, the sense amplifier 70, and the data output buffer 71 are specifically shown in FIG. 12, for example. Is configured.

FIG. 13 shows the high-potential power supply voltage drop detection circuit 3
8 is a waveform diagram showing the operation of the high-potential power supply voltage detection circuit 39 when there is no 8;
CC, the voltage of the node 73, and the voltage of the node 74 are shown.

When the high-potential power supply voltage VCC supplied from the outside is at VB of 3 Vth-n or less, the nMOS transistors 40 to 42 = OFF and the node 73 = L level.

As a result, the nMOS transistor 43 = 0
The FF, the node 74 = H level, the output voltage of the inverter 48 = L level, the pMOS transistor 51 = ON, and the high potential power supply voltage VCC externally supplied as the internal high potential power supply voltage VDD is supplied as it is.

From this state, when the high-potential power supply voltage VCC rises and exceeds 3Vth-n, the nMOS transistors 40 ...
42 = ON, and the voltage of the node 73 starts rising from the L level following the high potential power supply voltage VCC.

Here, the high potential power supply voltage VCC is 4Vth-n.
NMOS transistor 43 = ON, node 74 = L level, output voltage of inverter 48 = H level, pMOS transistor 51 = OFF, and internal high potential power supply voltage supply circuit 50 outputs internal high potential power supply voltage V
The step-down voltage VCC-Vth-n is supplied as DD.

After that, the high potential power supply voltage VCC is 4 Vth-n.
The high potential power supply voltage VCC starts to drop from this state, and when the high potential power supply voltage VCC becomes lower than 4Vth-n, the nMOS transistor 42 is turned off.

As a result, the node 74 = H level, the output voltage of the inverter 48 = L level, the pMOS transistor 51 = ON, and the internal high-potential power supply voltage supply circuit 50 replaces the step-down voltage as the internal high-potential power supply voltage VDD. The high-potential power supply voltage VCC supplied from the outside is supplied as it is.

When the high-potential power supply voltage is VA, current flows through the clamp resistors 45 and 46 when the nMOS transistors 40 to 43 = ON. In order to suppress this current to a small value, the resistance values of the clamp resistors 45 and 46 may be increased.

However, in this case, when the high potential power supply voltage VCC starts to drop, it takes time to discharge the parasitic capacitance of the node 73 as shown by the broken line 75 in FIG. Even if VCC becomes 4Vth-n or less, the node 73 does not immediately become Vth-n or less, and the nMOS transistor 43 = ON and the node 74 = L.
Maintain the level.

Even if the voltage of the node 73 drops below Vth-n and the nMOS transistor 43 is turned off, it takes time to charge up the node 74, and the voltage of the node 73 is at the L level. The change from the H level to the H level is blunted as shown by the broken line 76 in FIG.
In some cases, the output voltage of the inverter 48 cannot be set to the L level and the pMOS transistor 51 cannot be set to ON, and the high potential power supply voltage VCC is supplied from the internal high potential power supply voltage supply circuit 50 as the internal high potential power supply voltage VDD. The inconvenience of not being able to occur occurs.

In order to eliminate this inconvenience, a high potential power supply voltage drop detection circuit 38 is provided. FIG. 14 is a waveform diagram showing the operation of the high-potential power supply voltage drop detection circuit 38 and the high-potential power supply voltage detection circuit 39. The high-potential power supply voltage VCC supplied from the external power supply, the voltage of the node 32, and the voltage of the node 73. , The voltage of the node 74 and the high-potential power supply voltage drop detection signal.

It is preferable that the nMOS transistor 44 has a drivability sufficiently smaller than that of the nMOS transistors 40 to 42, and that the parasitic capacitance of the node 73 can be discharged relatively quickly. Is.

Further, it is preferable that the pMOS transistor 49 has a driving capacity sufficiently smaller than that of the nMOS transistor 43, and the parasitic capacitance of the node 74 can be charged up relatively quickly. .

Here, until the high potential power supply voltage VCC starts to rise from the minimum voltage VB and reaches the maximum voltage VA, nMO
S transistor 27 = ON, pMOS transistor 28
= OFF, the capacitor 29 is charged to VCC-Vth-n.

In this case, node 77 = L level (0
[V]), the nMOS transistor 44
Gate voltage = L level, the nMOS transistor 44
= OFF. Therefore, as described above, the high-potential power supply voltage detection circuit 39 operates similarly to the case where the high-potential power supply voltage drop detection circuit 38 is not provided.

When the high-potential power supply voltage VCC starts to drop from the maximum voltage VA, the high-potential power supply voltage drop detection circuit 38, at the time point when it drops by Vth-p, the high-potential power supply at the H level is applied to the node 77. Output the voltage drop detection signal.

As a result, the nMOS transistor 44 = 0
N, pMOS transistor 49 = ON, node 7
3 is discharged at high speed, the nMOS transistor 43 is turned off, the node 74 is charged up at high speed, and the voltage of the node 77 can be set to the H level at high speed.

That is, the output voltage of the inverter 48 at high speed =
L level, from the internal high potential power supply voltage supply circuit 50,
Instead of the step-down voltage, the high potential power supply voltage VCC supplied from the outside can be directly supplied as the internal high potential power supply voltage VDD.

As described above, when the high-potential power supply voltage drop detection circuit 38 of the third embodiment is used, the clamp resistor 4 is used.
Even if the resistance values of 5 and 46 are increased, the high-potential power supply voltage VC
The drop of C can be detected at high speed, and the internal high-potential power supply voltage VDD output from the internal high-potential power supply voltage supply circuit 50 can be switched at high speed.

A PN junction diode can be used instead of the diode-connected nMOS transistors 27 and 33. As for the capacitors 29 and 36, parasitic capacitance may be used as long as sufficient capacitance can be secured without forming any element.

[0090]

According to the present invention, it is possible to detect a drop in the high-potential power supply voltage with a simple structure.
In write mode, read mode, and standby mode, the high-potential power supply voltage supplied from the outside is used as the internal high-potential power supply voltage.
When used in an SRAM configured to use an externally supplied high-potential power supply voltage as the internal high-potential power supply voltage in the cell data holding mode, the internal high-potential power supply voltage is changed from the step-down voltage to the high-potential power supply voltage. This can be done quickly when switching.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a waveform chart showing the operation of the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a waveform diagram showing the operation of the second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

FIG. 7 is a waveform diagram showing the operation when the resistance value of the clamp resistor is increased in the second embodiment of the present invention.

FIG. 8 is a waveform chart showing the operation of the third embodiment of the present invention.

FIG. 9 is a circuit diagram showing a usage example of the third embodiment of the present invention.

FIG. 10 is a circuit diagram showing a specific configuration of part of the SRAM shown in FIG. 9 (row address buffer, row decoder, and cell array section).

FIG. 11 is a circuit diagram showing a specific configuration of part of the SRAM shown in FIG. 9 (a column address buffer, a column decoder, and a column selection circuit).

FIG. 12 is a part of the SRAM shown in FIG. 9 (a data input buffer, a write amplifier, a chip selection signal input buffer,
FIG. 6 is a circuit diagram showing a specific configuration of a write control signal input buffer, a sense amplifier, and a data output buffer).

FIG. 13 is a waveform diagram showing the operation of the high-potential power supply voltage detection circuit when there is no high-potential power supply voltage drop detection circuit in the usage example of the third embodiment of the present invention.

FIG. 14 is a waveform diagram showing operations of the high-potential power supply voltage drop detection circuit and the high-potential power supply voltage detection circuit in the usage example of the third embodiment of the present invention.

FIG. 15 is a circuit diagram showing an example of a signal potential drop detection circuit.

16 is a waveform chart showing an operation of the signal potential drop detection circuit shown in FIG.

FIG. 17 is a circuit diagram showing another example of a signal potential drop detection circuit.

18 is a waveform chart showing an operation of the signal potential drop detection circuit shown in FIG.

[Explanation of symbols]

 18 High-potential power supply voltage input terminal 19 Low-potential power supply voltage input terminal 20, 21 Switch element 22 Capacitor 23 Resistance

Claims (4)

[Claims] 1. One end is connected to a high-potential power supply voltage input terminal (18) to which a high-potential power supply voltage is input, and when the high-potential power supply voltage has a first voltage value, it is rendered conductive. A first switch element (20) that is rendered non-conductive when the high-potential power supply voltage drops from the first voltage value.
And a capacitor (22) having one end connected to the other end of the first switch element (20) and the other end connected to a low potential power supply voltage input terminal (19) to which a low potential power supply voltage is input.
And one end is connected to one end of the capacitor (22),
The high-potential power supply voltage is brought into a non-conducting state until the high-potential power supply voltage drops from the first voltage value to the second voltage value, and the high-potential power supply voltage drops from the first voltage value to the second voltage value. The second switch element (2
1) and one end thereof is connected to the other end of the second switch element (21), and the other end thereof is connected to the low potential power supply voltage input terminal (1
And a resistor (23) connected to 9), and is configured to obtain a high-potential power supply voltage drop detection signal at the other end of the second switch element (21). Voltage drop detection circuit. 2. An nMOS transistor (27) having a drain and a gate connected to a high-potential power supply voltage input terminal (25) to which a high-potential power supply voltage is input, and one end of the nMOS transistor (27).
A low-potential power supply voltage input terminal (2 connected to the source of the transistor (27) and having the other end input with the low-potential power supply voltage
6), a pMOS transistor (28) having a source connected to the capacitor (29) and a gate connected to the high-potential power supply voltage input terminal (25), and one end of the pMOS transistor (28). Transistor (2
And a resistor (30) connected to the drain of 8) and the other end of which is connected to the low-potential power supply voltage input terminal (26),
A high-potential power supply voltage drop detection circuit configured to obtain a high-potential power supply voltage drop detection signal at the drain of the pMOS transistor (28). 3. A first and second nMOS transistor (27, 33) whose drain and gate are connected to a high-potential power supply voltage input terminal (25) to which a high-potential power supply voltage is input.
A capacitor (29) having one end connected to the source of the first nMOS transistor (27) and the other end connected to a low potential power supply voltage input terminal (26) to which a low potential power supply voltage is input; Is connected to the capacitor (29), and the gate is connected to the second nMOS transistor (3
3) The pMOS transistor (2
8), a first resistor (30) having one end connected to the drain of the pMOS transistor (28) and the other end connected to the low potential power supply voltage input terminal (26), and one end connected to the second resistor (30). a second resistor (34) connected to the source of the nMOS transistor (33) and the other end of which is connected to the low potential power supply voltage input terminal (26), and a high potential is applied to the drain of the pMOS transistor (28). A high-potential power supply voltage drop detection circuit configured to obtain a power supply voltage drop detection signal. 4. A first and second nMOS transistor (27, 33) whose drain and gate are connected to a high-potential power supply voltage input terminal (25) to which a high-potential power supply voltage is input.
A capacitor (29) having one end connected to the source of the first nMOS transistor (27) and the other end connected to a low potential power supply voltage input terminal (26) to which a low potential power supply voltage is input; Is connected to the capacitor (29), and the gate is connected to the second nMOS transistor (3
3) The pMOS transistor (2
8), a first resistor (30) having one end connected to the drain of the pMOS transistor (28) and the other end connected to the low potential power supply voltage input terminal (26), and one end connected to the second resistor (30). A second resistor (34) connected to the source of the nMOS transistor (33) and having the other end connected to the low potential power supply voltage input terminal (26), and one end to the high potential power supply voltage input terminal (25). Connected to the other end of the pMOS
A second capacitor (36) connected to the gate of the transistor (28), and configured to obtain a high-potential power supply voltage drop detection signal at the drain of the pMOS transistor (28). High potential power supply voltage drop detection circuit.