JP3141494B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a dynamic random access memory (DRAM).
ndom access memory) and SRAM (staticrandom acc.
The present invention relates to a semiconductor memory device including a signal transmission line shared by a plurality of columns, a so-called data bus, and a read amplifier circuit, a so-called sense buffer, provided at the end of the data bus.

In recent years, in a semiconductor memory device such as a DRAM or an SRAM, an MO mounted on the
With the miniaturization of S transistors being advanced, the power supply voltage has been reduced to 5
There is a need to lower the voltage from [V] to 3 [V] or less.

Here, even when the power supply voltage is lower than 5 [V], the threshold voltage of the MOS transistor is determined by taking the sub-threshold current characteristic into consideration.
It cannot be reduced in proportion to the power supply voltage. This is because the sub-threshold current characteristic is determined by a physical mechanism regardless of the power supply voltage.

If the power supply voltage is set lower than 5 [V], the threshold voltage of the MOS transistor occupies a relatively large proportion of the power supply voltage, causing various inconveniences in circuit operation. Become. Therefore, if this is not solved, lowering the power supply voltage,
That is, high integration cannot be achieved.

[0005]

2. Description of the Related Art Conventionally, there is known a DRAM as shown in FIG. In the figure, WL is a word line, BL and / BL are bit lines, 1 is a memory cell,
Reference numeral 2 denotes an nMOS transistor serving as a transfer gate, and reference numeral 3 denotes a capacitor.

Reference numeral 4 denotes a sense amplifier, and reference numeral 5 denotes a sense amplifier driving circuit for driving the sense amplifier 4. In the sense amplifier 4, reference numerals 6 and 7 denote pMOS transistors;
Reference numeral 9 denotes an nMOS transistor, and a sense amplifier driving circuit 5. Reference numeral 10 denotes a Vcc power supply line for supplying a power supply voltage Vcc;
1 is a pMOS transistor, 12 is an nMOS transistor, and φ _SA and / φ _SA are sense amplifier activation signals.

Reference numeral 13 denotes a column decoder for decoding a column address. Reference numeral 14 denotes a column selection gate for selecting a column. In the column decoder 13, 15 is a NAND circuit, 16 is an inverter, and φ _CA is a column decoder activation signal. , Φ _CL are column selection signals, and in the column selection gate 14, 17 and 18 are nMOS transistors.

Further, DB and / DB are data buses shared by a plurality of columns, and 19 is Vcc for supplying a power supply voltage Vcc.
A power supply line, 20 and 21 are nMOS transistors, and / WE is a write signal. The write signal / WE is Vcc [V] at the time of reading and 0 [V] at the time of writing.

Here, the nMOS transistors 20, 21
Represents the voltage of the data buses DB and / DB as Vcc-Vth-n
(Threshold voltage of the nMOS transistor) and a load on the data buses DB and / DB as a load of the sense amplifier connected to the bit lines connected to the data buses DB and / DB, such as the sense amplifier 4. It serves to make the voltage amplitude of the signal an appropriate value.

[0010] Further, at the time of reading, the data bus D
B, and a sense buffer for amplifying a small signal on / DB.
The differential amplifier circuits 24 and 25 share the MOS transistor 23, 26 to 29 are nMOS transistors as input transistors, 30 to 33 are pMOS transistors as loads, and φ _SB is a sense buffer activation signal. It is.

At the time of reading, data buses DB and / DB
Is reset to Vcc-Vth-n, so that the nMOS transistors 26 to 29 of the sense buffer 22
The operation is performed using th-n as a gate bias voltage.

Reference numeral 34 denotes an RS flip-flop for latching the output of the sense buffer 22, and reference numerals 35 and 36 denote sense buffer activation signals φ _SB = “L”.
2 is deactivated and its output becomes indeterminate,
This is a pMOS transistor for setting the level of both the reset terminal R and the set terminal S of the RS flip-flop 34 to “H” and causing the RS flip-flop 34 to hold the logic state determined before that.

[0013]

Here, the bit line B
Since L and / BL are reset to Vcc / 2 at the time of reading, the sense amplifier 4 starts operating from a voltage near Vcc / 2. Further, the column selection gate 14 is turned on before the sense amplifier 4 completes the amplification to speed up the access.

As a result, the sense amplifier 4
The voltage difference between the data bus connected to the bit line amplified to the [V] side and the bit line amplified to the 0 [V] side is (Vcc-Vth-n) -Vcc / 2 + α = Vcc
/ 2−Vth−n + α. α is the voltage amplified by the sense amplifier 4.

Here, the case where the power supply voltage Vcc is made lower than 5 [V] in consideration of the miniaturization of the MOS transistor based on the high integration is examined. Note that even in this case, the threshold voltage of the MOS transistor is
As described above, in consideration of the subthreshold current characteristic, it cannot be reduced in proportion to the power supply voltage.

In such a conventional DRAM, the power supply voltage Vcc
, The voltage difference between the data bus connected to the bit line amplified to the 0 [V] side and the bit line amplified to the 0 [V] side decreases, and eventually the voltage difference becomes 0. [V]. For example, Vcc = 1.5 [V], Vt
If hn = 0.5 [V] and α = 0.1 [V], Vcc /
2-Vth-n + α = 0.35 [V].

The fact that this value is small means that when a column is selected, the sense amplifier 4 operates on the data buses DB and //.
This means that the momentum for driving the DB is reduced, and as a result, there is a disadvantage that the access time is delayed.

Therefore, the data buses DB and / DB are connected to Vcc-
Considering the case of resetting to Vcc instead of resetting to Vth-n, the data bus connected to the bit line amplified to 0 [V] side and amplified to 0 [V] side The voltage difference between the bit line and the bit line is Vcc / 2 + α. For example, similarly to the above example, Vcc = 1.5 [V], α
= 0.1 [V], Vcc / 2 + α = 0.85 [V]
Becomes

As described above, the data buses DB and / DB are connected to V
When resetting to cc, the sense amplifier 4
The voltage difference in anticipation of the data bus connected to the bit line amplified on the [V] side can be increased, and this data bus can be driven strongly, so that access delay can be prevented.

However, resetting the data buses DB and / DB to the power supply voltage Vcc causes the gates of the nMOS transistors 26 to 29 of the sense buffer 22 to be biased to Vcc, which significantly lowers the amplification of the sense buffer 22. In some cases, this may be caused.

That is, since the pMOS transistors 30 to 33 constituting the current mirror circuit are connected as loads to the nMOS transistors 26 to 29 of the sense buffer 22, the maximum value of the drain voltage of the nMOS transistors 26 to 29 is Vcc.

Therefore, the nMOS transistors 26 to 29
When the gates of the nMOS transistors 26 to 29 are biased to Vcc, the nMOS transistors 26 to 29 may be in a state in which the drain voltage is lower than the gate voltage, that is, a so-called triode region, that is, a bias state in which the transconductance gm is low.
As a result, the amplification factor of the sense buffer 22 is significantly reduced, and as a result, there may be a case where the data bus signal is not sufficiently amplified.

This inconvenience can be solved by increasing the number of amplification stages of the sense buffer 22, but in such a case, the signal delay becomes large, and the access time becomes long. However, there is an inconvenience that current consumption increases.

In the conventional DRAM shown in FIG. 6, at the time of reading, nMOSs 20, 21 have V.sub.
cc [V] is supplied to the diode-connected state, and the diode-connected nMOS transistor 2
Data buses DB and / DB are pulled up by 0 and 21.

For this reason, when a bump-down phenomenon, that is, a phenomenon in which the power supply voltage Vcc instantaneously drops during operation occurs, n
The MOS transistors 20 and 21 are cut off, and the data buses DB and / DB having a large parasitic capacitance of several picofarads are left in a high voltage state.

On the other hand, the power supply voltage Vcc of the sense buffer 22
Falls due to bump down, so that the gate voltages of the nMOS transistors 26 to 29 are relatively excessively high.

As a result, the nMOS transistors 26-2
No. 9 has a problem that bias is applied to a triode region having a low gm, the amplification degree of the sense buffer 22 is reduced, and access is slowed. That is, there is a problem that the access time is affected by the power supply noise.

In view of the above, the present invention provides a semiconductor memory device that can achieve high-speed access even when the power supply voltage is reduced, and that is not affected by access time due to power supply noise. The purpose is to:

[0029]

FIG. 1 is a diagram for explaining the principle of the present invention. A semiconductor memory device according to the present invention comprises a data bus 3 shared by a plurality of columns 37 ₁ , 37 ₂ ... 37 _n.
8 and a read amplification circuit provided at the end of the data bus 38, that is, an input transistor 40 of a sense buffer 39, a Vcc power supply line 42 for supplying a power supply voltage Vcc, A resistive element 43 for supplying a power supply voltage Vcc to the data bus 38 at the time of reading is provided between the sense buffer 39 and the bus 38.
And a bias circuit 44 for biasing the gate voltage of the input transistor 40 to a voltage Vpr lower than the power supply voltage Vcc.

Reference numeral 45 denotes a memory cell array portion in which memory cells are arranged, 46 ₁ , 46 ₂ , 46 _{n denote} column select gates, and 47 denotes a Vpr voltage line for supplying a voltage Vpr.

Here, the power supply voltage Vcc may be a power supply voltage supplied from outside the chip, or a power supply voltage obtained by stepping down a power supply voltage supplied from outside the chip inside the chip. It may be.

The resistance element 43 may be constituted by a pure resistance using a material such as polysilicon.
The configuration may be such that the channel resistance of the S transistor is used.

[0033]

According to the present invention, the data bus 38 is connected to the power supply voltage V.
When resetting to cc and reading, columns 37 ₁ , 37 ₂ ...
Since the voltage difference in view of the data bus 38 from 37 _n can be increased and the data bus 38 can be driven strongly, the access can be speeded up.

According to the present invention, the sense buffer 3
9 to the power supply voltage Vcc.
Voltage Vpr can be biased lower than
Even when the drain voltage of the input transistor 40 of the sense buffer 39 becomes the power supply voltage Vcc, the input transistor 40 can be operated in the pentapole region where gm is high.

Therefore, data bus 38 is connected to power supply voltage V
Even if resetting to cc, it is not necessary to increase the number of amplification stages of the sense buffer 39, and from this point, it is possible to speed up access.

According to the present invention, the data bus 38
Is connected to the Vcc power supply line 42 via the resistance element 43 at the time of reading. Therefore, when the power supply voltage Vcc drops momentarily due to power supply noise, the voltage of the data bus 38 also drops and the input transistor of the sense buffer 39 Since the gate voltage of 40 also drops, it is possible to prevent the access time from being affected by power supply noise.

The bias circuit 44 is connected to the Vpr voltage line 4
7 and the input transistor 40 of the sense buffer 39 are turned off while any of the column select gates 46 ₁ , 46 ₂ ... 46 _n is turned on, and turned on during the other periods. And a switch element controlled so that

The bias circuit 44 is connected to the Vpr voltage line 4
7 and the input transistor 40 of the sense buffer 39, the time constant of the capacitive element 41
_1, 46 ₂ ... 46 one of _n can also be configured by connecting a resistor having a resistance value that is larger than the period that is turned on.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIGS.
Embodiments 1 to 3 will be described with reference to an example in which the present invention is applied to a DRAM. 2, 4, and 5
In FIG. 6, the portions corresponding to those in FIG. 6 are denoted by the same reference numerals, and the description thereof will be omitted.

(1) First Embodiment FIGS. 2 and 3 FIG. 2 is a circuit diagram showing a main part of a first embodiment of the present invention.
In the first embodiment, an enhancement-type nMOS transistor is provided between the data bus DB and the nMOS transistors 26 and 28 of the sense buffer 22, and between the data bus / DB and the nMOS transistors 27 and 29 of the sense buffer 22, respectively. Transistor capacity 48, 4
9 is connected.

Further, between the Vcc power supply line 19 and the data bus DB and between the Vcc power supply line 19 and the data bus / DB,
The respective pMOS transistors 50 and 51 forming a load transistor are connected. In addition, these pM
The gates of the OS transistors 50 and 51 are supplied with an inverted write signal WE having an inverted relationship with the write signal / WE.

Therefore, at the time of reading, write signal / WE
= "H" and the inverted write signal WE = "L",
The pMOS transistors 50 and 51 are turned on, and the power supply voltage Vcc is supplied to the data buses DB and / DB.
At the time of writing, if the write signal / WE = “L” and the inverted write signal WE = “H”, the pMOS transistors 50 and 51 are turned off.

In FIG. 2, reference numeral 52 denotes a power supply voltage Vcc.
A Vpr voltage line for supplying a lower voltage Vpr, between the Vpr voltage line 52 and the gates of the nMOS transistors 26 and 28 and between the Vpr voltage line 52 and the gates of the nMOS transistors 27 and 29, respectively. , PMOS
The transistors 53 and 54 are connected.

A pMOS transistor 55 for short-circuiting the gates of the nMOS transistors 26 and 28 and the gates of the nMOS transistors 27 and 29 between the gates of the nMOS transistors 26 and 28 and the gates of the nMOS transistors 27 and 29. Is connected.

The pMOS transistors 53 to 53
The gates 55, column decoder activation signal phi _CA is supplied. For the rest, the conventional DRA shown in FIG.
It has the same configuration as M.

FIGS. 3A and 3B are waveform diagrams for explaining the operation of the first embodiment. In the first embodiment, the column decoder activating signal φ _CA = “ L "
During the period when the column selection signal φ _{CL is set to} “L” and all the column selection gates connected to the data buses DB and / DB, such as the column selection gate 14, are turned off, pM
OS transistors 53 to 55 are turned on, and nMO
The voltage Vpr is supplied to the gates of the S transistors 26 to 29 as a bias voltage.

Here, the sense buffer activation signal φ _SB =
At “H”, the sense buffer 22 is activated.
When the column decoder activating signal φ _CA = “H”, for example, the column selection signal φ _CL = “H”, the column selection gate 14 is turned on and the pMOS transistors 53 to 55 are turned off. Is done.

As a result, the nMOS transistors 26 to 2
9 is in a floating state, and during this floating state, the column selection gate 1
3 is in the ON state, for example, a period of about 5 nsec., So that the operation does not become unstable.

Here, for example, when the bit line / BL is amplified to the 0 [V] side by the sense amplifier 4, the data bus / DB is pulled toward the 0 [V] side. The amplitude of this change is suppressed within 100 mV by the pull-up effect of the pMOS transistor 51. In addition,
In this case, node 56 maintains the state of voltage Vpr.

Since the nMOS transistors 26 to 29 of the sense buffer 22 are biased to the voltage Vpr, the potential of the node 57 is set based on the bias voltage Vpr.
It falls reflecting the potential change of B.

Here, since the sense buffer 22 performs a differential amplification operation, the node 58 of the sense buffer 22 is connected to Vcc
, The node 59 falls to the 0 [V] side, and this
The data is latched by the S flip-flop 34.

In the first embodiment, the data buses DB and / DB are reset to the power supply voltage Vcc via the pMOS transistors 50 and 51, and the voltage difference between the sense amplifier 4 and the data buses DB and / DB is calculated as follows. Vcc-Vcc / 2
(= Precharge voltage of bit lines BL, / BL) = Vcc
/ 2 can be obtained.

By the way, if Vcc = 2.0 [V],
As a voltage difference between the sense amplifier 4 and the data buses DB and / DB, a large value of 1.0 [V] can be obtained. On the other hand, in the conventional DRAM shown in FIG. 6, the voltage difference between the sense amplifier 4 and the data buses DB and / DB is Vcc-Vth-n-Vcc / 2 = Vcc / 2-Vth-n
= 0.3 [V].

As described above, according to the first embodiment, at the time of reading, the voltage difference between the sense amplifier 4 and the data buses DB and / DB can be increased. , / DB can be driven strongly, and the access time can be shortened.

Further, according to the first embodiment, the gate voltages of the nMOS transistors 26 to 29 of the sense buffer 22 can be biased to Vpr which is lower than the power supply voltage Vcc. For example, Vcc = 2.0 [V], Vp
r can be set to 1.0 [V].

As a result, the nMOS of the sense buffer 22
The drain voltage of the transistors 26 to 29 is equal to the power supply voltage Vcc.
In the case where nMOS transistors 26 to 26
29 can be operated in the pentapole region with a high gm.

Therefore, even if data buses DB and / DB are reset to power supply voltage Vcc, sense buffer 2
It is not necessary to increase the number of amplification stages of 2, and from this point,
Access can be speeded up.

According to the first embodiment, at the time of reading, the data buses DB and / DB are connected to the Vcc power supply line 19 through the pMOS transistors 50 and 51 in the on state.

As a result, the power supply voltage Vcc
Instantaneously drops, the voltages of the data buses DB and / DB also drop, and the gate voltages of the nMOS transistors 26 to 29 of the sense buffer 22 also drop, so that the access time is not affected by power supply noise. Can be.

As described above, according to the first embodiment,
Even if the power supply voltage is lowered, the access speed can be increased, and the access time can be prevented from being affected by power supply noise.

FIG. 4 is a circuit diagram showing a main part of a second embodiment of the present invention. In the second embodiment, the Vpr voltage line 52 and nM
A resistor 6 having a resistance value of 20 KΩ is connected between the gates of the OS transistors 26 and 28 and between the Vpr voltage line 52 and the gates of the nMOS transistors 27 and 29, respectively.
0 and 61 are connected.

The resistors 60 and 61 may be constituted by pure resistors using a material such as polysilicon, or may be constituted by utilizing the channel resistance of a MOS transistor.

The resistance values of these resistors 60 and 61 are as follows:
It is determined by the relationship between the values of the capacitors 48 and 49 and the ON period of the column selection gate, and the capacitors 48 and 49 are determined by the input capacitance of the sense buffer 22.

Here, for example, the nMOS transistor 2
The gate length of 6 to 29 is 0.5 μm and the gate width is 10 μm.
m and the thickness of the gate oxide film is 10 nm, the nMOS
The input capacitances of the transistors 22 to 29 are each set to 0.
017 pF.

Here, the nMOS transistors 26 and 28
, And 27 and 29 are in a parallel relationship, so that the input capacitance of the sense buffer 22 is 0.034 pF.
If the capacitors 48 and 49 are sufficiently large with respect to the capacitors, almost all signals on the data buses DB and / DB appear at the input of the sense buffer 22.

For example, the capacitances 48 and 49 are equal to one of the input capacitances.
With a capacitance of 0 times, that is, 0.34 pF, the calculation is such that a 10/11 voltage of the signal on the data buses DB and / DB appears at the input of the sense buffer 22.
In the nMOS transistors forming the transistors 8 and 49, the gate length should be 10 μm, the gate width should be 10 μm, and the thickness of the gate oxide film should be 10 nm.

Here, the values of the resistors 60 and 61 are 0.34
It is sufficient that the time constant of the pF capacitors 48 and 49 is sufficiently large with respect to the passing signal. If the time constant is set to 20 KΩ as described above, the time constant is 6.8 ns.

The column selection signal supplied to the column selection gate has a pulse width of about 5 ns, and 6.8 n between the capacitor 48 and the resistor 60 and between the capacitor 49 and the resistor 61.
If there is a time constant of seconds, the alternating pulse signals on the data buses DB and / DB can be input to the sense buffer 22 through the capacitors 48 and 49.

In the second embodiment, the data bus D
Since B and / DB are configured to be reset to the power supply voltage Vcc, the voltage difference between the sense amplifier 4 and the data buses DB and / DB can be increased at the time of reading, and access can be speeded up. be able to.

Further, since the gate voltages of the nMOS transistors 26 to 29 of the sense buffer 22 can be biased to a voltage Vpr lower than the power supply voltage Vcc, the drain voltages of the nMOS transistors 26 to 29 of the sense buffer 22 are changed to the power supply voltage Vcc. NM
The OS transistors 26 to 29 can be operated in the pentapole region with a high gm.

Therefore, even if data buses DB and / DB are reset to power supply voltage Vcc, sense buffer 2
It is not necessary to increase the number of amplification stages of 2, and from this point,
Access can be speeded up.

At the time of reading, data buses DB, / DB
Is connected to the Vcc power supply line 19 via the pMOS transistors 50 and 51 in the ON state, so if the power supply voltage Vcc drops momentarily due to power supply noise, the voltages of the data buses DB and / DB also drop, N of the sense buffer 22
The gate voltages of the MOS transistors 26 to 29 can also be reduced, so that the access time is not affected by the power supply noise.

As described above, in the second embodiment, as in the first embodiment, even if the power supply voltage is lowered, the access can be speeded up and the access time can be reduced by the power supply noise. Can be unaffected.

(3) Third Embodiment FIG. 5 FIG. 5 is a circuit diagram showing a main part of a third embodiment of the present invention.
In the third embodiment, a sense amplifier 62 composed of a so-called direct sensing circuit is provided.
The configuration is the same as that of the first embodiment. 63,
64 is an nMOS transistor.

The sense amplifier 62 is characterized in that the data buses DB and / DB are driven by the nMOSs 63 and 64 whose gates are connected to the bit lines BL and / BL. / BL is
Instead of being directly connected to the data buses DB and / DB, they are connected through the gates of the nMOS transistors 63 and 64, so that the inside of the cell array is not affected by the voltage conditions on the data buses DB and / DB. This has the advantage that troubles such as cell destruction can be eliminated during reading.

Here, the nMOS transistors 63 and 64
Since the gate voltage is biased to Vcc / 2 by precharging the bit lines BL and / BL, if the drain voltage is close to Vcc / 2, the nMOS transistor is biased in the triode region and has a sufficient gain. Can not be obtained.

Therefore, the nMOS transistors 63 and 6
4 is high, that is, the reset voltage of the data buses DB and / DB is desirably high. In this regard, in the first embodiment, the data buses DB and / DB are reset to the power supply voltage Vcc. Transistor 63,
64 in the pentode region with a high gm and the data bus D
B and / DB can be driven strongly, and access can be speeded up.

Further, since the gate voltages of the nMOS transistors 26 to 29 of the sense buffer 22 can be biased to a voltage Vpr lower than the power supply voltage Vcc, the drain voltages of the nMOS transistors 26 to 29 of the sense buffer 22 become lower than the power supply voltage Vcc. NM
The OS transistors 26 to 29 can be operated in the pentapole region with a high gm.

Therefore, even if data buses DB and / DB are reset to power supply voltage Vcc, sense buffer 2
It is not necessary to increase the number of amplification stages of 2, and from this point,
Access can be speeded up.

At the time of reading, data buses DB and / DB
Is connected to the Vcc power supply line 19 via the pMOS transistors 50 and 51 in the ON state, so if the power supply voltage Vcc drops momentarily due to power supply noise, the voltages of the data buses DB and / DB also drop, N of the sense buffer 22
The gate voltages of the MOS transistors 26 to 29 can also be reduced, so that the access time is not affected by the power supply noise.

As described above, in the third embodiment, as in the first embodiment, even if the power supply voltage is lowered, the access can be speeded up and the access time can be reduced by the power supply noise. Can be unaffected.

(4) Others In the above-described embodiment, as the capacitive element interposed between the data bus DB and the sense buffer 22, the capacitor 48 composed of an enhancement type nMOS transistor is used.
Although the case where 49 is provided has been described, in particular,
When the voltage difference between the reset voltages of the data buses DB and / DB and the reset voltage on the input side of the sense buffer 22 is small, a depletion type is used instead of the capacitances 48 and 49 composed of enhancement type nMOS transistors. It is preferable to provide a capacitor composed of an nMOS transistor.

The reason is that the enhancement type nMO
The capacity of the S transistor is such that the voltage difference between the electrodes is nM
This is because when the threshold voltage is equal to or lower than the threshold voltage of the OS transistor, the resistance of the electrode suddenly increases, and the series parasitic resistance of the capacitor increases.

In place of the capacitances 48 and 49 formed of enhancement type nMOS transistors, a DRAM
When the structure of the storage capacitor used in the memory cell is used, the capacity per unit area can be increased, so that the capacity can be reduced and the depletion type n
As in the case of the capacitance by the MOS transistor, even if the voltage difference between the electrodes is small, there is no problem that the electrode resistance increases, so that it is most convenient.

In the above embodiment, the case where the present invention is applied to a DRAM has been described. In addition, the present invention relates to an SRA having a data bus similarly to a DRAM.
The present invention can be applied to all semiconductor memory devices having a sense buffer for amplifying a signal of a data bus, such as M and ROM.

[0086]

According to the present invention, the data bus is reset to the power supply voltage, and the voltage difference between the sense bus and the sense amplifier in the read operation is increased, and the data bus can be driven strongly. Can be achieved.

Also, according to the present invention, the gate voltage of the input transistor of the sense buffer can be biased to a voltage lower than the power supply voltage. Therefore, when the drain voltage of the input transistor of the sense buffer becomes the power supply voltage, Also, since the input transistor can be operated in the pentapole region having a high gm,
Access can be speeded up.

According to the present invention, the data bus is connected to the power supply line for supplying the power supply voltage via the resistance element at the time of reading. Therefore, when the power supply voltage drops momentarily due to power supply noise, the data bus is connected to the data bus. Since the voltage of the bus also drops and the gate voltage of the input transistor of the sense buffer can also drop, it is possible to prevent the access time from being affected by power supply noise.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a main part of the first embodiment of the present invention.

FIG. 3 is a waveform chart for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a main part of an example of a conventional DRAM.

[Explanation of symbols]

 40 Input transistor of sense buffer Vcc Power supply voltage Vpr Voltage lower than power supply voltage

Claims (6)

(57) [Claims] A plurality of columns (37 ₁ , 37 ₂ ... 3)
7 _n ) and a read amplifier circuit (3) provided at the end of the data bus (38).
9) between the input transistor (40) and the capacitive element (4).
1), the power supply voltage (Vcc) is supplied to the data bus (38) at the time of reading between the power supply line (42) for supplying the power supply voltage (Vcc) and the data bus (38). In addition to providing a resistance element (43), a bias circuit (44) for biasing the gate voltage of the input transistor (40) of the amplifier circuit (39) to a voltage (Vpr) lower than the power supply voltage (Vcc) is provided. A semiconductor memory device characterized in that: 2. The bias circuit (44) includes a voltage line (47) for supplying a voltage (Vpr) lower than the power supply voltage (Vcc) and an input transistor (40) of the amplifier circuit (39). In the meantime, the columns (37 ₁ , 37 _2.
..37 _n column selection gates (46 ₁ , 46 ₂ ...)
46 _n ), wherein a switch element is provided which is controlled to be in an off state during a period in which one of _n is in an on state and to be in an on state in other periods. Semiconductor storage device. 3. The amplifier circuit according to claim 2, wherein the bias circuit is connected between a voltage line supplying a voltage lower than the power supply voltage and an input transistor of the amplifier circuit. In addition, any one of the column selection gates (46 ₁ , 46 ₂ ... 46 _n ) of the plurality of columns (37 ₁ , 37 ₂ ... 37 _n ) whose time constant with the capacitance element (41) is turned on. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured by connecting a resistor having a resistance value larger than a period in which the state is set. 4. The semiconductor memory device according to claim 1, wherein said capacitance element is formed of a depletion type nMOS transistor. 5. The semiconductor memory device according to claim 1, wherein said capacitance element is constituted by a storage capacitance. 6. The semiconductor according to claim 1, wherein the power supply voltage (Vcc) is a voltage obtained by stepping down a voltage supplied from outside the chip inside the chip. Storage device.