JP2002093171A - Semiconductor memory and read-out method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly eliminate unexpected voltage variation (noise) of a bit line being made a floating state at the time of read-out. SOLUTION: This device has a capacitor C, a memory cell MC including a read-out transistor Q2 of which the gate is connected to a storage node SN, the drain is connected to a voltage supply line (read-out word line RWL), the source is connected to a bit line BL, and which is turned on or turned off in accordance with storage node voltage after boosting when the voltage of the storage node SN is boosted by fixed voltage through the capacitor C, a drive transistor Qd connected between the bit line BL and a supply line of reference voltage, and a control circuit CC making the drive transistor Qd a conduction state for a fixed period including a period in which the bit line BL is a floating state and storage node voltage is being boosted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a two-transistor-one-capacitor type memory cell, which is a kind of a so-called gain cell, and amplifies a storage data held in the cell by a read transistor and reads it out to a bit line. The present invention relates to a semiconductor memory device and a reading method thereof.

[0002]

2. Description of the Related Art A so-called two-transistor-one-capacitor type gain cell is common to a case where two bit lines are provided for writing and reading, and a case where two word lines are provided for writing and reading. 4 common cases
There are different types of cell configurations.

FIGS. 1 and 2 are circuit diagrams showing two examples of a gain cell configuration when a common bit line is used. These gain cells (memory cells MC) include a write transistor Q1, a read transistor Q2, and a capacitor (CAP).
Or C). The write transistor Q1 has its gate connected to the write word line WWL, and is connected between the storage node SN and the bit line BL. The read transistor Q2 has a gate connected to the storage node SN and a source connected to the bit line BL.

In FIG. 1, the drain of the read transistor Q2 is connected to a read word line RWL, and in FIG. 2, the drain of the read transistor Q2 is connected to a supply line of a power supply voltage V _CC . These read transistors Q
2 need only be biased at the time of reading. Therefore, in FIG. 1, one line is reduced by using the supply line of the power supply voltage V _cc for applying the drain bias of the read transistor Q2 and the read word line RWL together.

A capacitor (CAP or C) is provided for capacitively coupling the read word line RWL to the storage node SN. In FIG. 2, for example, MIM (Metal
Although a capacitive element CAP having a (-Insulator-Metal) structure is provided, in FIG. 1, the capacitor C can be configured using a parasitic capacitance Cp between the gate and the drain of the read transistor Q2. Therefore, the actual number of elements of the memory cell of FIG. 1 can be smaller than that of FIG.

In writing, one of binary voltages corresponding to "1" and "0" of write data is set to the bit line BL, and the write word line WWL is driven to turn on the write transistor Q1. Thereby, the bit line voltage is transmitted to storage node SN. After that, when the write transistor Q1 is turned off, the storage node SN enters an electrically floating state, so that storage data is held in the storage node SN. The threshold voltage is set so that the read transistor Q2 does not turn on in this storage state. For example, the voltage corresponding to the storage data “1” is 0.75 V, and the voltage corresponding to the storage data “0” is 0.
In the case of V, the threshold voltage VthQ2 of the read transistor Q2 is set to about 0.9 V so that the read transistor Q2 is not turned on even by the voltage 0.75V of the storage data "1".

Next, a read operation will be described. Here, the cell configuration of FIG. 1 is used as an example, and a sense amplifier SA provided for each bit line BL as shown in FIG. 3 is used. Changes in voltage of each signal line at the time of reading are shown in timing charts of FIGS. First, the bit line is set to a floating state at 0 V (FIG. 4C), and then the voltage of the read word line RWL is raised to a high level (1.5 V) (FIG. 4B). Thereby, the voltage of the storage node SN increases due to the capacitive coupling via the capacitor C. In boosting the storage node SN, the boosted voltage of the storage data “1” is higher than the threshold voltage VthQ2 of the read transistor Q2, and the boosted voltage of the storage data “0” is lower than the threshold voltage VthQ2. Thus, the capacitance value of the capacitor and the like are determined in advance. Therefore, when the stored data is "1", the read transistor Q2 is turned on, and as shown in FIG. 4C, the bit line BL changes the threshold voltage VthQ2 from the boosted voltage of the stored data "1".
Rises to the voltage VBLh obtained by subtracting On the other hand, when the storage data is “0”, the read transistor Q2 does not turn on, so that the bit line voltage is maintained at 0V. By amplifying this bit line voltage difference to an amplitude of 1.5 V by the sense amplifier SA, binary storage data is detected and read.

[0008]

However, in the read operation of the conventional semiconductor memory device, as shown in FIG. 4C, the bit line BL is discharged from 0 V to activate the sense amplifier SA. Because of the floating state, there is a problem that noise is easily received during this period, and unexpected voltage fluctuation appears on the bit line.

The noise is caused by the bit line BL
There is induced noise from a nearby wiring to which a high voltage is applied during the floating state. FIG.
L indicates a capacitive coupling with a wiring serving as a noise source. FIG.
, The central bit line BL2 is a bit line from which stored data is to be read, and other bit lines BL1 and BL3 formed of wirings of the same hierarchy are arranged on both sides thereof in parallel with the bit line BL2. . Since the bit lines are separated by a dielectric such as an interlayer insulating film, the bit lines B
A coupling capacitance C1 exists between L1 and BL2 and between the bit lines BL2 and BL3. Further, the read word line RWL is connected to the bit line B via a dielectric such as an interlayer insulating film.
L2, and a coupling capacitance C2 also exists between the read word line RWL and the bit line BL2.

When the read word line RWL is raised to 1.5 V as shown in FIG. 4B while the bit line BL shown in FIG. 4C is in the floating state at 0 V, the coupling shown in FIG. Positive induction noise may be superimposed on the bit line BL via the capacitor C2.

After that, after the voltage of the bit line BL changes according to the stored data, the sense amplifiers SA connected to the bit lines BL1, BL2, BL3 in FIG. Be activated.
Now, it is assumed that “0” storage data is read to the central bit line BL, and the voltage of the bit line BL2 has not changed. Also, "1" is applied to both adjacent bit lines BL1 and BL3.
The stored data is read, and the bit lines BL1 and BL3 are set to 0. It is assumed that the voltage is increased by about several volts. In this state, it is assumed that the sense amplifiers SA connected to the bit lines BL1 to BL3 are simultaneously activated. Sense amplifier SA
Although it depends on the configuration, there is usually a slight difference between the timing of raising the bit line voltage to the power supply voltage of 1.5 V and the timing of fixing the bit line voltage to the ground voltage of 0 V. Therefore, before the center bit line BL2 is fixed to the ground voltage, the other bit lines BL1. BL3
Is raised to the power supply voltage of 1.5 V, the voltage of the bit line BL2 still in the floating state increases due to the induction noise via the coupling capacitor C1 in FIG. 5, and the voltage relationship may be reversed. In this case, since the sense amplifier SA connected to the bit line BL2 may raise the voltage increased by the induction noise to the power supply voltage 1.5V, the bit line BL2 which should be "0" storage data
Erroneously determines that the voltage of “1” is stored data “1”.

As described above, in the conventional semiconductor memory device,
Bit line BL2 that is in a floating state at the time of reading
However, there has been a problem that the voltage fluctuates due to induced noise due to neighboring wirings coupled to this via the capacitors C1 and C2, and a malfunction may occur in some cases.

An object of the present invention is to provide an unexpected voltage fluctuation (noise) of a bit line which becomes a floating state at the time of reading.
To provide a semiconductor memory device with high operation reliability and a reading method therefor.

[0014]

In a semiconductor memory device according to a first aspect of the present invention, a capacitor and a gate are connected to a storage node, a drain is connected to a voltage supply line, and a source is connected to a bit line. A memory cell including a read transistor that is turned on or off in accordance with the boosted storage node voltage when the voltage of the storage node is boosted by a constant voltage through the capacitor, the bit line and a reference voltage supply line, And a control circuit that makes the drive transistor conductive for a certain period of time including when the storage node voltage is boosted while the bit line is in a floating state. The control circuit may further include an amplifier circuit connected to the bit line and amplifying the voltage of the bit line. Preferably, the certain period in which the control circuit turns on the drive transistor includes a time when the amplifier circuit is driven. .

In this semiconductor memory device, the control line for controlling the boosting and the bit line intersect with a dielectric interposed therebetween. A plurality of the memory cells are arranged in a matrix to form a memory cell array. The memory cell array includes a plurality of the bit lines commonly connected among a plurality of memory cells in a column direction in the memory cell array. Are arranged in parallel with a dielectric interposed therebetween, and the drive transistor whose gate is connected to the control circuit is connected to each of the plurality of bit lines.

Preferably, the minimum value of the current flowing through the drive transistor in a conductive state is such that the voltage of the storage node in one of the plurality of memory cells in the column direction is selected and the other non-selected memory cells are The minimum driving capability of the driving transistor is predetermined so that the total value of the off-leak current flowing through the read transistor in the plurality of unselected memory cells when all are at the high level is sufficiently large. Preferably, the maximum value of the current flowing through the driving transistor in a conductive state discharges the electric charge when a predetermined positive noise is applied to the bit line having a predetermined load capacitance for a predetermined maximum allowable time. The maximum drive capability of the drive transistor is determined in advance so as to be equal to or less than the current value. Alternatively, preferably, the maximum value of the current flowing through the driving transistor in a conductive state is determined when discharging the electric charge in a predetermined time when a predetermined positive noise is applied to the bit line having a predetermined load capacitance. The maximum driving capability of the driving transistor is determined in advance so that the power consumption is equal to or less than a predetermined value.

In the memory cell configuration of the semiconductor memory device according to the present invention, a capacitor is connected between a gate and a drain of a read transistor, and a voltage supply line connected to the drain is a read word line for controlling boosting of a storage node. There is a certain first cell configuration and a second cell configuration in which a capacitor is connected between a storage node and a read word line, and a drain of a read transistor is connected to, for example, a power supply voltage supply line. In each of the above-described first and second cell configurations, there are two cases, that is, a case where two bit lines are provided for writing and reading, and a case where one bit line is provided.

According to a second aspect of the present invention, there is provided a method for reading a semiconductor memory device, comprising: a capacitor; a gate connected to a storage node; a drain connected to a voltage supply line; a source connected to a bit line; A memory cell including a read transistor that is turned on or off in accordance with the boosted storage node voltage when the voltage of the storage node is boosted by a constant voltage, and between the bit line and a reference voltage supply line. A method of operating a semiconductor memory device having a driving transistor connected thereto, wherein the bit line is discharged to a floating state, the storage node voltage is boosted, and the storage node voltage is boosted according to the boosted storage node voltage. At the time of reading in which the read transistor is turned on or off to change the voltage of the bit line, Certain period including the time, to the driving transistor in a conducting state. Preferably, the step of amplifying the voltage change of the bit line includes a step of amplifying the bit line, wherein the certain period of time in which the driving transistor is turned on includes a time of starting the amplification of the bit line.

In the semiconductor memory device having such a configuration and its reading method, since the drive transistor is conductive during the floating state of the bit line at 0 V, noise superimposed on the bit line due to capacitive coupling with a neighboring wiring is provided. Is generated, the electric charge caused by the occurrence is quickly discharged to a reference voltage supply line, for example, a ground line. When a voltage corresponding to "1" storage data appears on the bit line,
The charge discharge by the drive transistor and the charge supply from the voltage supply line through the readout transistor are balanced, so that noise is not easily superimposed on the bit line. Returns. For example, when a positive voltage is applied to a neighboring wiring that generates noise on the bit line and the positive noise is superimposed on the bit line, the voltage fluctuation of the bit line in a floating state at a low level (0 V) is stored in the stored data. The corresponding voltage relationship is reversed, leading to malfunction. According to the present invention, unexpected voltage fluctuation (noise) of a bit line floating at a low level (0 V) is effectively removed.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings, taking as an example the case where all transistors in a memory cell are of the n-channel type.

The semiconductor memory device according to this embodiment has the memory cell having the configuration shown in FIG. 1 or 2 described above. In this embodiment, any of the memory cells shown in FIGS. 6 and 7 may be used. The memory cell shown in FIG. 6 is different from the memory cell of FIG. 1 in that it has two bit lines, a write bit line (write bit line WBL) and a read bit line (read bit line RBL). On the point. That is, the drain of the write transistor Q1 is connected to the write bit line WBL, and the source of the read transistor Q2 is connected to the read bit line RBL. Other configurations and connection relationships are the same as those in FIG. 1, and description thereof will be omitted. Similarly, the memory cell shown in FIG. 7 differs from the memory cell of FIG. 2 in that it has two bit lines, a write bit line WBL and a read bit line RBL. That is, the write bit line W
BL is connected to the drain of the write transistor Q1, and the read transistor Q is connected to the read bit line RBL.
2 sources are connected. Other configurations and connection relationships are the same as those in FIG. 2, and a description thereof will be omitted.

In the memory cell array, memory cells MC having such a configuration are arranged in a matrix, and a plurality of memory cells MC in a row direction are commonly connected by word lines WWL and RWL, and a plurality of memory cells MC in a column direction are arranged. Are commonly connected by a bit line BL (or WBL, RBL).

FIG. 8A shows a memory cell MC selected in the memory cell array and necessary parts of peripheral circuits.
As shown in FIG. 8A, a sense amplifier SA is connected to each bit line BL in the memory cell array. The sense amplifier SA is controlled by a sense amplifier drive line (not shown). Further, a drive transistor Qd is connected to each bit line BL. The drain of the drive transistor is connected to the bit line BL, and the source is connected to a supply line for a reference voltage, for example, a ground voltage. The gate is connected to the common drive line DL between the plurality of drive transistors Qd in the row direction. The control circuit CC is connected to the drive line DL. The control circuit CC sets the drive signal D applied to the drive line DL to a high level to turn on the drive transistor Qd for a certain period during a read cycle, and thereafter returns the drive signal D to a low level to turn off the drive transistor Qd. Let it.

In the read operation, the bit line BL is floated at 0 V as shown in FIG. 9C, and then the voltage of the read word line RWL is raised to a high level (1.5 V) as shown in FIG. ). At this time,
Due to the capacitive coupling via the capacitor C, the storage node S
The voltage of N increases. In boosting the storage node SN, as described above, the threshold voltage VthQ2 of the read transistor Q2 and the capacitance value of the capacitor C are determined in advance so that the boosted voltage of the storage node SN falls within an appropriate range. Therefore, as shown in FIG. 9C, when the storage data is “1”, the read transistor Q2 is turned on and the bit line BL is set to 0. When the voltage rises by several volts and the storage data is "0", the voltage of the bit line BL does not fluctuate while the read transistor Q2 remains off. When the change in the voltage of the bit line BL is stabilized, the sense amplifier S
By activating A and amplifying the bit line voltage to an amplitude of 1.5 V, binary storage data is detected and read.

The basics of the above read operation are the same as those of the prior art, but in this embodiment, FIGS. 9B and 9D
As shown in (5), in synchronization with the driving of the read word line RWL, the control circuit CC raises the drive line DL to 1.5 V and turns on the drive transistor Qd. Here, the relationship between the read transistor Q2 and the drive transistor Qd of the memory cell MC selected at the time of reading is shown in FIG.
As shown in (B), the read transistor Q2 is a load transistor, and the read word line RWL of the selected cell is used.
Is regarded as an inverter that uses the voltage of 1.5 V applied as a power supply voltage and outputs the bit line BL. A voltage corresponding to the data stored in the selected cell is applied to the gate of the load transistor.

FIG. 10 shows the relationship between the output voltage (bit line voltage VBL) of the inverter and the current I flowing through the inverter.
It is shown in (A). IV curve Sd of drive transistor Qd
At the intersection (indicated by a white circle) with the load curve Sq2 of the load transistor Q2, the bit line voltage VBL is fixed at a constant value. When reading “0” data from binary storage data, as shown in FIG. 10A, when positive noise enters the bit line BL stabilized at 0 V, the voltage VBL of the bit line BL becomes For example, 0. It rises by several V. Then, this noise voltage is applied to the driving transistor Q
Since it is applied to the drain of d, Qd conducts and acts to discharge the bit line voltage VBL. Therefore, the bit line voltage VBL returns to the original 0 V, and the noise voltage is quickly removed. On the other hand, when "1" data is read, the read transistor Q2 and the drive transistor Qd of the selected cell are both conductive, and the bit line BL is stable at, for example, about 0.7V. In this case, the noise is less likely to be superimposed than when the “0” data is read. However, even if a slight positive noise enters, the current flowing through the driving transistor Qd instantaneously flows because the driving transistor Qd is already in the conductive state. And noise is removed very quickly.

Incidentally, the semiconductor memory device according to the present embodiment can store not only binary data but also multi-valued data of three or more values. The four-valued storage data “00”, “01”, “1”
Consider the case of reading “0” and “11.” In this case, for example, as shown in FIG.
When reading the stored data of "1", "10", and "11", the bit line voltage VBL is set to 0.05 V and 0.3 V, respectively.
Stabilized at V, 0.55V, 0.8V. In either case, the read transistor Q2 and the drive transistor Qd of the selected cell are the same as in the case of “1” read of binary storage.
Are conducted together, it is difficult for noise to be superimposed, and even if a small amount of positive noise enters the scale, it is very quickly removed as described above.

Next, the range of the current value Id actually flowing through the driving transistor Qd, which is necessary for determining the driving capability of the driving transistor Qd, is estimated. The minimum value of the current value Id can be determined based on the relationship between the selected cell and the total leakage current of the non-selected cells in the same column. FIG. 11 (A)
M memory cells connected to one bit line BL,
The bias conditions at the time of reading the word lines WWL and RWL are shown. At the time of reading, all the write word lines WWL are held at 0 V, and only the read word line RWL of the memory cell MC1 to be selected is at a high level, for example, 1.5 V
Start up. Therefore, (m-1) memory cells MC2, MC3,..., MCm other than the selected cell MC1
Becomes unselected.

At the time of reading, the relationship between the read transistor Q2 of the selected cell MC1 and the read transistor Q2 of the non-selected cells MC2 to MCm is, as shown in FIG. 11B, the read transistor Q2 of the selected cell MC1.
Is the load transistor, the read transistor Q2 of the non-selected cells MC2 to MCm is the drive transistor (driver), the voltage of 1.5 V applied to the read word line RWL of the selected cell MC1 is the power supply voltage, and the bit line B
It is regarded as an inverter that outputs L. A voltage corresponding to the storage data of the selected cell is applied to the gate of the load transistor, and a voltage corresponding to the storage data of the non-selected cell is applied to each gate of the driver.

The read transistor Q2 of a non-selected cell serving as a driver is non-conductive, but since a gate voltage at the time of storing "1" is, for example, 0.75 V, a small subthreshold current flows through this driver. .
The integrated value of the subthreshold current becomes maximum when all the non-selected cells MC2 to MCm store “1”. In FIG. 8A, the minimum value of the current of the drive transistor Qd connected to the bit line BL must be several times or more of this maximum sub-threshold current and must be sufficiently large. This is to prevent the operating point (open circle) of the inverter characteristics shown in FIGS. 10A and 10B from fluctuating depending on the magnitude of the subthreshold current of the non-selected cell.

On the other hand, the maximum value of the current Id of the drive transistor Qd can be estimated from a request to discharge the load capacitance of the bit line BL containing noise in a proper time, for example, a time of about 10 ns at the maximum. The maximum value of the appropriate time is determined by, for example, the time from the rise of the read word line RWL to the activation of the sense amplifier SA in the read cycle in the operation timing design of the whole semiconductor memory device, or the sense amplifier SA. The time from when the high-level voltage of the bit line BL is raised to the power supply voltage V _{CC to} when the low-level voltage of the bit line BL is fixed at 0 V is the maximum allowable time. If this proper time is too long, the entire read cycle time will be long, so this time is limited to, for example, about 10 ns at the maximum. For example, 200fF
A voltage amplitude of 0.1 is applied to the bit line BL having a load capacitance C of
In the case where the noise of V is discharged and the noise is discharged at the time t of 10 ns, the maximum value Idmax of the current of the driving transistor Qd = 2 μA is obtained by the calculation according to the following equation.

Idmax = C × V / t = (200 fF × 0.1 V) / 10 ns = 2 μA (1)

The maximum value of the current Id of the driving transistor Qd can be determined by a limit based on the maximum power consumption at the time of reading. This is because recent semiconductor memories are strictly required to have a power consumption design in consideration of application to portable devices.

Within the above range of the current Id, parameter values for determining the driving capability such as the transistor size or the mutual conductance gm of the driving transistor Qd are designed.

The semiconductor memory according to the present embodiment has, for each bit line BL, a drive transistor Qd connected between the bit line BL and the reference voltage line and controlled on a row basis by the control circuit CC. Therefore, at the time of reading, in particular, the selected bit line BL which is in a floating state at 0 V is connected to the selected bit line BL.
Even if induced noise due to the capacitively coupled neighboring wiring enters, this noise is promptly removed. Therefore, a malfunction during reading hardly occurs, and the operation reliability is improved.

In this embodiment, various modifications are possible. For example, all the transistors in the memory cell can be p-channel type, or only one of the write transistor Q1 and the read transistor Q2 can be p-channel type. In that case, the logic of the control signal for each word line or the like is appropriately inverted and used. Further, when negative induction noise superimposed on the bit line becomes a problem, it is possible to change the drive transistor between the bit line and the supply line of the power supply voltage V _CC .

[0036]

According to the semiconductor memory device and the reading method of the present invention, unexpected voltage fluctuation (noise) of a bit line which becomes a floating state at the time of reading is promptly removed, whereby a semiconductor having high operation reliability is obtained. It has become possible to provide a storage device and a reading method thereof.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first memory cell configuration having one bit line in a semiconductor memory device according to an embodiment.

FIG. 2 is a circuit diagram showing a second memory cell configuration having one bit line in the semiconductor memory device according to the embodiment;

FIG. 3 is a diagram showing a memory cell to be read and a sense amplifier, which are used for describing a problem of the related art.

FIGS. 4A to 4C are timing charts showing a voltage change of each signal line at the time of reading in a conventional semiconductor memory device.

FIG. 5 is a circuit diagram showing a capacitive coupling between a bit line of a memory cell to be read and a wiring serving as a noise source, which is used for describing a problem of the related art.

FIG. 6 is a circuit diagram showing a third memory cell configuration having two bit lines in the semiconductor memory device according to the embodiment;

FIG. 7 is a circuit diagram showing a fourth memory cell configuration having two bit lines in the semiconductor memory device according to the embodiment.

FIG. 8A is a diagram showing a memory cell selected in a memory cell array according to the embodiment and a necessary portion of a peripheral circuit. (B) is an equivalent circuit diagram showing a relationship between a read transistor and a drive transistor of a memory cell selected at the time of read.

FIGS. 9A to 9D are timing charts showing a voltage change of each signal line at the time of reading in the semiconductor memory device according to the embodiment;

FIG. 10 shows a memory cell array according to the embodiment.
9 is a graph illustrating a relationship between an output voltage of the inverter illustrated in FIG. 8B and a current flowing through the inverter. (A) is 2
In the case of value storage, (B) is a case of four-value storage.

FIG. 11A is a circuit diagram illustrating a memory cell selected in the memory cell array according to the embodiment and a non-selected memory cell in the same column. FIG. 3B is an equivalent circuit diagram showing a relationship between a read transistor of a memory cell selected at the time of reading and a read transistor of a non-selected memory cell.

[Explanation of symbols]

MC: memory cell, MC1: selected memory cell, MC2
MCm: unselected memory cell, Q1: write transistor, Q2: read transistor, SN: storage node,
C, CAP: capacitor, Qd: drive transistor, C
C: control circuit, SA: sense amplifier, BL: bit line,
WBL: write bit line, RBL: read bit line, WWL: write word line, RWL: read word line, DL: drive line, D: drive signal, V _CC : power supply voltage,
I: current flowing through the inverter, VBL: bit line voltage, S
d: IV curve of the driving transistor, Sq2: load curve of the reading transistor.

Claims (13)

[Claims] A capacitor and a gate are connected to a storage node, a drain is connected to a voltage supply line, a source is connected to a bit line, and a voltage of the storage node is boosted by a constant voltage through the capacitor. A memory cell including a read transistor that is turned on or off in accordance with the boosted storage node voltage; a drive transistor connected between the bit line and a reference voltage supply line; A control circuit for turning on the drive transistor for a certain period including the time when the storage node voltage is boosted. 2. The semiconductor device according to claim 1, further comprising an amplifier circuit connected to said bit line for amplifying a voltage of said bit line, wherein said predetermined period in which said control circuit keeps said drive transistor conductive is a period during which said amplifier circuit is driven. Claim 1 containing
13. The semiconductor memory device according to claim 1. 3. The semiconductor memory device according to claim 1, wherein the control line for controlling the boosting and the bit line intersect with a dielectric interposed therebetween. 4. A plurality of memory cells are arranged in a matrix to form a memory cell array. The memory cell array includes a plurality of bit lines commonly connected among a plurality of memory cells in a column direction in the memory cell array. 2. The semiconductor memory device according to claim 1, wherein said plurality of bit lines are arranged in parallel with a dielectric interposed therebetween, and said drive transistor whose gate is connected to said control circuit is connected to each of said plurality of bit lines. 5. The minimum value of the current flowing through the conductive drive transistor is such that one of the plurality of memory cells in the column direction is selected and the voltages of the storage nodes in the other unselected memory cells are all equal. 5. The semiconductor according to claim 4, wherein the minimum driving capability of the driving transistor is predetermined so that the total driving current of the driving transistor is sufficiently larger than a total value of an off-leak current flowing through the read transistor in the plurality of unselected memory cells at a high level. Storage device. 6. A maximum value of a current flowing through the driving transistor in a conductive state discharges a charge when a predetermined positive noise is applied to the bit line having a predetermined load capacitance within a predetermined maximum allowable time. 5. The semiconductor memory device according to claim 4, wherein a maximum drive capability of said drive transistor is determined in advance so as to be equal to or less than a current value. 7. A maximum value of a current flowing through the driving transistor in a conductive state, the maximum value of the current when a predetermined positive noise is applied to the bit line having a predetermined load capacitance when the electric charge is discharged for a predetermined period of time. In order for the power consumption to be equal to or less than the predetermined value,
5. The semiconductor memory device according to claim 4, wherein a maximum driving capability of said driving transistor is predetermined. 8. The memory cell is connected between the bit line and the storage node and has a gate connected to a write word line, a read word line as the voltage supply line, and the bit line. 2. The semiconductor memory device according to claim 1, further comprising: the read transistor having a gate connected to the storage node, and a capacitor connected between a gate and a drain of the read transistor. 3. 9. The semiconductor memory device according to claim 8, wherein said bit line comprises a write bit line to which said write transistor is connected, and a read bit line to which said read transistor is connected. 10. The memory cell is connected between the bit line and the storage node and has a gate connected to a write word line, and a write transistor connected between the bit line and the voltage supply line. 2. The semiconductor memory device according to claim 1, further comprising: the read transistor having a gate connected to the storage node; and a capacitor connected between the storage node and a read word line. 11. The semiconductor memory device according to claim 10, wherein said bit line comprises a write bit line to which said write transistor is connected, and a read bit line to which said read transistor is connected. 12. A capacitor when a gate is connected to a storage node, a drain is connected to a voltage supply line, a source is connected to a bit line, and a voltage of the storage node is boosted by a constant voltage through the capacitor. Operating method of a semiconductor memory device including a memory cell including a read transistor that is turned on or off in accordance with a storage node voltage after boosting, and a drive transistor connected between the bit line and a reference voltage supply line Wherein the bit line is discharged to a floating state, the storage node voltage is boosted, and the read transistor is turned on or off according to the boosted storage node voltage to reduce the bit line voltage. At the time of reading to change, the driving transistor is turned on for a certain period including the time of the boosting. The method of reading a semiconductor memory device that. 13. The method according to claim 1, further comprising the step of: amplifying a change in the voltage of the bit line, wherein the predetermined period in which the driving transistor is turned on includes a time when the amplification of the bit line is started.
3. The method for reading a semiconductor memory device according to item 2.