JPH0370877B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field of the Invention> The present invention relates to an improvement of a dynamic type semiconductor memory device, and more particularly to a dynamic type semiconductor memory device having a novel configuration that enables high performance of a dynamic element. It is related to.

<Technical background of the invention and its problems> In the memory cell configuration of a conventional dynamic memory element, the operating margin deteriorates due to manufacturing variations in the load capacitance of complementary bit lines used for inputting and outputting information. There were other problems.

In other words, the conventionally used N channel
The circuit of the MOS dynamic memory element is configured as shown in FIG. 9, for example.

In FIG. 9, S is a sense amplifier, and 1
and 2 are complementary bit lines. Further, 3 and 3' are memory cells, and 4 and 4' are dummy cells. W _i and W _j are word lines W _D0 and W _D1
is a dummy word line, and _φP is a precharge signal.

5 and 5' are storage capacitors, and 6 and 6' select desired storage capacitors 5 and 5' and connect bit lines 1 and 2.
It is a transfer gate for electrically connecting to.

Here, the capacitance values of 5 and 5' are assumed to be C _S .

7 and 7' are dummy storage capacitors, and let their capacitance value be _CD .

8 and 8' are transfer gates for selectively connecting the dummy storage capacitors 7 and 7' to the bit lines 1 and 2, and 9 and 9' initialize the dummy storage capacitors 7 and 7' during the precharge period. It is a gate for

10 and 10' are bit line capacitances, and let the capacitance value be C _B.

FIG. 10 is a timing diagram for explaining the operation of FIG. 9.

In FIG. 9, when the memory cell on the bit line 1 side is selected, the dummy cell 4' on the bit line 2 side is selected, and when the memory cell on the bit line 2 side is selected, the dummy cell 4' on the bit line 1 side is selected. dummy cell 4 is selected.

Here, a case will be described where the word line W _i and the dummy word line W _D0 are at a high potential and the memory cell 3 and the dummy cell 4' are selected.

Here, it is assumed that a voltage boosted to a power supply voltage (Vcc) or higher is applied to the word line W _i and the dummy word line W _D0 .

It is also assumed that bit lines 1 and 2 are precharged to the power supply voltage (Vcc) during the precharge period in which the precharge signal φ _P is at a high potential. For convenience of explanation, the bit line 1 is assumed to be B, and the bit line 2 is assumed to be logic "1" for B: high potential and: low potential, and logic "0" for B: low potential and: high potential.

When the ground potential (GND) is stored in the storage capacitor 5 of the memory cell 3, the precharge signal _φP falls to a low potential and enters the active period, and when the word line signal is input at time _t1 , the bit line 1 side The potential V _B1 of is V _B1 = C _B /C _B +C _S VCC.

On the other hand, the potential V _B2 of bit line 2 on the dummy cell side
is V _B2 =C _B /C _B +C _D Vcc.

Therefore, the differential potential ΔV ₁ input to the sense amplifier S becomes ΔV ₁ =V _B2 V _B1 =(C _B /C _B +C _D −C _B /C _B +C _S )Vcc.

When the power supply potential (Vcc) is stored in the storage capacitor 5 of the memory cell 3: In this case, the potential V _B1 on the bit line 1 side does not change, and V _B1 =Vcc.

On the other hand, the potential V _B2 of bit line 2 on the dummy cell side
Similarly to , V _B2 = C _B /C _B + C _D Vcc.

Therefore, the differential potential ΔV ₂ input to the sense amplifier S becomes ΔV ₂ =V _B1 V _B2 = (1-C _B /C _B +C _D )Vcc.

Here, in both of the above cases, if the storage capacitance value C _D of the dummy cell is determined so that the differential potential input to the sense amplifier S is the same, then the differential potential ΔV input to the sense amplifier is ΔV=ΔV ₁ =ΔV ₂ =1/2·C _S /C _B +C _S Vcc (Formula 1).

The differential potential is amplified to a desired value by activating the sense amplifier S after time _t2 .

In such conventional systems, the load capacity balance of bit lines 1 and 2 is very important.
It is difficult to maintain the capacitance balance of bit lines 1 and 2 due to manufacturing variations, etc., resulting in disadvantages such as deterioration of the operating margin.

Furthermore, with recent advances in microfabrication technology, attempts have been made to realize large-scale memory devices, but the memory cell area inevitably becomes smaller, and the storage capacity within the memory cell tends to decrease further. A new problem has arisen in that it is no longer possible to obtain the differential voltage necessary to drive the sense amplifier.

In addition, as the memory cell area is reduced, the bit line pitch becomes smaller, and it becomes difficult to accommodate control circuits, sense amplifiers, etc. belonging to such bit lines within the bit line pitch while maintaining capacitance balance. It's becoming possible.

<Objects and Structure of the Invention> The present invention has been made in view of the above points, and the present invention improves the differential voltage input to the sense amplifier compared to the conventional method even when the same storage capacitance as the conventional method is used. The memory cell area can be made very small, or the memory cell area can be configured very small to obtain the same differential voltage as in the conventional method, and the stray capacitance balance of the complementary bit lines required in the conventional method can be It is an object of the present invention to provide a dynamic semiconductor memory device which has the advantage that it is not necessary to take this into consideration as carefully as in conventional methods, and the degree of freedom in pattern design of large-scale memory elements is greatly increased. , In order to achieve this objective, the dynamic semiconductor memory device of the present invention has the following features:
It has complementary first and second bit lines for inputting and outputting information, storage capacity means for storing information, and selection means for specifying the storage capacity means, A memory cell configuration in which one end of the storage capacitor means is connected to the first bit line and the other end of the storage capacitor means is connected to the first bit line via the selection means; and sense amplifier means for amplifying the differential voltage output to the second bit line, and the second bit line of the complementary bit line to which the storage capacitor means is directly connected. The second bit line is connected to the sense amplifier means only during the period when the differential voltage is input to the sense amplifier means, and the second bit line is connected to the sense amplifier means during the active period of the sense amplifier means. and control means for disconnecting from the sense amplifier means.

<Embodiments of the invention> A detailed description will be given below with reference to the drawings.

FIG. 1 is a circuit diagram showing the structure of an embodiment of a dynamic semiconductor memory device according to the present invention, which is composed of an N-channel MOS circuit.

In FIG. 1, S is a sense amplifier, 1 and 2
are complementary bit lines similar to those in FIG. 9 described above, and 11 and 11' are memory cells characteristic of the present invention.

W _i and W _j are word lines to which signals having an amplitude equal to or higher than the power supply voltage (Vcc) are applied.

12 and 12' are storage capacitors, one end of which is connected to the second bit line 2 of the complementary bit line, and the other end connected to the source-drain path of the transfer gate 13 or 13' which selects the desired memory cell. and is connected to the first bit line 1, which is the bit line on the opposite side of the complementary bit line.

Further, the gate of the transfer gate 13 is connected to the word line W _i , and the gate of the transfer gate 13' is connected to the word line W _j .

14 and 15 are stray capacitances of bit lines 1 and 2.

Here, the storage capacitance value of memory cell storage capacitors 12 and 12' is set as _CS , and the capacitance value on the bit line 1 side is
C _B1 and the capacitance value on the bit line 2 side are C _B2 . Furthermore, in order to clarify the features of the present invention, it is assumed that these capacitance values C _B1 and C _B2 are different capacitance values (C _B1 ≠ C _B2 ).

16 is a dummy storage capacitor, one end of which is connected to bit line 1, and the other end connected to dummy control signal φ _D
It is connected to the.

17 and 18 are sense input terminals of the sense amplifier S, and 19 is a MOS field effect transistor (hereinafter abbreviated as MOSFET).
Nineteen source-drain paths are interposed between the bit line 2 and the sense input terminal 18, and the bit line is connected only during the period when the voltage of the bit line 2 is inputted to one input terminal 18 of the sense amplifier S by the second control signal φ _T2 . 2 and the input terminal 18 of the sense amplifier are electrically connected.

20 is arranged in connection with an embodiment of the invention.
The source/drain path of the MOSFET 20 is interposed between the bit line 2 and the power supply Vcc, and the second precharge signal φ _P2 controls the bit line 2 during the precharge period, write period, or active period of the sense amplifier S. Hold at power supply potential (Vcc).

Reference numeral 21 designates a conventionally used MOSFET for precharging the bit line. The source/drain path of the MOSFET 21 is interposed between the bit line 1 and the power supply Vcc, and the first precharge signal φ _P1 causes the bit line 1 to be precharged during the precharge period. is held at the power supply potential (Vcc). Reference numerals 22 and 23 are conventionally used transfer gates between the bit line and the sense amplifier, and the first control signal φ _T1 temporarily disconnects the bit line and the sense amplifier at the beginning of driving the sense amplifier, thereby increasing the sense sensitivity. It has the function of making it bigger.

24 and 25 are column selection MOSFETs for selecting desired complementary bit lines, and a desired bit line pair and data bus D are selected by a column selection signal C _i .
By electrically connecting and, information can be input and output.

Here, for convenience, bit line 1 is referred to as B and bit line 2 is referred to as B.
A case will be described in which the memory cell 11 is selected with B: high potential and: low potential set to logic "1", and B: low potential and: high potential set to logic "0".

Writing Logic "1" or Logic "0" A timing diagram for writing in one embodiment of the present invention is shown in FIG.

When the precharge period ends, the first and second precharge signals φ _P1 and φ _P2 fall, and then the word line W _i rises above the power supply voltage (Vcc) and a read operation is started. If the period is a write cycle, data to be written is output onto the data bus D.

The second precharge signal φ _P2 rises above the power supply voltage (Vcc) again, turning on the MOSFET 20 and fixing the bit line 2 to the power supply voltage (Vcc), and the second control signal φ _T2 goes to the ground potential (GND). After the column selection signal C _i reaches the power supply voltage (Vcc), the MOSFET 19 turns off and the bit line 2 and sense amplifier S are disconnected.
The potential increases to the above level, and MOSFETs 24 and 25 are turned on. At this point, data bus D and bit line 1 are electrically connected, so that the write data on data bus D is output onto bit line 1 and sent to node 26 of memory cell 11 via transfer gate 13. be remembered.

In the case of writing a logic "1", the power supply potential is output on the data bus D, and therefore the power supply potential (Vcc) is stored in the node 26 of the memory cell 11. On the other hand, in the case of writing logic "0", the ground potential is output on the data bus D, and therefore the ground potential (GND) is stored in the node 26 of the memory cell 11.

Here, what is the other data bus and bit line 2?
Since MOSFET 19 is in the off state, it is electrically disconnected, so information on the data bus is not involved in writing to the memory cell.

Reading of Logic "1" A timing diagram for reading in one embodiment of the present invention is shown in FIG.

When the precharge period ends, the first precharge signal φ _P1 falls to the ground potential (GND), and the second precharge signal φ _P2 falls to a predetermined potential that can sufficiently turn off the MOSFET 20.
Bit lines 1 and 2 are disconnected from the power supply (Vcc) and become floating.

Next, the dummy drive signal φ _D is raised to the power supply potential (Vcc), and by capacitive coupling of the dummy storage capacitor 16, the potential on the bit line 1 side is slightly raised above the power supply voltage (Vcc).

Next, a selection signal higher than the power supply voltage (Vcc) is input to the word line _Wi , and the transfer gate 13
Bit lines 1 and 2 are capacitively coupled via storage capacitor 12.

Since the power supply potential (Vcc) was previously held at the node 26 of the memory cell 11, the potentials of the bit lines 1 and 2 only slightly change toward the lower potential side;
No reversal of potential occurs.

If the differential voltage between bit lines 1 and 2 in this case is ΔV ₁ , then ΔV ₁ = 1/1 + (C _S /C _B2 ) + (C _G /C
_B1 +C _D )·C _D /C _B1 +C _D ·Vcc (Formula 2) The differential voltage ΔV ₁ is input to the input terminals 17 and 18 of the sense amplifier S.

Next, the first control signal φ _T1 drops to a predetermined potential, disconnecting the sense amplifier S and bit lines 1 and 2, and then the second control signal φ _T2 drops to the ground potential (GND), and the second control signal φ T2 drops to the ground potential (GND). The second precharge signal φ _P2 rises again to a potential higher than the power supply voltage (Vcc) and turns on the MOSFET 20, thereby fixing the second bit line 2 to the power supply potential (Vcc).

Next, the sense amplifier drive signal φ _S falls to the ground potential, and the differential voltage input to the sense amplifier S is amplified to a desired voltage. in this case,
Node 26 of memory cell 11 holds a high potential, and there is no need for rewriting.

Reading a logic "0" A timing diagram of the bit line and sense input signal for reading a logic "0" is also shown in FIG.

The operation until the selection signal is input to the word line W _i is similar to reading a logic "1". In the case of reading logic "0", the ground potential (GND) is held in advance at the node 26 of the memory cell 11, so when the transfer gate 13 is turned on by the selection signal, the potential of the bit line 1 drops. Conversely, the potential of bit line 2 increases, and the potentials of bit line 1 and bit line 2 are reversed. If the differential voltage between bit lines 1 and 2 in this case is ΔV ₂ , then ΔV ₂ = 1/1 + (C _S /C _B2 ) + (C _S /C _B1 + C _D
)・{C _S /C _B2 +C _S −C _D /C _B1 +C _D }・Vcc... (Formula 3) The differential voltage ΔV ₂ is input to the input terminals 17 and 18 of the sense amplifier S.

Next, the first control signal φ _T1 drops to a predetermined potential in the same way as when reading logic “1”, and after disconnecting the sense amplifier S and bit lines 1 and 2, the second control signal φ _T2 goes to ground. The voltage drops to the potential (GND), and the second precharge signal _φP2 rises again to a potential higher than the power supply potential (Vcc).
By turning on MOSFET20, the second
The bit line 2 of is fixed to the power supply potential (Vcc).

Next, the sense amplifier drive signal φ _S falls to the ground potential, and the differential voltage input to the sense amplifier S is amplified to a desired voltage, and
The bit line 1 is discharged to the ground potential through the MOSFET 22, and the node 26 of the memory cell 11 is connected to the node 26 of the memory cell 11.
Rewrite the ground potential (GND) to the

Here, the differential voltages ΔV ₁ and ΔV ₂ between the bit lines when reading logic “1” and logic “0”
The dummy storage capacitance value C _D is set so that both are equal.
If we set dummy storage capacitance value C _D
becomes C _D =C _B1 +C _B2 /2C _B2 -C _S・C _S , and (Equation 2) and (Equation 3) become ΔV=ΔV ₁ =ΔV ₂ =1/1+(C _S /C _B2 ) +{C _S (2C
_B2 −C _S )/C _B2 (2C _B1 +C _S )}・C _S (C _B1 +C _B2 )/C _B2 (
2C _B1 +C _S )・Vcc...(Formula 4).

Here, in order to clarify the features of this method compared to the conventional method, the differential signal voltage input to the sense amplifier under the condition of C _B1 + C _B2 = 2C _B is expressed as (Equation 4) and ( It is calculated from Equation 1) and the results are shown in FIGS. 4 and 5.

FIG. 4 shows the relationship between the differential signal voltage and the stray capacitance ratio C _B1 /C _B2 of bit line 1 and bit line 2 in the embodiment of the present invention when C _B /C _S =10.

As is clear from the graph shown in FIG. 4, according to the present invention, if the sum of stray capacitances C _B1 and C _B2 of complementary bit lines 1 and 2 is constant, C _B1 and C _B2 are Since the differential signal voltage increases as the difference increases, the best way to utilize the features of the present invention is to minimize the stray capacitance of one bit line as much as possible.
This results in a larger differential signal voltage.

This is a very important feature of the present invention, and completely eliminates the restriction that the stray capacitances of complementary bit lines must be the same as in the conventional system, and increases the degree of freedom in pattern design. becomes very large.

FIG. 5 shows the conventional method and the embodiment according to the present invention under the condition that C _B1 +C _B2 =2C _B.
The differential signal voltage characteristics when changing the C _B /C _S ratio are shown.

28 is the differential signal voltage characteristic of the conventional system obtained from (Formula 1), and 27 is the differential signal voltage characteristic obtained from (Formula 4) in an embodiment of the present invention.

In one embodiment of the present invention, from FIG. 4, C _B1 /
It has been shown that the differential signal voltage is the smallest when the value of C _B2 is around 1.0, but even in such a worst case, as shown in graph 28 in Figure 5, the differential signal voltage is about 1.5 to 2 times that of the conventional method. A differential signal voltage of 1 is obtained, and the characteristics shown in graphs 29 and 30 can be realized by devising the distribution of the bit line stray capacitance.

This means that by employing the present invention, the differential signal voltage can be increased without changing the storage capacity of the memory cell, which is very effective as a means for realizing a large-scale memory element.

6 and 7 are diagrams showing the memory cell structure of the dynamic semiconductor memory device according to the present invention shown in FIG. 1, respectively.

FIG. 6 shows a cross-sectional structure taken along line A-A' in FIG. 7.

FIG. 7 is a pattern diagram for four memory cells (M ₀ to M ₃ ), and in an actual memory element, this pattern is repeatedly arranged as many times as necessary.

Next, the structure of a memory cell realizing the semiconductor memory device of the present invention will be described with reference to FIG. 6, assuming an N-channel MOS process.

First, an element isolation region 32 is formed on the surface of a P-type silicon substrate 31 by selective oxidation or the like, and then a portion 33 forming a word line and a transfer gate of a memory cell is formed by a first wiring means.

Next, diffusion regions 34 and 35 which will become the source and drain of the MOSFET are formed by ion implantation or the like.

Next, the drain part 3 of the transfer gate part
After opening the embedded contact window 36 in the second
One electrode 37 of the storage capacitor is formed by wiring means and connected to the drain 34 of the transfer gate portion through the buried contact window 36.

Here, the electrode 37 formed by the second wiring means can also be formed on the upper surface of the first wiring means 33, contributing to an increase in the storage capacity of the memory cell. After forming a thin insulating film 38 for forming a storage capacitor on the upper surface of the second wiring means, the other electrode of the storage capacitor is formed by a third wiring means 39, and then an insulating film 40 is formed.

Next, after opening the normal contact window 50, the fourth contact window 50 is opened.
A wiring means 51 is formed and connected to the source region 35 of the transfer gate portion through the contact window 50.

Here, the first to third wiring means are generally made of ordinary polysilicon, silicide, high melting point metal, etc., and the fourth wiring means is generally made of aluminum, etc. It is.

Fourth wiring means 51 and third wiring means 39
are shared by a plurality of memory cells, and constitute complementary bit lines. In other words, in the memory cell structure that implements the device according to one embodiment of the present invention, complementary bit lines are formed with different wiring means in a multilayer structure, and therefore complementary bit lines are formed with the same wiring means. The memory cell area can be reduced compared to the conventional method. Further, the area of the diffusion regions 34 and 35 is the same as that of the contact window 36.
, and 50 is sufficient, the diffusion region within the memory cell is smaller than in the conventional method, and the resistance to alpha rays is increased, making it possible to realize a safe memory element.

FIG. 8 is a diagram showing an example of the arrangement of a memory cell array in a device according to an embodiment of the present invention.

It has already been mentioned that according to the memory cell configuration according to the present invention, the memory cell area can be significantly reduced. However, as a result, the control circuits, sense amplifiers, etc. for the bit line pairs to which the memory cells are connected require a relatively larger area than the memory cells. A problem arises in that it becomes difficult to house the circuit.

These problems can be solved by arranging the control circuits, sense amplifiers, etc. that belong to a single or multiple bit line pairs at both ends of each bit line pair.

In FIG. 8, C ₀ to C ₆₃ are complementary bit line pairs, and K ₀ to _{K 63} are control circuits, sense amplifiers, etc. belonging to each complementary bit line pair C ₀ to _{C 63} . An example is shown in which they are arranged alternately at both ends of the pair.

Although the present invention has been explained using an N-channel MOS process in the above embodiments, the present invention does not limit the manufacturing process for realizing the device, and the present invention is not limited to a P-channel MOS process.
It can be applied to MOS process, CMOS process, SOI process, etc.

<Effects of the Invention> As described above, according to the present invention, the memory cell area can be made extremely small while maintaining a sufficient operating margin, thus greatly contributing to the realization of large-scale dynamic memory devices. You can.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a device according to an embodiment of the present invention, FIG. 2 is a timing diagram in a write cycle to explain the operation of an embodiment of the present invention, and FIG. 3 is an embodiment of an embodiment of the present invention. FIG. 4 is a timing diagram in a read cycle for explaining the operation in the example, and shows the relationship between the differential signal voltage and the stray capacitance ratio of the complementary bit lines during reading between the complementary bit lines in one embodiment of the present invention. A characteristic diagram showing the relationship; FIG. 5 is a graph comparing differential signal voltages between complementary bit lines in a conventional system and an embodiment of the present invention; FIG. 6 is a graph for realizing a device according to an embodiment of the present invention. 7 is a plan view of a memory cell structure for realizing a device according to an embodiment of the present invention, and FIG. 8 is a diagram showing complementary bit lines and a control circuit in a device according to an embodiment of the present invention. , a conceptual diagram for explaining the arrangement of sense amplifiers, etc., FIG. 9 is a circuit diagram of a dynamic memory element in the conventional system, and FIG. 10 is a timing chart for explaining the operation in the conventional system. W _i , W _j ...word line, W _D0 , W _D1 ... dummy word line, φ _P ... precharge signal, φ _P1 ... first
precharge signal, φ _P2 ... second precharge signal, φ _D ... dummy control signal, φ _T1 ... first control signal, φ _T2 ... second control signal, φ _S ... sense drive signal, C _i ...column selection signal, D,...data bus, C _B , C _B1 , C _B2 ...bit line capacitance value, C _S ...
Storage capacitance value of memory cell, C _D ...Storage capacitance value for dummy, 1, 2, B,...Bit line, S...Sense amplifier, 3, 3', 11, 11'...Memory cell, 4, 4'... Dummy cell, 12, 12'... Memory cell storage capacity, 13, 13'... Transfer gate, 16... Dummy storage capacitor, 32...
...Element isolation region, 34, 35...Diffusion region, 36
...Buried contact window, 38...First wiring layer, 37...Second wiring layer, 39...Third wiring layer, 51...Fourth wiring layer, 38...Thin insulating film, 50 ... Contact window, C ₀ - C ₆₃ ... Complementary bit line pair, K ₀ - _{K 63} ... Control circuit, sense amplifier, etc. belonging to the complementary bit line pair.

Claims (1)

[Claims] 1. Complementary first and second devices for inputting and outputting information
a bit line, a storage capacity means for storing information,
It has a selection means for specifying the storage capacity means, one end of the storage capacity means is connected to the second bit line, and the other end of the storage capacity means is connected to the first bit line through the selection means. a memory cell structure connected to the first and second complementary bit lines; a sense amplifier means for amplifying the differential voltage output to the complementary first and second bit lines; The second bit line connected to the sense amplifier means is connected to the sense amplifier means only during the period when the differential voltage is input to the sense amplifier means, and during the active period of the sense amplifier means. A dynamic semiconductor memory device comprising control means for disconnecting the second bit line from the sense amplifier means. 2. The second bit line directly connected to the storage capacitor means is fixed at a predetermined potential unrelated to read or write information during the active period of the sense amplifier means. A dynamic semiconductor memory device according to claim 1. 3. The second bit line on the side to which the storage capacitor means is directly connected is fixed at a predetermined potential unrelated to read or write information during a standby period and/or a write period in which information is written into a predetermined memory cell. A dynamic semiconductor memory device according to claim 1, characterized in that the dynamic semiconductor memory device is constructed as follows.