JPS60256998A - Dynamic semiconductor storage device - Google Patents

Abstract

PURPOSE:To increase the differential signal voltage without changing a storage capacitance of a memory cell by connecting a bit line to which the storage capacitance is connected directly to a sense amplifier only when a difference voltage is inputted to the sense amplifier. CONSTITUTION:A data is outputted to a data bus D at write cycle. Then an MOSFET20 is turned on, the bit line 2 is fixed to a power supply potential, an MOSFET19 is turned off, and after the bit line 2 and the sense amplifier S are disconnected, MOSFETs 24, 25 are turned on. A write data on the bus D is stored in a node 26 of a memory cell 11 via a transfer gate 13. Then the FET20 is turned off, a selection signal is inputted to a word line Wi and the bit lines 1, 2 are connected to the storage capacitance 12 via a gate 13. In this case, a differential voltage between the bit lines 1 and 2 is inputted to input terminals 17, 18 of the amplifier S. Then the transfer gates 22, 23 are turned off, a drive signal phiS falls down and the differential voltage of the amplifier S is amplified.

Description

[Detailed Description of the Invention] <Technical Field of the Invention> The present invention relates to improvement of a dynamic semiconductor memory device.
More specifically, the present invention relates to a dynamic semiconductor memory device having a novel configuration that enables high performance dynamic elements.

<Technical background of the invention and its problems> In the memory cell configuration of a conventional dynamic memory element, the operating margin deteriorates due to manufacturing variations in the load capacitance of complementary bit lines used for inputting and outputting information. There were problems such as:

That is, the circuit of a conventionally used N-channel MOS dynamic memory element is configured as shown in FIG. 9, for example.

In FIG. 9, S is a sense amplifier, and 1 and 2 are complementary bit lines. Further, 3 and 3' are memory cells and recells, and 4 and 4' are dummy cells. Wi and W
j is a word line, Wvo and WD+ are dummy word lines, and φp is a precharge signal.

5 and 5' are storage capacitors, and 6 and 6' are transformer 7 agates for selecting desired storage capacitors 5 and 5' and electrically connecting them to the bit lines 1 and 2.

Here, the capacitance values of 5 and 5' are assumed to be C8.

7 and 7' are dummy storage capacitors, whose capacitance value is C1.
).

8 and 8' are transfer gates for selectively connecting the dummy storage capacitors 7 and 7' to the bit lines 1 and 2, and 9 and 9' are transfer gates for connecting the dummy storage capacitors 7 and 7' to the bit lines 1 and 2 during the precharge period.
and 7'.

10 and 10' are bit line capacitances, and the capacitance value is c
Let it be B.

FIG. 1θ is a timing diagram for explaining the operation of FIG. 9.

In FIG. 9, when the memory cell on the bit line 1 side is selected, the dummy cell 4' on the bit line 2 side is selected;
Furthermore, when the memory cell on the bit line 2 side is selected, the dummy cell 4 on the bit line 1 side is selected.

Here, a word line Wi and a dummy word line WD.

A case where the potential becomes high and the memory cell 3 and the dummy cell 4' are selected will be explained.

Here, it is assumed that a voltage boosted to a power supply voltage (Vcc) or higher is applied to the word line Wi and the dummy word line WDQ.

Furthermore, during the precharge period when the precharge signal φp is at a high potential, bit lines 1 and 2 are connected to the power supply voltage (VCC
) is assumed to be precharged. For convenience of explanation, let bit line 1 be B1 and bit line 2 be B, and B: high potential and B: low potential logic i ++ , +1, and B
: Low potential and B: High potential as logic 6'0''.

■When the ground potential (GND) is stored in the storage capacitor 5 of the memory cell 3, the precharge signal φβ falls to a low potential and enters the active period.
When a word line signal is input at time t1, bit line 1
The potential VBI on the side becomes 2.

On the other hand, the potential ■B2 of the bit line 2 on the dummy cell side is cB VB2=CB+cDvCC becomes.

Therefore, it becomes a differential potential input to the sense amplifier S.

(2) When the power supply potential (Vcc) is stored in the storage capacitor 5 of the memory cell 3 In this case, the potential VBI on the bit al side does not change, and VB1=Vcc.

On the other hand, the potential VB2 of the bit line 2 on the dummy cell side is as follows.

Therefore, the differential potential Δv2 input to the sense amplifier S is as follows.

Here, in both cases of ■ and ■ above, if the storage capacitance value CD of the dummy cell is determined so that the differential potential input to the sense amplifier S is the same, then the differential potential input to the sense amplifier ΔV is as follows.

The differential potential is amplified to a desired value by activating the sense amplifier S after time t2.

In this conventional method, the load capacitance balance between bit lines 1 and 2 is very important, but due to manufacturing variations, etc., it is difficult to maintain the capacitance balance between bit lines 1 and 2, which worsens the operating margin. There were drawbacks such as:

In addition, with recent advances in microfabrication technology, attempts have been made to realize υ large-scale memory devices, but the memory cell area inevitably becomes smaller, and therefore the storage capacity within the memory cell is reduced to 1.
As a result, a new problem has arisen in that it is no longer possible to obtain the differential voltage necessary to drive the sense amplifier.

Furthermore, as the memory cell area is reduced, the bit line pitch becomes smaller, and it becomes difficult to accommodate the control circuits, sense amplifiers, etc. belonging to such bit lines within the above bit line pitch while maintaining capacitance balance. It's becoming possible.

<Objects and Structure of the Invention> The present invention has been made in view of the above points, and the present invention improves the differential voltage input to the sense amplifier compared to the conventional method even when the same storage capacitor as the conventional method is used. The memory cell area can be made very large, or the memory cell area can be made much smaller in lJ to obtain the same differential voltage as the conventional method, and the complementary bit line floating required in the conventional method can be An object of the present invention is to provide a dynamic semiconductor memory device which has the advantage that there is no need to carefully consider capacity balance as in conventional methods, and therefore the degree of freedom in designing a large-scale memory element is greatly increased. In order to achieve this object, the dynamic semiconductor memory device of the present invention includes complementary first and second bit lines for inputting and outputting information, storage capacitor means for storing information, and storage capacity means for storing information. selection means for specifying the capacity means;
A memory cell in which one end of the storage capacitor means is connected to the second bit line, and the other end of the storage capacitor means is connected to the first bit line via the selection means. a sense amplifier means for amplifying the differential voltage outputted to the complementary first and second bit lines; and a sense amplifier means that is directly connected to the storage capacitor means among the complementary bit lines. Connecting the second pinpoint line to the sense amplifier means only during the period when the differential voltage is inputted to the sense amplifier means with respect to the second pinpoint line on the side where the voltage is applied;
The control means disconnects the second bit line from the sense amplifier means during the active period of the sense amplifier means.

<Embodiments of the invention> A detailed description will be given below with reference to the drawings.

FIG. 1 is a circuit diagram showing the structure of an embodiment of a dynamic semiconductor memory device according to the present invention, which is composed of an N-channel MO5 circuit.

In FIG. 1, S is a sense amplifier, 1 and 2 are complementary bit lines similar to those in FIG. 9, and 11 and 11 are complementary bit lines.
' is a characteristic memory cell in the present invention.

Wi and Wj are word lines to which signals having an amplitude equal to or higher than the power supply voltage (Vcc) are applied. "12 and 12'
is a storage capacitor, one end of which is connected to the second complementary bit line.
The first bit line l, which is the bit line on the opposite side of the complementary bit line, is connected to bit line 2 of connected to.

Further, the gate of the transfer gate 13 is connected to the word line W.
1, and the gate of the transfer gate 18' is connected to the word line Wj.

14 and 15 are stray capacitances of bit lines 1 and 2.

Here, the storage capacitance value of the memory cell storage capacitors 12 and 12' is set as C8, and the capacitance value on the bit line 1 side is set as CBI+the capacitance value of bit-0 as cB2. Capacity value CBII
In order to clarify the features of the present invention, it is assumed that CB2 has a different capacitance value (CB+"qcB2).

16 is a dummy storage capacitor, one end of which is connected to bit line 1.
The other end is connected to the dummy control signal φD.

17 and 18 are the sense input terminals of the sense amplifier S,
19 is MO3 field effect transistor (hereinafter MO3FE)
The source-drain path of the MO5FET 19 is interposed between the bit line 2 and the sense input terminal 218, and the voltage of the bit line 2 is controlled by the second control signal φT2 to one input terminal of the sense amplifier S. The bit line 2 and the input terminal 18 of the sense amplifier are electrically connected only during the period of input to the sense amplifier 18.

20 is a MOS arranged in connection with the embodiment of the present invention
FET, the source-drain path of the MO5FET 20 is interposed between the bit line 2 and the power supply Vcc, and the second
The bit line 2 is held at the power supply potential (Vcc) by the precharge signal φp2 during the precharge period, the write period, or the active period of the sense amplifier S.

21 is a conventionally used bit line precharge MOS FET, and the MOS FET2+
A source drain path is interposed between the bit line l and the power supply VCC, and the bit line l is set to the power supply potential (VCC
). Reference numerals 22 and 23 are conventionally used transfer gates between the bit line and the sense amplifier, and the first control signal φT1 temporarily disconnects the bit line and the sense amplifier at the beginning of driving the sense amplifier, thereby increasing the sense sensitivity. There is a function to do that.

24 and 25 are column selection MO5FETs for selecting a desired complementary bit line, and a column selection signal Ci [Therefore, by electrically connecting a desired bit line pair to data buses D and Df, information input is performed. Perform output.

Here, for convenience, bit line 1 is assumed to be B and bit line 2 is assumed to be B: high potential and B: low potential as logic ffr, II,
Further, a case will be described in which the memory cell 11 is selected with B: low potential and B: high potential as logic RO'''.

■ Writing of logic R, +1 or logic +1011 The timing diagram for writing in one embodiment of the present invention is shown in the second diagram.
As shown in the figure.

7' When the IJ charge period ends, the first and second precharge signals 1 and φ, 2 fall, and then the word line Wi rises above the power supply voltage (v c'c ), and the readout starts. Operation is started, and if the current active period is a write cycle, the data to be written is output to the data bus P.

Second precharge signal φp? is again the power supply voltage (Vcc
), the MO5FET20 turns on and the bit line 2 is fixed at the power supply potential (VCC), and the second control signal φT2 falls to the ground potential (GND) and the MQ
SFET? 9 is turned off and the bit line 2 and sense amplifier S are disconnected, the column selection signal Ci changes to the power supply voltage (
Vcc) or higher, the MO5FETs 24 and 25 turn on. At this point, the data bus D and the bit line l are electrically connected, so that the write data on the data bus D is output onto the bit line 1, and is passed through the transfer gate 13 to the node 26 of the memory cell 11.
is memorized.

Here, in the case of writing the logic "J", the power supply potential is output on the data bus D, and therefore the power supply potential (Vcc) is stored in the node 26 of the memory cell 11. On the other hand, in the case of writing logic +l O++, the ground potential is output on the data bus D, and therefore the ground potential (GND) is stored in the node 26 of the memory cell 11.

Here, the other data bus D and bit line 2 are MO5FE
Since T19 is in the off state, it is electrically disconnected, and therefore the information on data bus D is not involved in writing to the memory cell.

(2) Reading of logic ++, ++ A timing diagram for reading in one embodiment of the present invention is shown in FIG.

When the precharge period ends, the first precharge signal φp1 falls to the ground potential (GND) K, and the second precharge signal φp2 falls to a predetermined potential that can sufficiently turn off the MO3FET 20, and the bit lines 1 and 2 is disconnected from the power supply (Vcc) and placed in a floating state.

Next, the dummy drive signal φD is raised to the power supply potential (VCC), and due to capacitive coupling of the dummy storage capacitor 16, the potential on the bit line 1 side is slightly raised above the power supply voltage (Vcc).

Next, a selection signal higher than the power supply voltage (VCC) is input to the word line Wi, and the bit lines I and 2 are capacitively coupled by the storage capacitor 12 via the transfer gate 13'r.

The node 26 of the memory cell 11 is previously connected to a power supply potential (VC
Since C) is maintained, the potentials of bit lines 1 and 2 only slightly change to the lower potential side, and the potentials of bit lines 1 and 2 are unlikely to be reversed.

The differential voltage between bit lines 1 and 2 in this case is Δ
v1, then the differential voltage ΔV1 is input to the input terminals 17 and 18 of the sense amplifier S.

Next, the first control signal φTl falls at a predetermined potential level, disconnecting the sense amplifier S and bit lines 1 and 2, and then
The second control signal φT2 falls to the ground potential (GND), and the second precharge signal φp2 returns to the power supply voltage (GND).
By increasing the potential to the power supply potential (Vcc) or higher and turning on the MO3FET 20, the second bit line 2 is set to the power supply potential (Vcc).
cc).

Next, the sense amplifier drive signal φ8 falls to the ground potential,
The differential voltage input to the sense amplifier S is amplified to a desired voltage. In this case, node 2 of memory cell 11
6 holds a high potential and there is no need to rewrite it.

(2) Logic +l OI+ read logic ++ A timing diagram of the bit line and sense input signal in reading O'' is also shown in FIG.

The operation until the selection signal is input to the word line W1 is the same as reading the logic "1". In the case of reading the logic +tO", the node 26 of the memory cell 11 is connected to the ground potential (GND) in advance. is held, so when transfer gate 18 is turned on by the selection signal, bit line 1
The potential of bit line 2 decreases, and conversely, the potential of bit line 2 increases, and the potentials of bit line 1 and bit line 2 are reversed. If the differential voltage between bit lines 1 and 2 in this case is ΔV2, then the differential voltage Δ■2 is input to the input terminals 17 and 18 of the sense amplifier S.

Next, in the same way as reading the logic "L", the first control signal φT
1 falls at a predetermined potential switch, and after the sense amplifier S and the bits I and 2f are disconnected, the second control signal φT2
falls to the ground potential (GND), and the second precharge signal φp2 rises again at a potential higher than the power supply potential (Vcc,), turning on the MOS and FE720, and the second bit Line 2 is fixed at the power supply potential (Vcc) K.

Next, the sense amplifier drive signal φS falls to the ground potential,
The differential voltage input to the sense amplifier S is amplified to a desired voltage, and the bit line l is discharged to the ground potential via the MO3FET 22, thereby rewriting the ground potential (GND) to the node 26 of the memory cell 11. Do the following.

Here, the dummy storage capacitance value Ca+t is determined so that the differential voltages Δvl and ΔV2 between the bit lines in reading logic 11, 11 and logic ++On are both equal. If set, the dummy storage capacitance value cD becomes, and (Equation 2) and (2) become as follows.

Here, in order to clearly clarify the features of this method when compared with the conventional method, the differential signal voltage input to the sense amplifier under the condition of CDI +'CB2 = 2CB is expressed as (Equation 4) and ( From equation 1'), the results are shown in FIGS. 4 and 5.

FIG. 4 shows the relationship between the differential signal voltage and the stray capacitance ratio CBI/CB2 of the bit line 1 and the heat line 2 in the embodiment according to the present invention when CB/C3=10.

As is clear from the graph shown in Figure 4,
According to the present invention, if the stray capacitances of CBI and CB2 are constant, then CBI and C
Since the differential signal voltage increases as the difference in B2 increases, in order to make the most of the features of the US invention,
The goal is to minimize the stray capacitance of one bit line as much as possible, thereby obtaining a larger differential signal voltage.

This is a very significant feature of the present invention, and completely eliminates the restriction that complementary bit lines must have the same stray capacitance as in conventional systems.
The degree of freedom in pattern design is greatly increased. Figure 5 shows that the CB/C3 ratio is changed for the conventional method and the embodiment according to the present invention under the five conditions of cBl + CB2 '' 2CB. The differential signal voltage characteristics are shown below.

28 is a differential signal voltage characteristic of the conventional system obtained by formula (1), and 27 is a differential signal voltage characteristic obtained by formula (4) in an embodiment of the present invention.

In one embodiment of the present invention, from FIG. 4, CBI /cB
It has been shown that the differential signal voltage becomes the smallest when the value of 2 is around 1 (11), but even in such a worst case, as shown in graph 28 of FIG.
A differential signal voltage approximately twice as large is obtained, and the characteristics shown in graphs 29 and 30 can be achieved by devising the distribution of the bit line stray capacitance.

This means that by employing the present invention, the differential signal voltage can be increased without changing the storage capacity of the memory cell, which is very effective as a means for realizing a large-scale memory element.

6 and 7 are diagrams showing the memory cell structure of the dynamic semiconductor memory device according to the present invention shown in FIG. 1, respectively.

FIG. 6 shows a cross-sectional structure taken along line AA' in FIG. 7.

FIG. 71 is a Kuhn diagram for four memory cells (Mo=Ma), and in an actual memory element, this pattern is repeatedly arranged as many times as necessary.

Next, with reference to FIG. 6, the structure of a memory cell that realizes the semiconductor memory device of the present invention will be explained assuming an N-channel MOS process. After that, seven portions 33 forming the word lines and the transfer gates of the memory cells are formed by the second wiring means.

Next KMO5FETL7) Diffusion regions 34 and 35 that will become the source and drain are formed by ion implantation or the like.

Next, after a buried contact window 36 is opened in the drain portion 34 of the transfer gate portion, a single electrode 37 of the storage capacitor is formed by the second wiring means, and the buried contact window 36 is connected to the drain portion 34 of the transfer gate portion. Connecting.

Here, the electrode 37 formed by the second wiring means can also be formed on the upper surface of the first wiring means 33, contributing to an increase in the storage capacity of the memory cell. After forming a thin insulating film 38 for forming a storage capacitor on the upper surface of the second wiring means, the other electrode of the storage capacitor is formed by a third wiring means 89, and then an insulating film 40 is formed.

Next, after opening a normal contact window 50, a fourth wiring means 51 is formed, and the contact window 50 is connected to the source region 35 of the transfer gate portion.

Here, the first to third wiring means are generally made of ordinary polysilicon, silicide, or high-melting point metal, and the fourth wiring means is generally made of aluminum or the like. It is true.

The fourth wiring means 51 and the third wiring means 39 are shared by a plurality of memory cells, and constitute complementary bit lines. In other words, in the memory cell structure that implements the device according to one embodiment of the present invention, complementary bit lines are formed with different wiring means in a multilayer structure, and therefore complementary bit lines are formed with the same wiring means. The memory cell area can be reduced compared to the conventional method. In addition, since the area of the diffusion regions 34 and 35 is sufficient to form the contact windows 36 and 50, the diffusion region in the memory cell is smaller compared to the conventional method, and the resistance to alpha rays is increased, resulting in a stable memory. Elements can be realized.

FIG. 8 is a diagram showing an example of the arrangement of a memory cell array in a device according to an embodiment of the present invention.

It has already been mentioned that according to the memory cell configuration according to the present invention, the memory cell area can be significantly reduced. but,
As a result, control circuits, sense amplifiers, etc. for the bit line pairs to which memory cells are connected require a relatively larger area than the memory cells, and the above circuits must be placed within the repeating bit line pitch. The problem arises that it becomes difficult to store.

Such problems can be solved by arranging the control circuits, sense amplifiers, etc. that belong to a single bit line pair or a plurality of bit line pairs at both ends of each bit line pair.

In FIG. 8, Co-C63 is a complementary bit line pair, and KQ-63 is a complementary bit line pair C.
The control circuits, sense amplifiers, etc. belonging to o to C6B are arranged alternately at both ends of each bit line pair. In order to explain the present invention, in the above embodiment, an N-channel MOS process is used. Although the present invention was explained using
The manufacturing process for realizing the device is not limited, and can be applied to a P-channel MOS process, a CMOS process, an SOI process, etc.

<Effects of the Invention> As described above, according to the present invention, the memory cell area can be made extremely small while maintaining a sufficient operating margin, and thus greatly contributes to the realization of large-scale dynamic memory devices. Rukoto can.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a device according to an embodiment of the present invention, FIG. 2 is a timing diagram in a write cycle to explain the operation of an embodiment of the present invention, and FIG. 3 is an embodiment of an embodiment of the present invention. FIG. 4 is a timing diagram in a read cycle for explaining the operation in an example, and shows the relationship between the differential signal voltage during read between complementary bit lines and the stray capacitance ratio of complementary bit lines in one embodiment of the present invention. Figure 5 is a graph comparing differential signal voltages between complementary bit lines in a conventional system and an embodiment of the present invention, and Figure 6 is a graph showing a device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view of a memory cell structure to be realized, FIG. 7 is a cross-sectional view of a memory cell array for realizing a device according to an embodiment of the present invention, and FIG. 8 is a diagram showing complementary bit lines in a device according to an embodiment of the present invention. Conceptual diagram for explaining the arrangement of control circuits, sense amplifiers, etc.
FIG. 9 is a circuit diagram of a dynamic memory element in the conventional method, and FIG. 10 is a timing diagram for explaining the operation in the conventional method. Wi, Wj-word line, WDOl wD, dummy word line, φP... precharge signal, φP+
...first precharge signal, φP2...second precharge signal, φD...dummy control signal, φT1...
・First control signal, φT2...Second control signal, φS
...Sense drive signal, Ci...Column selection signal, D, D
...Data bus, clj+,... cBl + CB2...Bit line capacitance value, C5...Storage capacitance value of memory cell, cD...Storage capacitance value for dummy, 1°2, B, B...Bit line, S...Sense amplifier , 3°8',] I, 11'...Memory cell, 4,
4'...Dummy cell, 12.12'...Storage capacity of memory cell, 13°13'...Transfer gate,
16... Dummy storage capacitor, 32... Element isolation region, 34.85... Diffusion region, 36... Buried contact window, 33... First wiring layer, 37... Second wiring layer, 39... third wiring layer, 51... fourth wiring layer, 38... thin insulating film, 50... contact window, CD-C63... complementary bit line pair , K (1 = 68...Control circuits, sense amplifiers, etc. belonging to complementary bit line pairs. Agent: Patent attorney Yoshihiko Fuku (and 2 others) 0ν = 1L Fig. 5 1 Fig. 7 Fig. 8 Figure Woo Wbt φp wt 7/12

Claims (1)

[Scope of Claims] l Complementary first and second bit lines for inputting and outputting information, storage capacitor means for storing information, and selection means for specifying the storage capacitor means; a memory cell configuration in which one end of the storage capacitor means is connected to the first bit line, and the other end of the storage capacitor means is connected to the first bit line via the selection means; a sense amplifier for amplifying a differential voltage output to a second bit line; and a sense amplifier for a second bit line to which the storage capacitor is directly connected among the complementary bit lines. control for connecting the second bit line to the sense amplifier means only during the period when the differential voltage is input to the means, and disconnecting the second bit line from the sense amplifier means during the active period of the sense amplifier means; A dynamic semiconductor memory device characterized by having all the means and features. 2. The second bit line to which the storage capacitor means is directly connected is fixed at a predetermined potential unrelated to read or write information during the active period of the sense amplifier means. A dynamic semiconductor memory device according to claim 1, characterized in that: 3. The second bit line on the side to which the storage capacitor means is directly connected is set to a predetermined potential unrelated to read or write information during a standby period and/or a write period in which information is written into a predetermined memory cell. 2. The dynamic semiconductor memory device according to claim 1, wherein the dynamic semiconductor memory device is fixed.