JP2001202776A - Ferroelectric memory and data read-out method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to apply symmetric voltage to a ferroelectric capacitor at the time of rewriting and to enlarge read-out margin of data so that it can be easily discriminated by a sense amplifier. SOLUTION: This device isprovided with at least one memory cell 16 provided with a ferroelectric capacitor 12 and a selection transistor 14 in which one end 14a of a main current path is connected to one side of an electrode 12a of the ferroelectric capacitor, a word line WL 1 connected to a control electrode 14x of the selection transistor, a bit line BL 1 connected to other ends 14 of the main current path of the selection transistor, a plate line PL 1 connected to the other electrode 12b of the ferroelectric capacitor, a sense amplifier 28 connected to a bit line, and a plate line driver 30 applying voltage to the plate line, and the plate line driver is constituted as a voltage generating circuit which generates selectively first voltare as power source voltage and second voltage being lower voltage than power source voltage by threshold voltage of the selection transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a ferroelectric memory using polarization of a ferroelectric and a method of reading data from the ferroelectric memory.

[0002]

2. Description of the Related Art FIG. 11 is a circuit diagram showing a configuration of a conventional 2T2C type ferroelectric memory (FeRAM). FIG.
1 shows a memory array structure of a general 2T2C type FeRAM. This FeRAM includes a plurality of word lines WL0 to WL3, a plurality of plate lines PL0 and PL1, and a plurality of bit lines BL0 to BL3. In FIG. 11, the word lines are connected to the four WL0-WL3.
Although two plate lines PL0 and PL1 and four bit lines BL0 to BL3 are shown, the number of each line is not limited thereto. Each of these lines is connected to memory cells 100a to 100d composed of a selection transistor and a ferroelectric capacitor. In addition, FeR
The AM has a sense amplifier 102. Each bit line B
L0 to BL3 are connected to the sense amplifier 102. This sense amplifier 102 operates according to a sense amplifier activation signal SAE. Further, each plate line PL0
And PL1 have a plate line driver 104 respectively.
Is connected. Generally, CMOS inverters are used as the plate line drivers 104.

A memory cell of a 2T2C type FeRAM includes two selection transistors and two ferroelectric capacitors. For example, the memory cell 1 in FIG.
Focusing on 00a, its configuration will be described with reference to FIG. FIG. 12 is an enlarged view schematically showing a configuration of memory cell 100a. The memory cell 100a includes a first memory cell 100ax including a selection transistor 110 and a ferroelectric capacitor 112, and a selection transistor 1
14 and a second memory cell 100ay composed of a ferroelectric capacitor 116. The main current path (channel) of the select transistor 110 and the ferroelectric capacitor 112 correspond to the bit line BL0 and the plate line PL0.
Are connected in series in this order from the bit line BL0 side, and the control electrode (gate electrode) 110x of the selection transistor 110 is connected to the word line WL0.
The main current path of the select transistor 114 and the ferroelectric capacitor 116 are connected to the bit line BL1 and the plate line PL.
0 is connected in series in this order from the bit line BL1 side.
x is connected to the word line WL1. A connection point between the connection transistor 110 and the ferroelectric capacitor 112 is a storage node 118, and a connection point between the selection transistor 114 and the ferroelectric capacitor 116 is a storage node 120.
And Further, the memory cells 100b to 100d of FIG.
Has the same configuration as the memory cell 100a described above.

[0004] Further, as shown in FIG.
Has a floating control line (equalizer) EQ0 and a pair of transistors 122 and 124 for floating control. The main current path of each of these transistors 122 and 124 is directly connected between the bit lines to which the memory cells are connected. For example, first-stage transistors 122 and 124 are connected in series between bit lines BL0 and BL1. Have been. A connection point 126 between these main current paths is connected to a ground terminal 128.
The control electrodes 122x and 124x of the transistors 122 and 124 are connected to the control line EQ0 (FIG. 11).

[0005] Next, referring to FIG.
A method for reading data from the 2C type FeRAM will be described. This data reading is generally performed according to the literature “Low power consumption, high speed LSI technology, pp. 234-23.
6, issued in January 1998, issued by Realize Co., Ltd. " FIG. 13 is a timing chart showing a data read operation in the above-described conventional FeRAM. Note that the symbol “L” in FIG. 13 represents the level of the ground potential (corresponding to the logical level “0”), and the symbol “H” represents the level of the power supply potential (corresponding to the logical level “1”). Is represented. The symbol “HH” indicates a level of a potential higher than the level “H” by the threshold voltage (Vt) of the selection transistors T0 and T1. At the time of reading, the ferroelectric capacitor 112 of the first memory cell 100ax and the second
The ferroelectric capacitor 116 of the memory cell 100ay is polarized in an opposite direction. That is, complementary data is written in each cell.

At time t0, the first and second floating control lines EQ0 are set to level "H".
The bit lines BL0 and BL1 are set to level "L". Further, the first and second word lines WL0 and WL1 are set to level "L", the plate line PL0 is set to level "L", and the sense amplifier activation signal SAE is set to level "L".

In the read operation, first, at time t1, the floating control line EQ0 is set to the level "L", and the bit lines BL0 and BL1 are set to the floating state at the level of "L".

Next, at time t2, word line WL0
And WL1 are respectively applied with voltage VH to open the gates of select transistors 110 and 114. The applied voltage VH is higher than the power supply voltage Vcc by about the threshold voltage Vt of the selection transistors 110 and 114. Note that the word lines WL0 and W
The potential of L1 becomes level "HH" (FIG. 13).

Next, at time t3, the plate line PL
0 is a level “H”. As a result, charges are released from the ferroelectric capacitors 112 and 116, and the released charges appear as read potentials on the bit lines BL0 and BL1. Since the capacitors 112 and 116 have different capacities depending on the polarization directions, the read potentials generated on the bit lines BL0 and BL1 also differ depending on the polarization directions.

Here, it is assumed that the ferroelectric capacitor 112 emits more charges than the ferroelectric capacitor 116. As a result, the read potential generated on the bit line BL0 is higher than the read potential generated on the bit line BL1. This state is shown by a solid line and a broken line in the period from t3 to t4 in FIG.

Next, at time t4, the sense amplifier activating signal SAE is set to the level "H", and the sense amplifier 1
Activate 02. The sense amplifier 102 is connected to the bit line B
A difference ΔV between the read potentials generated in L0 and BL1 is sensed, and the potential difference ΔV is amplified so as to become the power supply voltage Vcc. As a result, here, the bit line BL0 becomes the power supply potential “H”, and the bit line BL1 becomes the ground potential “L”. These potentials are at the logic level “1” after reading.
And "0" respectively.

At this time, word lines WL0 and WL
1 are applied with the voltage VH. Therefore, when the potential of the bit line BL0 is amplified to the power supply potential “H”, no voltage drop occurs, and the potential of the storage node 118 can be set to the level “H”. For this reason, at this time, the potentials on both sides of the ferroelectric capacitor 112 are at the level “H”.
No voltage is applied to 2 and the data at the time of reading is held as it is.

On the other hand, the potential of the bit line BL1 is a ground potential. For this reason, the potential of the storage node 120 becomes the level “L” according to the ground potential. The plate line P
The potential of L0 is at the level “H”. Therefore, the potential on both sides of the ferroelectric capacitor 116 is
The level is at level "L" and the plate line PL0 is at level "H". Therefore, the voltage (Vcc) is applied to the ferroelectric capacitor 116. In this way, rewriting is performed on the ferroelectric capacitor 116.

Next, at time t5, the plate line PL
0 is set to level “L”.

As a result, the potential on both sides of the ferroelectric capacitor 112 becomes the ground potential on the plate line PL0 side and the power supply potential on the storage node 118 side. Therefore, a voltage (Vcc) is applied to the ferroelectric capacitor 112. Thereby, rewriting can be performed on the ferroelectric capacitor 112. At this time, both sides of the ferroelectric capacitor 116 are at the ground potential, so that the ferroelectric capacitor 116 can hold the data rewritten at the time t4 as it is.

Next, at time t6, when the floating control line EQ0 is set to level "H" and the sense amplifier activation signal SAE is set to level "L", the bit lines BL0,
The potentials of BL1 and storage nodes 118 and 120 are all at level "L", that is, the ground potential.

Finally, at time t7, the word line WL
A series of read operation and rewrite operation are completed by setting 0 and WL1 to level “L”.

FIG. 14 is a characteristic diagram showing a hysteresis loop of the ferroelectric capacitor. In the figure, the horizontal axis indicates the voltage V applied to the ferroelectric capacitor, and the vertical axis indicates the polarization P of the ferroelectric capacitor.
In the figure, the remanent polarization states indicated by symbols A and B represent states in which data “1” (logical level) and “0” (logical level) are held, respectively. Also, the symbol a
And b represent the remanent polarization states A and B
, And its slope is determined by the value of the bit line capacitance Cb. The difference V1 between the voltage at the intersection of the load line a and the hysteresis loop and the power supply voltage Vcc is
This corresponds to the bit line potential at the time of reading data “1”. The difference V0 between the voltage at the intersection of the load line b and the hysteresis loop and the power supply voltage Vcc corresponds to the bit line potential (read potential) when data "0" is read. The difference ΔV between these bit line potentials V1 and V0 needs to be equal to or higher than the discrimination sensitivity of the sense amplifier.

[0019]

As described above, in the conventional FeRAM, since a symmetric voltage is applied to the ferroelectric capacitor at the time of rewriting to the ferroelectric capacitor at times t4 and t5. , A voltage VH higher than the power supply voltage Vcc by the threshold voltage Vt of the selection transistor is applied to the word line. Here, the symmetric voltage means that the magnitude of the voltage does not change depending on the application direction of the voltage applied to the ferroelectric capacitor. That is, at t4 or t5, the potential of one bit line is amplified to the power supply potential by the sense amplifier. The potential on the storage node side of the ferroelectric capacitor connected to the bit line can be set to the power supply potential by applying the above-described voltage VH to the word line. Thereby, the voltage applied to the ferroelectric capacitor when the potential on the plate line side is the ground potential,
When the potential on the plate line side of the ferroelectric capacitor is Vcc and the potential on the storage node side is the ground potential, the voltage applied to the ferroelectric capacitor is the same voltage (Vcc), that is, a symmetrical voltage. Can be

A voltage VH higher than the power supply voltage Vcc by about the threshold voltage Vt of the selection transistor with respect to the word line.
Is applied. Of course, this voltage VH must be generated inside the device. for that purpose,
For example, it is common practice to mount a charge pump circuit as used in a DRAM. However, when boosting is performed by a charge pump circuit, it takes a time on the order of microseconds until the voltage becomes stable. Also, the charge pump circuit requires a large current. Although FeRAM is a promising device for application to a non-contact type IC card, a circuit configuration requiring a microsecond time for a setup time or a circuit requiring a large current requires speed and consumption. It can be a fatal drawback in terms of power.

However, the power supply voltage Vcc is applied to the word line.
Is applied, because of the so-called “Vt drop” due to the voltage drop at the select transistor portion,
An asymmetrical voltage as shown in FIG. 15 is applied to the ferroelectric capacitor. That is, as shown in FIG. 15, a voltage of Vcc is applied to the ferroelectric capacitor in one direction, and a voltage of -Vcc + Vt is applied to the other direction. In such a case, imprint, which is a deterioration phenomenon peculiar to the ferroelectric substance, occurs. Imprinting refers to a phenomenon in which a hysteresis loop of a ferroelectric becomes electrically asymmetric due to a constant voltage application to a ferroelectric capacitor. This imprint effect is
This makes the read potential of the eRAM unstable and causes a problem such as erroneous read. In particular, this problem becomes serious at the time of low voltage operation in which the hysteresis loop is small.

Therefore, there has been a demand for a ferroelectric memory in which a symmetrical voltage is applied to a ferroelectric capacitor even when a voltage applied to a word line is used as a power supply voltage. Was.

It is also desirable to provide a method of reading data from a ferroelectric memory in which the difference (ΔV) between bit line potentials V1 and V0 can be made large enough to be easily discriminated by a sense amplifier when reading data. I was

[0024]

Therefore, according to the ferroelectric memory of the present invention, a ferroelectric capacitor and a selection transistor having one end of a main current path connected to one electrode of the ferroelectric capacitor are provided. At least one memory cell, a word line connected to the control electrode of the select transistor, a bit line connected to the other end of the main current path of the select transistor, and the other electrode of the ferroelectric capacitor. A sense amplifier connected to the plate line, the bit line, and a plate line driver for applying a voltage to the plate line; The plate line driver is configured as a voltage generating circuit for selectively generating a first voltage as a power supply voltage and a second voltage lower than the power supply voltage by a threshold voltage of the selection transistor. It is.

Since the plate line driver is configured as described above, a voltage lower than the power supply voltage by the threshold voltage of the selection transistor can be applied to the plate line. Therefore, it is possible to apply a symmetric voltage to the ferroelectric capacitor.

Here, the voltage applied to the ferroelectric capacitor is considered in two application directions. First,
When the power supply voltage is applied to the word line and the bit line is also applied and the plate line is set to the ground potential, the potential on both sides of the ferroelectric capacitor becomes the ground potential on the plate line side and the bit line The voltage on the side becomes lower than the power supply potential (Vcc) by the threshold voltage (Vt) of the selection transistor due to the "fall of Vt". Therefore, a voltage (VL: corresponding to the second voltage) smaller than the power supply voltage by Vt in one direction is applied to the ferroelectric capacitor. Next, when the word line is set to the ground potential, the power supply voltage is applied to the bit line, and the second voltage (VL) is applied to the plate line, the bit line side of the ferroelectric capacitor is set to the ground potential and the plate line side is set. Potential is V from ground potential
The potential becomes higher by L. Therefore, a voltage (VL) in a direction opposite to the above direction is applied to the ferroelectric capacitor. Thus, a voltage (second voltage) smaller than the power supply voltage by the threshold voltage of the selection transistor is applied to the plate line.
, It is possible to apply voltages of the same magnitude to the ferroelectric capacitor from two directions, that is, symmetric voltages. As a result, the imprint of the ferroelectric capacitor can be reduced.

The power supply voltage (Vcc) is a voltage generally used in a ferroelectric memory.

In the ferroelectric memory according to the present invention, it is preferable that the plate line driver is configured as a voltage generating circuit having the following configuration. That is, the voltage generation circuit includes a first voltage supply line for supplying a first voltage, a second voltage supply line for supplying a second voltage, and a first PMO
An S field effect transistor (hereinafter referred to as FET);
A second PMOSFET and a first NMOSFET are provided. And a first PMOSFET, a second PMOSFET
And one end of each main current path of the first NMOSFET is connected to a plate line, and the other end of the main current path of the first PMOSFET is connected to a first voltage supply line.
The other end of the main current path of T is connected to the second voltage supply line, and the other end of the first NMOSFET is connected to the ground potential point.

By using the plate line driver having the voltage generating circuit having such a configuration, the first voltage and the second voltage can be selectively generated on the plate line. 1st P
MOSFET, second PMOSFET and first NMOS
An input terminal for applying a voltage to the gate is connected to each of the FETs.

First, when the first voltage is generated on the plate line, the input terminal of the first PMOSFET is set to the level "L".
, The input terminal of the second PMOSFET is at level "H".
And the input terminal of the first NMOSFET are set to the level “L” potential. Note that the level “H” potential is a power supply potential and the level “L” potential is a ground potential.
As a result, the first voltage is applied to the plate line.

When the second voltage is generated, the first voltage
The input terminal of the PMOSFET is set at the potential of level “H”, the second
The input terminal of the PMOSFET is set to the level "L" and the input terminal of the first NMOSFET is set to the level "L". As a result, the second voltage is applied to the plate line.

If the input terminal of the first PMOSFET is set to the potential of level "H", the input terminal of the second PMOSFET is set to the potential of level "H", and the input terminal of the first NMOSFET is set to the potential of level "H", the plate line Becomes the ground potential.

As described above, the plate line driver which can selectively supply the first voltage and the second voltage to the plate line is a component of the CMOS inverter conventionally used as the plate line driver. This is a simple configuration in which only one PMOS transistor is added as a new component. Moreover, the plate line driver can supply stable first and second voltages to the plate line. Further, in order to supply a voltage to the plate line, it is only necessary to set the input terminals of the three transistors to the potential of the level “H” or the potential of the level “L”, so that the supply timing can be easily set. it can.

In this ferroelectric memory, preferably, the second voltage supply line has the same threshold voltage as that of the selection transistor and is connected to the first voltage supply line via an NMOSFET different from the first NMOSFET. It is preferable to connect to a voltage supply line.

As described above, the first voltage supply line and the second voltage supply line are connected via the NMOS transistor,
By making the threshold voltage of this other NMOSFET the same as the threshold voltage (Vt) of the selection transistor in the memory cell, the second voltage supply line has a voltage Vt more than the first voltage (power supply voltage Vcc). Only a small voltage can be supplied. A voltage lower than the first voltage by Vt corresponds to the second voltage.

In another preferred embodiment of the ferroelectric memory, the plate line driver is preferably configured as a voltage generating circuit having the following components. That is, the voltage generation circuit includes a first voltage supply line for supplying a first voltage, a first PMOSFET, a first NMOSFET having the same threshold voltage as the selection transistor, and a second NMOSFET.
MOSFET. And the first PMOSF
ET, one end of each main current path of the first NMOSFET and the second NMOSFET are connected to a plate line, respectively, and the other end of the main current path of the first PMOSFET and the first NMOS
The other end of the main current path of the FET is connected to the first voltage supply line, and the other end of the second NMOSFET is connected to the ground potential point.
A transistor having a lower current driving capability than a MOSFET is used.

The first voltage and the second voltage can be selectively generated on the plate line by using the plate line driver having the voltage generating circuit having such a configuration. 1st P
MOSFET, first NMOSFET and second NMOS
An input terminal for applying a voltage to the gate is connected to each of the FETs.

First, when the first voltage is generated on the plate line, the input terminal of the first PMOSFET is set to the level "L".
, The input terminal of the first NMOSFET is set to level "L".
And the input terminal of the second NMOSFET are set to the level “L”. As a result, the first voltage is supplied to the plate line.

At this time, the input terminal of the first NMOSFET is set to the level "H" potential instead of the level "L" potential. Here, comparing the PMOSFET and the NMOSFET having the same gate dimensions, the NMOSFET has a higher current driving capability than the PMOSFET. Therefore, when the first voltage is generated, the supply speed of the first voltage to the plate line can be increased by setting the input terminal of the first NMOSFET to the potential of the level “H”.

When the second voltage is generated on the plate line, the input terminal of the first PMOS transistor is connected to the level "H" potential, the input terminal of the first NMOSFET is connected to the level "H" potential, and the input terminal of the second NMOSFET is connected to the input terminal. The potential is set to the level “H”. However, the second NMOSFET
Is set to the level "H" at a time required for the voltage supplied to the plate line to reach the second voltage. The current drive capability of the second NMOSFET is
Since the current driving capability of the first NMOSFET is lower than that of the first NMOSFET, the potential of the plate line does not reach the ground potential even when the second NMOSFET is turned on. Therefore, by making the second NMOSFET conductive for a desired time, a second voltage lower than the first voltage by the threshold voltage of the selection transistor can be supplied to the plate line.

In order to lower the current driving capability of the transistor, for example, a method of structurally increasing the gate length of the transistor, reducing the gate width, or increasing the threshold voltage can be considered. .

If the input terminal of the first PMOSFET is set to the potential of level "H", the input terminal of the first NMOSFET is set to the potential of level "L", and the input terminal of the second NMOSFET is set to the potential of level "H", the plate line The potential becomes the ground potential.

As described above, the plate line driver capable of selectively supplying the first voltage and the second voltage to the plate line is a component of a CMOS inverter conventionally used as a plate line driver. This is a simple configuration in which only one NMOSFET is added as a new component. Moreover, the plate line driver can supply stable first and second voltages to the plate line. Further, in order to supply a voltage to the plate line, it is only necessary to set the input terminals of the three transistors to the potential of the level “H” or the potential of the level “L”, so that the supply timing can be easily set. it can.

In such a ferroelectric memory, preferably, the threshold voltage of the selection transistor is a transistor in the ferroelectric memory and in a peripheral circuit of a memory cell, that is, for a peripheral circuit configuration. It is preferable to use a transistor whose threshold voltage is lower than that of the transistor.

The peripheral circuit refers to, for example, a decoder circuit or a control circuit for selecting a bit line or a plate line.
This peripheral circuit usually includes a transistor as a component. By making the threshold voltage of the selection transistor lower than the threshold voltage of the transistor for forming a peripheral circuit, a read margin in data reading can be increased.

Further, the threshold voltage of the transistor in the peripheral circuit cannot be easily reduced because there is a possibility that the leakage current increases. On the other hand, a transistor having a small threshold voltage can be used as a selection transistor in a memory cell because all the wirings connected to the selection transistor are at the ground potential during standby of the memory cell. Therefore, there is no possibility that an off-leak current is generated from the selection transistor.

In the ferroelectric memory having the above-described configuration, preferably, at the time of data reading, the voltage generating circuit first generates the first voltage and then generates the second voltage. By generating the first voltage and the second voltage on the plate line in this order, the read margin of the read potential generated on the bit line can be increased. Further, at the time of rewriting to the ferroelectric capacitor, a symmetric voltage can be applied to the ferroelectric capacitor.

According to the data reading method of the present invention, at least one memory cell having a ferroelectric capacitor and a selection transistor is connected to the memory cell for writing and reading the memory cell. Reading data from a memory cell for which a write operation has been completed from a ferroelectric memory including a word line, a bit line, a plate line, and a sense amplifier connected to the bit line, including the following steps: It is characterized by.

After grounding the bit line, a step of electrically floating the bit line.

Next, a step of applying a power supply voltage to the word lines.

Next, a step of applying a first voltage as a power supply voltage to the plate line.

Next, a step of applying a second voltage, which is a voltage lower than the first voltage by the threshold voltage of the selection transistor, to the plate line.

Next, a step of activating the sense amplifier.

Next, a step of grounding the plate line.

Consider a method of reading data from one memory cell after the write operation has been completed. In the process,
After grounding the bit line connected to the memory cell,
Float electrically. As a result, the bit line floats at the ground potential. Next, in a step, a power supply voltage (Vcc) is applied to a word line connected to the gate of the selection transistor of the memory cell. Thus, the selection transistor is turned on. Next, in the process, a power supply voltage (Vcc) is applied to the plate line. As a result, charge is released from the ferroelectric capacitor of the memory cell, and a potential (read potential) corresponding to the charge amount is generated on the bit line. In addition, the amount of charge released from the ferroelectric capacitor differs depending on the data written by the write operation, that is, the polarization direction. Next, in the step, in the reading method of the present invention, a voltage (VL) lower than the power supply voltage (Vcc) by the threshold voltage (Vt) of the selection transistor is applied to the plate line. Accordingly, the read potential changes.

Here, in the case of a 2T2C type ferroelectric memory, first, a read potential from two ferroelectric capacitors to which contradictory data is written is connected to a bit line connected to each ferroelectric capacitor. Occurs. The determination of the written data is made using the difference between the two generated read potentials. When a voltage that changes from Vcc to VL is applied to the plate line from step to step, the difference in read potential can be made larger than when only VL is applied to the plate line. This is due to the characteristics of the ferroelectric.

Therefore, in the 2T2C type ferroelectric memory, the difference in read potential, that is, the read margin can be made larger than in the case where VL is simply applied at the time of read.

In the case of a 1T1C type ferroelectric memory, a memory cell including one ferroelectric capacitor and one selection transistor is provided. The data written in the memory cell can take two kinds of values according to the polarization direction of the ferroelectric capacitor. Therefore, there are two kinds of potential values generated in the bit line at the time of reading. The 1T1C ferroelectric memory is provided with a reference cell for generating an intermediate potential between the above two potentials. Therefore, reading of written data is performed by comparing the read potential generated in the bit line with the output potential from the reference cell by the sense amplifier.

In the case of a 1T1C type ferroelectric memory, data written in the ferroelectric capacitor, that is, two polarization directions of the ferroelectric capacitor can be considered. The difference between the output potential from the reference cell and the read potential can be increased.

Thereafter, in a step, the sense amplifier is activated. In the case of a 2T2C type ferroelectric memory, two bit lines are connected to a sense amplifier. Then, the sense amplifier senses the difference between the read potentials generated on the two bit lines, and recognizes the difference as the power supply voltage (Vcc).
Amplify up to. Therefore, one bit line (bit line A
And Is the power supply potential, and the potential of the other bit line (bit line B) is the ground potential. At this time, a rewriting operation is performed on the ferroelectric capacitor connected to the bit line B. The bit line side of this ferroelectric capacitor is at the ground potential. The potential on the plate line side is VL. Therefore, the voltage VL is applied to the ferroelectric capacitor, and as a result, rewriting is performed. On the other hand, the potential on both sides of the ferroelectric capacitor connected to the bit line A has a potential of VL on the plate line side, and the potential on the bit line side is lower than Vcc due to Vt drop caused by the selection transistor. V
The potential becomes a voltage VL smaller by t. Therefore,
No voltage is applied to the ferroelectric capacitor, that is, the data is held in a state where data is destroyed by the read operation.

Thereafter, in the process, the plate wire is grounded. Thus, the potential on both sides of the ferroelectric capacitor connected to the bit line A becomes the ground potential on the plate line side, and becomes VL on the bit line side. Thereby, the voltage VL is applied to the ferroelectric capacitor, and the rewriting is performed. Note that the direction of application of the voltage to the ferroelectric capacitor connected to the bit line A is the same as that of the voltage applied during rewriting to the ferroelectric capacitor connected to the bit line B in the above process. The direction is just opposite to the direction. At this time, since the potential on both sides of the ferroelectric capacitor connected to the bit line B is the ground potential, no voltage is applied to this ferroelectric capacitor, and as a result, rewriting is performed in the process. State is maintained.

As described above, the power supply voltage (Vc
By applying a voltage (VL) smaller than c) by the threshold voltage (Vt) of the selection transistor, two ferroelectric capacitors can be rewritten at the time of rewriting to two ferroelectric capacitors having the same hysteresis characteristics. The voltage VL of the same magnitude can be applied to the capacitor in different directions. As a result, the imprint of the ferroelectric capacitor can be reduced.

The rewriting operation of the 1T1C ferroelectric memory is the same as that of the 2T2C type ferroelectric memory. In the process, by activating the sense amplifier, the potential difference between the read potential generated on the bit line and the output potential from the reference cell is amplified to the power supply voltage (Vcc). When the potential of the bit line becomes the power supply potential (Vcc), the potential on both sides of the ferroelectric capacitor becomes a potential having the magnitude of VL, so that no voltage is applied to the ferroelectric capacitor, and thus the data is not applied. Is kept destroyed. Thereafter, in the process, the plate line is grounded, so that the potential on the plate line side of the ferroelectric capacitor becomes the ground potential, and the potential on the bit line side becomes the VL potential. Done.

When the read potential generated on the bit line becomes the ground potential, on both sides of the ferroelectric capacitor, the plate line side becomes the VL potential, and as a result, the bit line side becomes the ground potential. Therefore, the voltage VL is applied to the ferroelectric capacitor, and rewriting is performed.

As a result, although the application direction of the voltage applied to the ferroelectric capacitor at the time of rewriting differs depending on the read potential generated on each bit line, the same voltage VL can be applied to all. That is, a symmetric voltage can be applied to the ferroelectric capacitor. Therefore, the imprint of the ferroelectric capacitor can be reduced.

[0066]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In addition, each drawing merely schematically shows connection relations and the like to an extent that the invention can be understood,
Therefore, the present invention is not limited to the illustrated example.

<First Embodiment> FIG. 1 is a circuit diagram showing a configuration of a ferroelectric memory (FeRAM) according to this embodiment. FIG. 1 shows one memory cell in a memory cell array, which is a configuration of a main part of the FeRAM, and a configuration around the memory cell.

The FeRAM shown in FIG. 1 is a 2T2C type ferroelectric memory. The ferroelectric memory includes first and second memory cells 16 and 22. The first memory cell 16 includes a first ferroelectric capacitor 12 and a first selection transistor 14 having one end 14 a of a main current path connected to one electrode 12 a of the first ferroelectric capacitor 12.
With The second memory cell 22 includes a second ferroelectric capacitor 18 and a second selection transistor 20 having one end 20a of a main current path connected to one electrode 18a of the second ferroelectric capacitor 18. . These first
And second memory cells 16 and 22 constitute one memory cell 10. The connection point between the first ferroelectric capacitor 12 and the second main electrode of the first selection transistor 14 is defined as a first storage node 24, and the second ferroelectric capacitor 18 and the first main electrode of the second selection transistor 20 are connected to each other. Is a second storage node 26. Further, a first word line WL1 is connected to the control electrode 14x of the first selection transistor 14, and the second selection transistor 2
The second word line WL2 is connected to the 0 control electrode 20x. Further, the first bit line BL1 is connected to the other end (first main electrode) 14b of the main current path of the first selection transistor 14, and the other end (second main electrode) of the main current path of the second selection transistor 20 ) The second bit line BL2 is connected to 20b. Further, a sense amplifier 28 is connected to the first bit line BL1 and the second bit line BL2, and the sense amplifier 28 operates according to a sense amplifier activation signal SAE input thereto from outside. Further, a plate line PL1 is connected to the other electrode 12b of the first ferroelectric capacitor 12 and the other electrode 18b of the second ferroelectric capacitor 18.

The plate line driver 30 is connected to the plate line PL1. In this embodiment, the plate line driver 30 sets the first voltage as the power supply voltage (Vcc) and a voltage lower than the power supply voltage by the threshold voltage (Vt) of the first and second selection transistors 14 and 20. Is configured as a driver for selectively generating the second voltage with respect to the plate line PL1, that is, a voltage generation circuit.

The FeRAM has a floating control line EQ1 and a floating control transistor 32,
34. The main current paths of these transistors 32 and 34 are connected in series between the first bit line BL1 and the second bit line BL2. A connection point 36 between these main current paths is connected to a ground terminal 38. Then, the control electrodes 32x, 34 of the transistors 32, 34
x are connected to the control line EQ1.

Next, the operation of reading data from the FeRAM of this embodiment will be described with reference to FIG.
FIG. 2 is a timing chart showing a data read operation in the FeRAM according to the embodiment. The symbol “L” in FIG. 2 represents the level of the ground potential (corresponding to the logic level “0”), and the symbol “H” represents the level of the power supply potential (corresponding to the logic level “1”). . The symbol "M" indicates a potential level lower than the power supply potential by the threshold voltage (Vt) of the first and second selection transistors. Since the level “L” is the ground potential, the potential difference between the level “H” and the level “L” corresponds to the power supply voltage (Vcc, the first voltage). The potential difference between the level "M" and the level "L" is equal to the power supply voltage (Vcc).
This corresponds to a voltage (VL, second voltage) smaller by the threshold voltage (Vt) of the first and second selection transistors.

In this FeRAM, it is assumed that complementary data has already been written in the first memory cell 16 and the second memory cell 22. Then, at time t0,
By setting the floating control line EQ1 to the level “H”, the first and second bit lines BL1 and BL2 are set to the level “L”. Further, the first and second word lines W
L1 and WL2 are at level "L", plate line PL1 is at level "L", and sense amplifier activation signal SAE is at level "L".

In the read operation, first, at time t1,
By setting the floating control line to the level “L”, the first and second bit lines are set to the floating state at the potential of the level “L”.

Next, at time t2, the first word line W
L1 and the second word line WL2 are set to level “H”, respectively.
To Thereby, the first selection transistor 14 and the second selection transistor 20 are turned on.

Next, at time t3, the plate line driver 30 is activated, and the power supply voltage (V
cc, a first voltage). As a result, a potential corresponding to the polarization direction of the first ferroelectric capacitor 12 is generated on the first bit line BL1. Similarly, the second bit line BL2
A potential corresponding to the polarization direction of the second ferroelectric capacitor 18 is generated. Since the FeRAM of this embodiment is of the 2T2C type, complementary data is written in the first memory cell 16 and the second memory cell 22.
That is, the polarization directions of the first ferroelectric capacitor 12 and the second ferroelectric capacitor 18 are opposite. In this embodiment, as shown in FIG. 2, the potential of the first bit line BL2 is higher than the potential (indicated by a solid line in FIG. 2).
A data reading method when the potential (indicated by a broken line in FIG. 2) generated on the bit line BL1 is higher will be described.

Next, at time t4, a second voltage (VL) is applied from the plate line driver 30 to the plate line PL1. As a result, the first and second bit lines BL1, BL1,
The potential generated at BL2 changes.

Here, referring to FIG. 3, the first and second bit lines are applied by applying a first voltage to plate line PL1 at time t3 and then applying a second voltage to plate line PL1 at time t4. A change in the potential (read potential) of BL1 and BL2 will be described. FIG. 3 is a hysteresis characteristic curve diagram of the first and second ferroelectric capacitors. In FIG. 3, the horizontal axis indicates the voltage (V) applied to the ferroelectric capacitors 12 and 18, and the vertical axis indicates the polarization (μC / cm ² ) of the ferroelectric. The first ferroelectric capacitor 12 and the second ferroelectric capacitor 1
8 have substantially the same hysteresis characteristics. Therefore, description will be made with reference to the same characteristic diagram (FIG. 3). FIG.
In the middle, the remanent polarization states indicated by A and B represent states in which data “1” (logical level) and “0” (logical level) are held, respectively. Also, the symbols a ₁ ,
Line segments represented by a ₂ , b _1, and b ₂ indicate load lines corresponding to each remanent polarization state, and the slope is determined by the value of the bit line capacitance Cb.

First, at time t3, the plate line PL
1 when the power supply voltage Vcc is applied to the first bit line BL
1 is a load line (shown by a broken line) a _{1 in the} figure.
And a hysteresis characteristic curve (also referred to as a hysteresis loop), and corresponds to a difference Va1 between the power supply voltage Vcc and the voltage at the intersection. The potential generated on the second bit line BL2 at the time t3 is the load line b ₁ (shown by a broken line).
And a hysteresis loop, and corresponds to a difference Vb1 between the power supply voltage Vcc and the voltage at the intersection of the power supply voltage Vcc.

Thereafter, when the second voltage (VL) is applied to the plate line PL1 at time t4, the potentials generated on the first bit line BL1 and the second bit line BL2 change. First
Potential generated on the bit line BL1 should be the difference between the voltage and the voltage VL at the intersection of the load line a ₂ (indicated by a solid line) and the hysteresis loop. However, the first ferroelectric capacitor tries to maintain the polarization direction at time t3. Therefore, the potential generated in the first bit line BL1 becomes the voltage at the intersection between the curve R which are newly formed inside the load line a ₂ and the hysteresis loop, the difference Va2 of the voltage VL. Also, the voltage at the intersection of the load line b ₂ (shown by a solid line) and the hysteresis loop and the power supply voltage VL
Vb2 corresponds to the potential of the second bit line BL2 at time t4. Therefore, the potential difference between the first bit line BL1 and the second bit line BL2 determined by the sense amplifier 28 is the difference ΔV between Va2 and Vb2.

FIG. 3 shows potentials generated on the first bit line BL1 and the second bit line BL2 when only the second voltage (VL) is applied to the plate line PL1. Potential generated in the first bit line BL1, corresponds to the difference Vax between the voltage and the voltage VL at the intersection of the load line a ₂ and a hysteresis loop. Also, the second bit line B
Potential generated in L2 corresponds to the difference Vbx between the voltage and the voltage VL at the intersection of the load line b ₂ and the hysteresis loop. Thus, the potential difference between the potential of the first bit line BL1 and the potential of the second bit line BL2 becomes ΔVx.

As a result, as shown in FIG. 3, ΔV becomes larger than ΔVx. These ΔVx and ΔV
Is a read margin determined by the sense amplifier 28. Therefore, when the power supply voltage (first voltage) is applied to the plate line PL1 and then the VL (second voltage) is applied during the read operation, the read margin is higher than when only the second voltage is applied to the plate line PL1. Can be increased. This is due to the above-mentioned characteristic of the ferroelectric capacitor in which the polarization direction is to be maintained.

Referring now to FIG. 4, the dependence of the difference (read margin) between the read potentials generated on the first bit line BL1 and the second bit line BL2 on the bit line capacitance will be examined. FIG. 4 shows a case where the power supply voltage Vcc is 3.3 V,
FIG. 11 is a diagram illustrating a bit line capacitance dependence characteristic of a difference between read potentials in a ferroelectric memory in which the threshold voltage (Vt) of the first and second selection transistors 14 and 20 is 0.8 V. In FIG. 4, the horizontal axis represents the bit line capacitance Cb (pF), and the vertical axis represents the first bit line BL1 and the second bit line BL.
2, the potential difference (V) is shown. Further, the capacitances of the first bit line BL1 and the second bit line BL2 are assumed to be the same. When changing to an arbitrary bit line capacitance Cb from 0 to 2.0 × 10 ^{-1 2} pF, Vcc to the plate line PL1
After applying (3.3 V), VL (2.5 V) is applied. Thus, the potential difference ΔV generated in the bit line is compared with the potential difference ΔVx generated by applying only VL (2.5 V) to the plate line PL1. In FIG. 4, curve I is Δ
V, and curve II shows the change in ΔVx.
According to FIG. 4, the bit line capacitance Cb ranges from 0 to 2..
In the range of 0 × 10 ⁻¹² pF, ΔV is larger than ΔVx. That is, the read margin is large.

Next, at time t5, the sense amplifier activating signal SAE is set to the level “H”, and the sense amplifier 2
Activate 8 The sense amplifier 28 is connected to the first bit line B
L1 and the potential difference between the second bit line BL2 (Δ
V), the difference is amplified to the power supply voltage (Vcc). Thereby, the potential of the first bit line BL1 (FIG. 2)
Shown by broken lines inside. ) Is the power supply potential and the second bit line B
The potential of L2 (shown by a solid line in FIG. 2) is the ground potential. At this time, in the first memory cell 16, the potential on the plate line PL1 side of the first ferroelectric capacitor 12 is at the level “M”. Further, the potential on the first storage node 24 side also becomes level “M”. This is because when the potential of the first bit line BL1 becomes the power supply potential, the first storage node 24 and the first storage node 24
Since the first selection transistor 14 is interposed between the bit line BL1 and the bit line BL1, a "Vt drop" occurs at the first selection transistor 14. Thereby, the first storage node 24
Is at the potential level "M" lower than the level "H" by the voltage Vt. Therefore, since both sides of the first ferroelectric capacitor 12 have the same potential, no voltage is applied to the first ferroelectric capacitor 12. In the second memory cell 22, the potential on the plate line PL1 side of the second ferroelectric capacitor 18 is at level "M". Then, the potential of the second storage node 26 becomes the level “L” because the potential of the second bit line BL2 is the ground potential. Therefore, the second ferroelectric capacitor 18
Is applied with a voltage VL. This means that rewriting has been performed on the second ferroelectric capacitor 18.

Next, at time t6, the plate line PL
1 is set to the level “L” (FIG. 2). As a result, in the first memory cell 16, the potential on the plate line PL1 side of the first ferroelectric capacitor 12 becomes the level “L”, and the first
The potential on the storage node 24 side remains at the level “M”.
Therefore, the voltage VL is applied to the first ferroelectric capacitor 12, and rewriting is performed. In the second memory cell 22, the plate line P of the second ferroelectric
Both the potential on the L1 side and the potential on the second storage node 26 are at level "L". Therefore, no voltage is applied to the second ferroelectric capacitor 18, and the state in which rewriting has been performed at time t5 is maintained.

Therefore, it is possible to apply the same voltage VL to the first ferroelectric capacitor 12 and the second ferroelectric capacitor 18 at the time of rewriting. Also, the first and second ferroelectric capacitors 12, 1
In the case where data opposite to the above is written in 8, the data is read out in the same manner as described above, so that both ferroelectric capacitors 12,
18 can be applied with the voltage VL. This makes it possible to apply a symmetrical voltage to the ferroelectric capacitor. As a result, the imprint of the ferroelectric capacitor can be reduced.

Next, at time t7, when the floating control line EQ1 is set to the level “H” and the sense amplifier activation signal SAE is set to the level “L”, the first bit line BL1, the second bit line BL2, The potentials of the first storage node 24 and the second storage node 26 are all at the level “L”.

Finally, at time t8, the read operation is completed by setting the first word line WL1 and the second word line WL2 to level "L".

<Second Embodiment> FIG. 5 is a circuit diagram showing a configuration of a ferroelectric memory according to a second embodiment. FIG. 5 shows a memory cell array 50 having many memory cells shown in FIG. 1 and a peripheral circuit section 52. The peripheral circuit section 52 includes a decoder circuit and a control circuit for selecting a bit line or a plate line. Usually, these circuits include necessary transistors for peripheral circuit configuration. The FeRAM has a plurality of word lines WL1 to WL4 and a plurality of plate lines PL1 and PL1.
2 and a plurality of bit lines BL1 to BL4. However, the number of each line is not limited to this. A plurality of memory cells similar to the memory cell 10 shown in FIG. 1 are connected to these lines.

In this embodiment, the memory cell array 5
0, the threshold voltage of the selection transistor in the peripheral circuit unit 52, for example, N
The transistor is set to be lower than the threshold voltage of the MOSFET.

For example, here, the power supply voltage Vcc is set to 3.
The threshold voltage of the NMOS transistor in the peripheral circuit unit 52 is set to 0.8 V, and the threshold voltage of the selection transistor is set to 0.3 V.

Then, in the same manner as in the first embodiment, the memory cells 10 in which data has been written are stored at times t0 to t.
4 is performed to generate a read potential on the first bit line BL1 and the second bit line BL2.

Here, the first and second bit lines BL1, BL1,
By changing the capacitance Cb of BL2 within the range of 0 to 2.0 × 10 ⁻¹² pF, a difference (read margin) between read potentials generated on the first bit line BL1 and the second bit line BL ″ is measured. As a result, a bit line capacitance dependence characteristic diagram of the read margin as shown in FIG. 6 is obtained.
Is shown with the bit line capacitance Cb (pF) on the horizontal axis and the potential difference (V) between the first bit line BL1 and the second bit line BL2 on the vertical axis. Also, the first bit line BL1
And the capacity of the second bit line BL2 is the same. In FIG. 6, a curve III shows a change curve of the read margin ΔVv of this embodiment, and a curve IV shows a change curve of the read margin ΔV of the first embodiment. As shown in FIG. 6, the bit line capacitance Cb is 0 to 2.0.
In the range of × 10 ⁻¹² pF, ΔVv is larger than ΔV. Therefore, it is possible to further increase the read margin by reducing the threshold voltage of the select transistor of the memory cell 10.

When the threshold voltage of the selection transistor is reduced, the second voltage (V) applied to the plate line at time t4
L) can be increased. That is, the second voltage can be made closer to the power supply voltage. Therefore, the second voltage applied to the ferroelectric capacitor is higher than in the first embodiment, so that the difference between the read potentials generated on the first bit line BL1 and the second bit line BL2 can be increased. .

The NMOSFET in the peripheral circuit section 52
Cannot be easily reduced. This is because off-leak current may increase due to a decrease in threshold voltage. On the other hand, with respect to the selection transistor in the memory cell, all the wirings connected to the selection transistor are at the ground potential at the time of standby and at the end of use of the selection transistor, so that there is no concern that an off-leak current occurs.

To lower the threshold voltage of the select transistor, an ion implantation step for controlling the threshold voltage may be added, for example, when the select transistor is manufactured.

[0096]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, the structure of a plate line driver used in a ferroelectric memory of the present invention will be described.
A description will be given with some configuration examples. It should be noted that the drawings only schematically show connection relations and the like to the extent that the present invention can be understood. Therefore, the present invention is not limited to the illustrated example.

<Embodiment 1> FIG. 7 is a circuit diagram showing a configuration of a plate line driver 30 of Embodiment 1. The plate line driver 30 is a voltage generation circuit, and has a power supply voltage (Vc
c) the threshold voltage (V) of the first and second select transistors 14 and 20 over the first voltage and the power supply voltage.
The configuration is such that the second voltage which is a voltage (VL) smaller by t) is selectively generated on the plate line PL1.

According to the configuration shown in FIG. 7, the first voltage supply line 60 for supplying the first voltage, the second voltage supply line 62 for supplying the second voltage, the first PMOSFET 64, and the second PM
An OSFET 66 and a first NMOSFET 68 are provided. And a first PMOSFET 64 and a second PMOS
One end 64a (second main electrode), 66a (second main electrode) of each main current path of the FET 66 and the first NMOSFET 68,
68a (first main electrodes) are connected to the respective plate lines PL1. The other end (first main electrode) 64 b of the main current path of the first PMOSFET 64 is connected to the first voltage supply line 60.
It is connected to the. Also, the second PMOS transistor 6
The other end (first main electrode) 66 b of the main current path 6 is connected to the second voltage supply line 62. Also, the first NMOSFET
The other end (second main electrode) 68 b of the main current path 68 is connected to the ground potential point 70. Each of the transistors 64, 66, and 68 has an input terminal IP1, IP2, IN for applying a voltage to a control electrode, that is, a gate electrode.
1 is connected.

FIG. 8 is a timing chart when a read operation from a memory cell is performed using such a plate line driver 30. FIG. 8 shows input terminals IP1, IP2, I2 of transistors 64, 66, 68, respectively.
The timing of applying a voltage to N1 is shown together with the potential change of the plate line PL1 in the timing chart shown in FIG. 2 in the first embodiment. The relationship among the symbols H, L, and M in FIG. 8 is the same as that described with reference to FIG. 2, and a detailed description thereof will be omitted.

At time t0, a power supply voltage is applied to the input terminal IP1 of the first PMOS transistor 64, the input terminal IP2 of the second PMOS transistor 66, and the input terminal IN1 of the first NMOS transistor 68 such that the potentials are at the level "H". Apply it. As a result, the plate line PL1 becomes the ground potential level “L”.

Next, at time t3, the plate line PL
1 is applied with a power supply voltage (Vcc). For this purpose,
In this example, the input terminal IP1 of the first PMOSFET 64
To the level “L”. Also, the first NMOSFET 68
Of the input terminal IN1 is at the level “L”. This allows
The first PMOSFET 64 is turned on, and the power supply voltage (Vcc) is supplied from the first voltage supply line 60 to the plate line PL1 through the first PMOSFET 64 (FIG. 7).
Therefore, the potential of plate line PL1 attains level "H" (FIG. 8).

Next, at time t4, the plate line PL
1 is applied with a second voltage (VL). To achieve this purpose, in this example, the input terminal IP1 of the first PMOSFET 64 is set to the level “H”. Also, the second PMOSFE
The input terminal IP2 of T66 is set to level “L”. Also,
The input terminal IN1 of the first NMOSFET 68 is kept at the level “L”. Thereby, the first PMOSF
The ET 64 becomes non-conductive, and the second PMOSFET 66
Becomes conductive. Therefore, the second voltage supply line 62 passes through the second PMOSFET 66 to the plate line PL1,
The voltage (VL) is supplied (FIG. 7). Therefore, the potential of plate line PL1 attains level "M" (FIG. 8).

Thereafter, at time t6 when rewriting the ferroelectric capacitor, the potential of the plate line PL1 is set to the level "L". In order to achieve this object, in this example, the input terminal IP1 of the first PMOSFET 64 is kept at the level “H”, the input terminal IP2 of the second PMOSFET 66 is set at the level “H”, and the first NMOSFET 6
8 input terminal IN1 is at level “H”. Thereby, the first and second PMOSFETs 64 and 66 are turned off. Then, the first NMOSFET 68 is turned on. Therefore, the plate line PL1 is connected to the first NMOSF
Since it is connected to the ground potential point 70 via the ET 68, the potential is at the level "L" (see FIGS. 7 and 8).

As described above, by using the plate line driver 30 described in this embodiment, the first voltage (Vcc) and the second voltage (VL) can be selectively applied to the plate line PL1. Therefore, as described in the first embodiment, it is possible to apply voltages of different directions and of the same magnitude to the ferroelectric capacitors of the memory cells. Thereby, the imprint of the ferroelectric capacitor can be reduced. The plate line P
By applying the second voltage after applying the first voltage to L1, the first bit line BL1 and the second bit line BL1
2 (read margin) can be increased. Therefore, sense amplifier 2
8 can more easily determine the potential difference.

The above-described plate line driver 30
Is a CM that was conventionally used as a plate line driver
As a new component to the components of the OS inverter, P
This is a simple configuration in which only one MOSFET is added. Moreover, stable first and second voltages can be supplied to the plate line PL1 by the plate line driver 30. In order to supply a voltage to the plate line PL1, the input terminals of the three transistors are connected
Since only the potential of the level “H” or the level “L” is required, the supply timing can be easily set.

The second voltage supply line 62 is connected to the first voltage supply line 60 via, for example, an NMOS transistor having the same threshold voltage as the selection transistor and different from the first NMOSFET (not shown). Zu). This causes a voltage drop by the threshold voltage of the NMOS transistor, so that a voltage VL (second voltage) smaller than Vcc by the threshold voltage Vt is supplied to the second voltage supply line. Therefore, the second voltage can be supplied from the second voltage supply line.

Second Embodiment FIG. 9 is a circuit diagram showing a configuration of a plate line driver 30 according to a second embodiment.

Hereinafter, points different from the first embodiment will be described, and detailed description of the same points as the first embodiment will be omitted.

According to FIG. 9, a first voltage supply line 72 for supplying a first voltage, a first PMOSFET 74, a first NMOSFET 76 having the same threshold voltage as a selection transistor in a memory cell, and a second NMOSFET 78 are provided. I have. Then, the first PMOSFET 74 and the first N
One end 74a (second main electrode), 76a (second main electrode) and 78a (first main electrode) of each main current path of MOSFET 76 and second NMOSFET 78 are connected to plate line P, respectively.
L1. Also, the first PMOSFET 74
The other end (first main electrode) 74b of the main current path and the first NM
The other end (first main electrode) 76b of the main current path of the OSFET 76
Are connected to the first voltage supply line 72, respectively. The other end (second main electrode) 78 b of the main current path of the second NMOSFET 78 is connected to the ground potential point 80. Further, the second NMOS transistor 78 is a transistor having a lower current driving capability than the first NMOS transistor 76. The transistors 74, 76, 7
8 has an input terminal I for applying a voltage to the gate electrode.
P1, IN1, and IN2 are connected. FIG. 10 shows a timing chart when a read operation from a memory cell is performed using such a plate line driver 30. FIG. 10 shows each of the transistors 74, 76, 7
8 shows the timing of applying a voltage to the input terminals IP1, IN1, and IN2, and also shows the potential change of the plate line PL1 in the timing chart shown in FIG.

At time t0, the first PMOSFET 7
4 input terminal IP1 to the level “H”, and the first NMOS
The input terminal IN1 of the FET 76 is set to the level “L”, and the second
The input terminal IN2 of the NMOSFET 78 is set to the level “H”. As a result, the potential of the plate line PL1 is at the level "L".

Next, at time t3, the plate line PL
1 is applied with a power supply voltage (Vcc). For this purpose,
In this example, the input terminal IP1 of the first PMOSFET 74
To the level “L”. Also, the second NMOSFET 78
Input terminal IN2 is set to level “L”. As a result, the first PMOSFET 74 becomes conductive, and the power supply voltage (Vcc) is supplied from the first voltage supply line 72 to the plate line PL1 through the first PMOSFET 74 (FIG. 9). In this example, at this time, the input terminal IN1 of the first NMOSFET 76 is further set to the level “H”. Here, PMOSFET and NMOSFET having the same gate size have N
It is known that a MOSFET has a higher current driving capability. Therefore, at time t3, the first NMOSFE
T76 is also made conductive so that the plate line PL
1 can be quickly raised to the power supply potential.

Next, at time t4, the plate line PL
1 is applied with a second voltage (VL) (FIG. 10). For this purpose, in this embodiment, the input terminal IP1 of the first PMOSFET 74 is set to the level “H” and the first NMOS FE
The input terminal IN1 of T76 is kept at the level “H”.
Further, the input terminal IN2 of the second NMOSFET 78 is set to the level “H” for an arbitrary time. This arbitrary time depends on the characteristics of the transistor.
Is a time required until the potential of the signal reaches the level “M”.
The current driving capability of the second NMOSFET 78 is the first NMO
It is lower than the current driving capability of the SFET 76. Therefore, even when the second NMOSFET 78 is turned on, the potential of the plate line PL1 does not go to the level “L”. Therefore, the potential of the plate line PL1 drops from the level “H” by the threshold voltage (Vt) of the first NMOSFET 76, and settles at the level “M”.
Thereby, the potential of the plate line PL1 can be set to the level “M”, that is, the second voltage can be applied to the plate line PL1.

Thereafter, at time t6, plate line P
The potential of L1 is set to level “L”. For this purpose, in this example, the input terminal IP1 of the first PMOSFET 74 is kept at the level “H”, the input terminal IN1 of the first NMOSFET 76 is set at the level “L”, and the second NMOSFET
The input terminal IN2 at 78 is set to level “H”. Thereby, the first PMOSFET 74 and the first NMOSFET
Reference numeral 76 turns off. And the second NMOSFET
Reference numeral 78 indicates a conductive state. Therefore, the plate line PL1
Is connected to the ground potential point 80 via the second NMOSFET 78, so that the potential is at the level “L”.

As described above, by using the plate line driver 30 described in this embodiment, the first voltage (Vcc) and the second voltage (VL) can be selectively applied to the plate line PL1. Therefore, as described in the first embodiment, it is possible to apply voltages of different directions and of the same magnitude to the ferroelectric capacitors of the memory cells. Thereby, the imprint of the ferroelectric capacitor can be reduced. The plate line P
By applying the second voltage after applying the first voltage to L1, the first bit line BL1 and the second bit line BL1
2 (read margin) can be increased. Therefore, sense amplifier 2
8 can more easily determine the potential difference.

Also, the plate line driver 30 described above is used.
Is a CM that was conventionally used as a plate line driver
N as a new component in OS inverter components
This is a simple configuration in which only one MOSFET is added. Moreover, stable first and second voltages can be supplied to the plate line PL1 by the plate line driver 30. In order to supply a voltage to the plate line PL1, the input terminals of the three transistors are connected
Since only the potential of the level “H” or the level “L” is required, the supply timing can be easily set.

In order to lower the current driving capability of the second NMOSFET 78, a method of increasing the gate length of the transistor, reducing the gate width, or increasing the threshold voltage may be employed.

[0117]

As is apparent from the above description, according to the ferroelectric memory of the present invention, a ferroelectric capacitor,
And at least one transistor having a selection transistor having one end of a main current path connected to one electrode of a ferroelectric capacitor.
One memory cell, a word line connected to the control electrode of the select transistor, a bit line connected to the other end of the main current path of the select transistor, and a plate line connected to the other electrode of the ferroelectric capacitor. , A sense amplifier connected to the bit line, and a plate line driver for applying a voltage to the plate line, wherein the plate line driver has a first voltage as a power supply voltage and a voltage lower than the power supply voltage. The second voltage which is smaller by the threshold voltage
It is configured as a voltage generating circuit for selectively generating a voltage.

As described above, a voltage lower than the power supply voltage by the threshold voltage of the selection transistor can be applied to the plate line. Therefore, it is possible to apply a symmetric voltage to the ferroelectric capacitor. As a result, the imprint of the ferroelectric capacitor can be reduced.

According to the data read method of the present invention, at least one memory cell having a ferroelectric capacitor and a select transistor is connected to the memory cell for writing and reading the memory cell. When reading data from a memory cell for which a write operation has been completed from a ferroelectric memory including a word line, a bit line, a plate line, and a sense amplifier connected to the bit line, the following steps are required. Features.

After grounding the bit line, a step of electrically floating the bit line.

Next, a step of applying a power supply voltage to the word lines.

Next, a step of applying a first voltage as a power supply voltage to the plate line.

Next, a step of applying a second voltage, which is lower than the power supply voltage (first voltage) by the threshold voltage of the selection transistor, to the plate line.

Next, a step of activating the sense amplifier.

Next, a step of grounding the plate line.

A method of reading data from one memory cell after a write operation has been completed will be considered. In the process,
After grounding the bit line connected to the memory cell,
Float electrically. As a result, the bit line floats at the ground potential. Next, in a step, a power supply voltage (Vcc) is applied to a word line connected to the gate of the selection transistor of the memory cell. Thus, the selection transistor is turned on. Next, in the process, a power supply voltage (Vcc) is applied to the plate line. As a result, charge is released from the ferroelectric capacitor of the memory cell, and a potential (read potential) corresponding to the charge amount is generated on the bit line. In addition, the amount of charge released from the ferroelectric capacitor differs depending on data written by the write operation, that is, the polarization direction. Next, in the step, in the reading method of the present invention, a voltage (VL) lower than the power supply voltage (Vcc) by the threshold voltage (Vt) of the selection transistor is applied to the plate line. Accordingly, the read potential changes.

Here, first, in the case of a 2T2C type ferroelectric memory, the read potentials from two ferroelectric capacitors in which contradictory data are written are connected to the bit lines connected to the respective ferroelectric capacitors. Occurs. The determination of the written data is made using the difference between the two generated read potentials. When a voltage that changes from Vcc to VL is applied to the plate line from step to step, the difference in read potential (read margin) can be made larger than when only VL is applied to the plate line. Therefore, the determination by the sense amplifier can be more easily performed.

Also in the case of a 1T1C type ferroelectric memory, the difference between the read potential generated on the bit line and the output potential from the reference cell can be increased, so that the determination by the sense amplifier can be easily performed. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a schematic memory cell configuration diagram for explaining a first embodiment;

FIG. 2 is a timing chart illustrating a data read operation for explaining the first embodiment;

FIG. 3 is a hysteresis characteristic curve diagram for describing the first embodiment.

FIG. 4 is a diagram illustrating a bit line capacitance dependence characteristic of a difference between read potentials for explaining the first embodiment;

FIG. 5 is a circuit diagram schematically illustrating a configuration of a ferroelectric memory according to a second embodiment;

FIG. 6 is a diagram illustrating a bit line capacitance dependence characteristic of a read margin for explanation of a second embodiment;

FIG. 7 is a schematic configuration diagram of a plate line driver according to the first embodiment.

FIG. 8 is a timing chart when data is read by the plate line driver according to the first embodiment.

FIG. 9 is a schematic configuration diagram of a plate line driver according to a second embodiment.

FIG. 10 is a timing chart when data is read by a plate line driver according to the second embodiment.

FIG. 11 is a configuration diagram of a conventional ferroelectric memory.

FIG. 12 is an enlarged view of a memory cell 100a in FIG.

FIG. 13 is a timing chart showing a data read operation of a conventional ferroelectric memory.

FIG. 14 is a diagram illustrating a hysteresis characteristic curve of a ferroelectric capacitor, which is used for describing a conventional technique.

FIG. 15 is a diagram provided for explanation of a problem.

[Explanation of symbols]

10, 100a, 100b, 100c, 100d: memory cell 12: first ferroelectric capacitor 12a: one electrode 12b: other electrode 14: first selection transistor 14a: one end of main current path 14b: other than main current path End 14x, 20x, 110x, 114x: Control electrode 16, 100ax: First memory cell 18: Second ferroelectric capacitor 18a: One electrode 18b: The other electrode 20: Second selection transistor 20a: One end of main current path 20b: the other end of the main current path 22, 100ay: second memory cell 24: first storage node 26: second storage node 28, 102: sense amplifier 30, 104: plate line driver 32, 34, 122, 124: floating Control transistors 32x, 34x, 122x, 124x: control electrodes 36, 126: contact Connection points 38, 128: ground terminal 50: memory cell array 52: peripheral circuit section 60, 72: first voltage supply line 62: second voltage supply line 64, 74: first PMOS transistor 64a, 66a, 68a, 74a, 76a, 78a: One end of the main current path 64b, 66b, 68b, 74b, 76b, 78b: The other end of the main current path 66: Second PMOS transistor 68, 76: First NMOS transistor 70, 80: Ground potential point 78: Second NMOS transistor 110 , 114: selection transistor 112, 116: ferroelectric capacitor 118, 120: storage node

Claims (14)

[Claims] At least one memory cell comprising a ferroelectric capacitor and a select transistor having one end of a main current path connected to one electrode of the ferroelectric capacitor, and a select electrode connected to a control electrode of the select transistor A word line, a bit line connected to the other end of the main current path of the select transistor, a plate line connected to the other electrode of the ferroelectric capacitor, and a sense amplifier connected to the bit line. A plate line driver for applying a voltage to the plate line, wherein the plate line driver has a first voltage as a power supply voltage and a voltage lower than the power supply voltage by a threshold voltage of the selection transistor. A ferroelectric memory, wherein the ferroelectric memory is configured as a voltage generation circuit for selectively generating two voltages. 2. The ferroelectric memory according to claim 1, wherein said voltage generation circuit includes a first voltage supply line for supplying said first voltage, and a second voltage supply line for supplying said second voltage. ,
A first PMOS field-effect transistor, a second PMOS field-effect transistor, and a first NMOS field-effect transistor, wherein the first PMOS field-effect transistor and the second PMOS
One end of each main current path of the field-effect transistor and the first NMOS field-effect transistor is connected to the plate line, and the other end of the main current path of the first PMOS field-effect transistor is connected to the first voltage supply line; The second PMOS
The other end of the main current path of the field effect transistor is connected to the second voltage supply line, and the other end of the first NMOS field effect transistor is connected to a ground potential point. 3. The ferroelectric memory according to claim 2, wherein the second voltage supply line is via an NMOS field-effect transistor having the same threshold voltage as the selection transistor and different from the first NMOS transistor. A ferroelectric memory, wherein the ferroelectric memory is connected to the first voltage supply line. 4. The ferroelectric memory according to claim 1, wherein a threshold voltage of said select transistor is within said ferroelectric memory and said memory cell A ferroelectric memory characterized in that the transistor is smaller than the threshold voltage of the transistor for forming a peripheral circuit. 5. The ferroelectric memory according to claim 1, wherein the voltage generation circuit is the same as a first voltage supply line for supplying the first voltage, a first PMOS field effect transistor, and the selection transistor. A first NM having a threshold voltage
An OS field effect transistor and a second NMOS field effect transistor, wherein the first PMOS field effect transistor and the first NMOS
One end of each main current path of the field-effect transistor and the second NMOS field-effect transistor is connected to the plate line, respectively, and the other end of the main current path of the first PMOS field-effect transistor and the main current path of the first NMOS field-effect transistor Are connected to the first voltage supply line, respectively, and the other end of the second NMOS field effect transistor is connected to the ground potential point. The second NMOS field effect transistor is connected to the first N
A ferroelectric memory, wherein the transistor has a lower current driving capability than a MOS field effect transistor. 6. The ferroelectric memory according to claim 1, wherein said select transistor has a threshold voltage within said ferroelectric memory for peripheral circuit configuration of said memory cell. A ferroelectric memory, wherein the transistor is lower than a threshold voltage of the transistor. 7. The ferroelectric memory according to claim 1, wherein at the time of reading data, the voltage generating circuit first generates the first voltage, and then generates the second voltage. Ferroelectric memory. 8. The ferroelectric memory according to claim 1, wherein the ferroelectric memory includes two memory cells in the one memory cell.
A ferroelectric memory comprising a 2T2C type ferroelectric memory including two ferroelectric capacitors and two selection transistors. 9. The ferroelectric memory according to claim 1, wherein said ferroelectric memory includes one of said memory cells.
1. A ferroelectric memory, which is a 1T1C type ferroelectric memory including one ferroelectric capacitor and one selection transistor. 10. A memory cell having at least one memory cell having a ferroelectric capacitor and a selection transistor, and a word line, a bit line, and a plate line respectively connected to the memory cell for writing and reading of the memory cell. When reading data from the memory cell, for which a write operation has been completed, from a ferroelectric memory including a sense amplifier connected to the bit line, first, after grounding the bit line, the bit line is connected. Electrically floating; then, applying a power supply voltage to the word line; then, applying a first voltage as a power supply voltage to the plate line; , The second voltage being lower than the first voltage by the threshold voltage of the selection transistor.
A data reading method, comprising: applying a voltage; next, activating the sense amplifier; and grounding the plate line. 11. A first and a second memory cell each including a ferroelectric capacitor and a select transistor having one end of a main current path connected to one electrode of the ferroelectric capacitor, and a control electrode of the select transistor. First and second word lines respectively connected to the first and second bit lines connected to the other end of the main current path of the selection transistor, and the other electrode of the ferroelectric capacitor, respectively. 2T comprising a connected plate line and a sense amplifier connected to the first and second bit lines
When reading data from the memory cell after the write operation from the 2C type ferroelectric memory, the first and second bit lines are floated at a ground potential, and a power supply is applied to the first and second word lines. In a state where a voltage is applied, first, a first power supply voltage is applied to the plate line.
Applying a voltage, and then applying a second voltage which is lower than a power supply voltage by a threshold voltage of the selection transistor. 12. The data reading method according to claim 11, wherein a difference between potentials generated on the first and second bit lines is detected by applying the second voltage to the plate line. Characteristic data reading method. 13. The data read method according to claim 12, wherein the potential difference is amplified to a power supply voltage. 14. The data read method according to claim 10, wherein, in the step of activating the sense amplifier, the second voltage is applied to the ferroelectric capacitor polarized in one of two directions. Then, in the step of grounding the plate line,
A method of applying the second voltage to the ferroelectric capacitor polarized in the other one of the directions.