JP2006079769A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve information holding without refresh, stable reading operation and low standby power requirement in a semiconductor device using a memory cell consisting of four transistors. <P>SOLUTION: Capacitors C1 and C2 are provided to the storage nodes N1 and N2 of a memory cell MC to carry out rewriting after destructive read in the case of information reading and to hold the potential of the storage nodes N1 and N2 by leakage current flowing through transistors MP1 and MP2 by keeping bit lines BL and /BL to have a fixed potential in the case of information holding. In the case, impedance in the off state of transistors MN1 and MN2 is designated to be larger than the impedance in the off state of transistors MP1 and MP2. Moreover, by using a TFT transistor whose channel part is about 5 nm, the leakage current is reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a technology that is effective when applied to a semiconductor memory device that has low standby power and high integration and does not require a refresh operation.

  For example, as a technique examined by the present inventors, a static memory (SRAM) is widely used as a random access memory (RAM) which is a kind of semiconductor memory device. Compared to dynamic memory (DRAM), SRAM is disadvantageous in terms of integration because it has a large number of elements constituting a memory cell, but it is not necessary to refresh and is easy to use.

An SRAM memory cell is generally composed of six transistors. Examples of four memory transistors are disclosed in Patent Documents 1 to 3.
JP 2000-124333 A JP 2001-167573 A JP 2003-303491 A

  By the way, as a result of examination of the SRAM memory cell technology as described above by the present inventors, the following has been clarified.

  There are two problems when an SRAM cell is composed of four transistors.

  The first problem is that it is difficult to satisfy both the information holding condition and the condition in which information is not destroyed during reading. Patent Documents 1 and 2 disclose means for retaining information without refreshing in a cell composed of four transistors, but this problem has not been solved.

  The second problem is that it is difficult to reduce the standby current while satisfying the information retention condition. A solution to this problem is not disclosed in Patent Documents 1 to 3.

  Patent Document 3 discloses a method of performing destructive read and restoring information by a rewrite operation in an SRAM cell composed of six transistors, and also describes an embodiment composed of four transistors. However, in the embodiment composed of four transistors, the design conditions necessary for holding and reading information and the design conditions and means for reducing the standby power are not sufficiently described. In addition, specific means are not sufficiently described regarding a method of configuring a capacitor for simplifying the manufacturing process.

  Accordingly, an object of the present invention is to stably hold information and read / write and realize low standby power for a semiconductor device having memory cells composed of four transistors.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A memory cell consisting of four transistors is provided with a capacitor for holding information, and writing is performed by taking charge into and out of the capacitor from the bit line, and reading is conducted electrically between the precharged bit line and the capacitor. The change in the bit line potential due to the detection is detected and amplified by the sense amplifier, and the potential of the capacitor changed in the reading is restored by rewriting in the reading cycle. Information is held by maintaining the potential of the capacitor by the difference in impedance of the transistor in which the source / drain path is connected between the bit line precharged to the same potential as the precharge at the time of reading and the power supply.

  Information retention is stabilized by making the impedance in the off state of the transistor between the bit line and the storage node smaller than the impedance in the off state of the transistor between the storage node and the power source.

  In addition, as a capacitor, a field effect transistor or a planar MIM (Metal Insulator Metal) capacitor using a metal layer used for wiring of a peripheral circuit is used, and a transistor in which a source / drain path is connected between a capacitor and a power source, A transistor formed using a film having a channel region thickness of 8 nm or less, preferably about 5 nm or less is used.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, a low power operation semiconductor device can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1A and 1B are diagrams showing an equivalent circuit of a memory cell and its operation according to an embodiment of the present invention.

  First, an example of the configuration of the memory cell according to the present embodiment will be described with reference to FIG. The memory cell MC of the present embodiment includes four field effect transistors MP1 (first transistor), MP2 (second transistor), MN1 (third transistor), MN2 (fourth transistor), and two capacitors C1 ( First capacitor) and C2 (second capacitor). Of the transistors, MP1 and MP2 are p-channel transistors, and MN1 and MN2 are n-channel transistors. WL is a word line, and BL and / BL are bit lines. PL is a plate electrode, and is maintained at a constant potential such as Vdd, Vss, for example.

  The transistor MP1 has a source / drain path connected to the bit line / BL (first bit line) and the storage node N1 (first electrode of the first capacitor C1), and a gate electrode connected to the word line WL. In the transistor MP2, the source / drain path is connected to the bit line BL (second bit line) and the storage node N2 (first electrode of the second capacitor C2), and the gate electrode is connected to the word line WL. The transistor MN1 has a source / drain path connected to the storage node N1 and a power supply GND (first power supply), and a gate electrode connected to the storage node N2. In the transistor MN2, a source / drain path is connected to the storage node N2 and the power supply GND, and a gate electrode is connected to the storage node N1. The second electrodes of the capacitors C1 and C2 are connected to the plate electrode PL.

  Information stored in the memory cell MC is stored by setting one of the storage nodes N1 and N2 to a high potential and the other to a low potential. That is, the first electrode of the capacitor C1 is high potential and the first electrode of the capacitor C2 is low potential, and the first electrode of the capacitor C1 is low potential and the first electrode of the capacitor C2 is high potential. Depending on the state, 1-bit information can be stored.

  A read operation (read), a write operation (write), and an information holding operation (retention) will be described with reference to FIG. In the following description, it is assumed that the high potential is Vdd, the low potential is 0 V, and the power supply GND is 0 V among the potentials that serve as the reference for the operation of the memory cell.

  In reading, the word line WL is set to a low potential in a state where the bit lines BL and / BL are precharged to Vdd. At this time, the potential of the word line WL is lowered from 0V so that the p-channel transistors MP1 and MP2 are sufficiently turned on and rewriting described later is sufficiently performed. As a result, charge redistribution occurs between the capacitors C1 and C2 and the capacitances of the bit lines BL and / BL, and the potential of one of the bit lines is lowered according to the stored information. The potential difference generated in the bit lines BL and / BL is detected and amplified by a sense amplifier SA (not shown), information is read from the memory, and the low potential side is set to 0 V while the high potential side is kept at Vdd. As a result, the potential of the first electrode of the capacitors C1 and C2 is recovered. Thereafter, the potential of the word line WL is returned to Vdd, and the bit lines BL and / BL are precharged to Vdd again.

  The write operation is as follows. First, similarly to the read operation, the word line WL is lowered to 0 V or less, and after the amplification by the sense amplifier SA is started, the bit lines BL and / BL are set to a potential to be newly stored. FIG. 1B shows a state where a potential different from the stored information is written. Thereafter, the potential of the word line WL is returned to Vdd, and the bit lines BL and / BL are precharged to Vdd again.

  As described above, the information is once read and written after the amplification is started for the following reason. As will be described later (see FIG. 3), the memory cells MC are arranged in an array, and a large number of memory cells MC are connected to one word line WL. Accordingly, the plurality of memory cells MC are selected at the same time when the word line WL is lowered to 0 V or less. Even if the number of cells to be written is smaller than the number of selected memory cells, there is no problem in principle because rewriting is performed in unselected cells on the same word line. However, if the selected cell is written before the amplification by the sense amplifier SA, the potential of the bit line of the non-selected cell on the same word line adjacent to the selected cell fluctuates due to noise, and the sense amplifier SA on the non-selected cell side. This is because there is a possibility of malfunction. In this manner, since the sense amplifier SA is operating, it is possible to expect a stable operation that is hardly affected by noise.

  Next, the information holding operation will be described. The information holding operation is simple. As shown in FIG. 1B, it is only necessary to turn on the precharge circuit PRG (see FIG. 3) to be described later and keep the bit lines BL and / BL at Vdd while keeping the word line WL at Vdd. A refresh operation like a normal DRAM is not necessary.

  FIGS. 2A and 2B are diagrams showing the principle and conditions for holding information in the memory cell according to the present embodiment. The principle of information retention will be described with reference to FIGS. FIG. 2A shows a case where the storage node N1 on the capacitor C1 side is at the high potential VH and the storage node N2 on the capacitor C2 side is at the low potential VL. In this case, the transistors MP1, MP2, and MN1 are off, and the transistor MN2 is on. As a result, the storage node N2 on the capacitor C2 side is kept at 0V by the transistor MN2. On the other hand, since the transistors MP1 and MN1 are both turned off, a potential between the potential Vdd of the bit line / BL and the potential 0V of the GND is set due to the difference in impedance between the transistors MP1 and MN1. By using this, the constants and threshold voltages of the transistors MP1 and MN1 are set so that the impedance of the transistor MP1 in the off state is lower than the impedance in the off state of the transistor MN1, so that the storage node on the capacitor C1 side is set. The potential of N1 is held at a potential close to Vdd.

  Although the case where the storage node N1 on the capacitor C1 side is at the high potential VH has been described above, information is retained on the same principle when the storage node N2 is at the high potential VH. In that case, the impedance in the off state of the transistor MP2 may be set lower than the impedance in the off state of the transistor MN2. That is, in order to retain information in the memory cell of FIG. 2A, a constant (channel width W) is set so that the impedance in the off state of the transistors MP1 and MP2 is lower than the impedance in the off state of the transistors MN1 and MN2. , Channel length L, threshold voltage Vth, etc.) may be set. If the ratio of both impedances is about 1:10, the storage node on the high potential side can be held at a sufficient potential. For example, the ratio L / W of the channel length L and the channel width W of the transistors MP1 and MP2 is made smaller than the ratio L / W of the channel length L and the channel width W of the transistors MN1 and MN2, The threshold voltage is made smaller than the threshold voltages of the transistors MN1 and MN2.

The above information retention (data retention) conditions are summarized in the upper part of FIG. The holding condition of the high potential VH is
Z (MP-off) <Z (MN-off) (1)
The holding condition of the low potential VL is
Z (MP-off)> Z (MN-on) (2)
It can be expressed as. Here, Z indicates impedance, MP in parentheses after that indicates a p-channel transistor, MN indicates an n-channel transistor, on indicates that they are in an on state, and off indicates that they are in an off state. For the sake of simplicity, the distinction between the on state and the off state is shown here. However, since the storage node is at a high potential in Equation (1) and is at a low potential in Equation (2), for example, Equation (1) The drain potential of the p-channel transistor differs between Z (MP-off) of the equation (2) and Z (MP-off) of the equation (2).

The lower part of FIG. 2B shows the nondestructive reading conditions as described in Patent Document 1 and the like. For nondestructive reading, it is necessary to make the impedance of the p-channel transistor higher than the impedance of the n-channel transistor so that the potential of the storage node on the low potential side does not rise at the time of reading. As shown,
Z (MP-on)> Z (MN-on) (3)
It can be expressed as.

From formulas (1) to (3),
Z (MN-off)> Z (MP-off)> Z (MP-on)> Z (MN-on) (4)
It can be expressed as.

  Therefore, it can be seen that in order to achieve both non-destructive reading and high potential holding conditions, the difference in impedance between the n-channel transistors when turning on and off needs to be larger than the difference between impedances when turning on and off in the p-channel transistors. In many cases, it is difficult to satisfy this condition within a range of transistor variations and a wide operating temperature.

  In the present embodiment, since rewriting is performed without performing non-destructive reading, the condition of Expression (3) becomes unnecessary, and a stable operation with a sufficient margin can be expected. Note that the condition of Equation (2) can be easily satisfied because the on-state impedance of the n-channel transistor only needs to be lower than the off-state impedance of the p-channel transistor.

  As a further advantage of the circuit and design conditions according to this embodiment as described above, it is easy to reduce standby power. As can be seen from FIG. 2A, the main components of the consumption current during the standby time are the leakage current flowing through the off-state transistors MP1 and MN1, and the leakage current flowing through the off-state transistor MP2 and the on-state transistor MN2. It is. The former is negligible compared to the latter because both transistors are off, and the latter is governed by the leakage current of the transistor MP2.

  Therefore, the standby current is determined by the leakage current of the p-channel transistor, and in order to reduce it, it is necessary to increase the impedance Z (MP-off) in the OFF state of the p-channel transistor. Therefore, in order to reduce the standby current from the condition of equation (1), it is necessary to further increase the impedance Z (MN-off) in the off state of the n-channel transistor.

  If the standby power is to be lowered while satisfying the nondestructive readout condition of Equation (3), it can be seen that the impedance difference when turning on and off the n-channel transistor needs to be very wide. From this, it can be said that the present embodiment shown in FIG. 1 does not require the condition of the expression (3), and can easily achieve low standby power.

  FIG. 3 is a diagram showing a configuration of a memory array using the memory cells of FIG. In FIG. 3, an address buffer, a decoder and driver circuit, a read and write circuit, a timing generation circuit, a power supply circuit, and the like are omitted. These can be configured within the range of ordinary memory design knowledge. In FIG. 3, the memory cells MC shown in FIG. 1 are two-dimensionally arranged, and a precharge circuit PRG and a sense amplifier SA are provided for each pair of bit lines BL and / BL.

  The precharge circuit PRG is composed of p-channel transistors MP3, MP4 and MP5. The transistor MP3 has a source / drain path connected to the bit lines BL and / BL and a gate connected to the signal line PR. Transistors MP4 and MP5 have sources connected to Vdd, drains connected to bit lines BL and / BL, and gates connected to signal line PR.

  The sense amplifier SA includes p-channel transistors MP6 and MP7 and n-channel transistors MN3 and MN4. The transistors MP6 and MP7 have sources connected to the signal line PSA, gates connected to one bit line BL, / BL, and drains connected to the other bit line / BL, BL. The transistors MN3 and MN4 have sources connected to the signal line NSA, gates connected to one bit line BL, / BL, and drains connected to the other bit line / BL, BL.

  In order to activate the precharge circuit PRG, the potential of the signal line PR may be set to 0V. As a result, the p-channel transistors MP3, MP4, and MP5 connected to the signal line PR are turned on, and the paired bit lines BL and / BL are short-circuited by the transistor MP3 and precharged to Vdd by the transistors MP4 and MP5. . After the precharge, if the potential of the signal line PR is set to Vdd, the bit lines BL and / BL are brought into a floating state at the potential of Vdd, and read and write operations can be started. In the information holding state, PR is set to 0 V so that an information holding current can be supplied to the memory cell. The reason why the precharge circuit PRG is configured by the p-channel transistors MP4 and MP5 is that the bit lines BL and / BL are precharged with the high potential Vdd. In the case of using an n-channel transistor, the potential of the signal line PR needs to be higher than Vdd.

  As the sense amplifier SA, a four-transistor used in a DRAM or the like can be used. In order to operate, the potential of the signal line PSA is lowered to Vdd, and the potential of the signal line NSA is lowered to 0V. When the sense amplifier SA is turned off during standby or the like, both the signal lines PSA and NSA may be set to Vdd.

  In the present embodiment, the precharge circuit PRG and the sense amplifier SA can be configured with a small number of transistors, so that the area is small, and these circuits can be provided for each bit line. Since a normal SRAM is nondestructive reading, it is possible to share a sense amplifier with a plurality of bit lines. However, since the memory cell shown in FIG. 1 performs rewriting, it must be provided for each bit line pair. Therefore, the configuration according to the present embodiment shown in FIG. 3 is effective.

  In order to implement the above-described embodiment on an integrated circuit at a low manufacturing cost, it is effective to form the capacitors C1 and C2 of the memory cell MC by a simple process. As an example, a planar capacitor having an MIM (Metal Insulator Metal) structure using a wiring layer of a peripheral circuit as an electrode is effective. In this case, since the capacitor can be arranged above the transistor constituting the memory cell, the area of the memory cell is also reduced, and further reduction in manufacturing cost due to the area reduction can be expected.

  As the manufacturing process and the cross-sectional structure of such a capacitor, those described in the patent application JP01 / 010991 (PCT) and Japanese Patent Application Laid-Open No. 2003-264236 filed earlier by the present applicant can be used. In this example, tantalum pentoxide is used as the insulating film, and a sufficient capacity can be obtained with a small area, which is suitable for this embodiment. Since such a capacitor has good compatibility with a process of a logic LSI, it is suitable when the memory of the present embodiment is used as an on-chip memory of a logic LSI such as an ordinary processor.

  Normally, in the differential sense amplifier as shown in FIG. 3, the potential difference between the bit line pair at the time of reading, that is, the signal voltage needs to be about 50 mV or more in consideration of variations in the threshold voltage of the transistors. In the memory cell shown in FIG. 1, the signal voltage is approximately proportional to Vdd · Cs / (Cs + Cd). Here, Cs is the capacitance of the capacitors C1 and C2, and Cd is the capacitance of the bit lines BL and / BL.

  Therefore, the capacitances of the capacitors C1 and C2 may be designed so as to obtain a value equal to or higher than the minimum signal amount according to the voltage Vdd and the capacitance Cd of the bit lines BL and / BL.

  In some cases, it may be difficult to add a manufacturing process for the capacitor. In such a case, it is possible to form a capacitor with the gate capacitance of the transistor. Such an embodiment is shown in FIG.

  FIGS. 4A and 4B are diagrams showing an equivalent circuit and its operation when the capacitor of the memory cell is formed of a field effect transistor. In the memory cell shown in FIG. 4A, capacitors C1 and C2 are composed of transistors MN5 and MN6. The gate electrodes of the transistors MN5 and MN6 are storage nodes N1 and N2, and the drain and source are plate electrodes PL. Connected. In the present embodiment, in addition to the effect of eliminating the increase in process steps as described above, the signal amount can be increased by performing the operation as shown in FIG.

  The principle will be described with reference to FIG. Although FIG. 4B shows only the read operation, the write operation as shown in FIG. 1B has the same effect because the read operation is first performed. Information holding is the same as that of the embodiment shown in FIG. In FIG. 4B, the potential of the plate electrode PL is raised to Vdd when the potential of the word line WL is lowered. At this time, the transistor (MN5 or MN6) connected to the storage node (N1 or N2) on the high potential side has a sufficient capacity, but the capacitor (C1 or C2) on the low potential side has the transistor (MN5 or MN6). ) Is off, so the capacity is low. Therefore, when the potential of the plate electrode PL is raised, the potential of the storage node on the high potential side rises and the low potential side does not change much. As a result, the potential of the bit line on the high potential side can be made higher than Vdd, and the signal amount can be increased.

  If the potential of the plate electrode PL is lowered after the word line WL is raised to Vdd, the potentials of the storage nodes N1 and N2 are lowered, so that the potential of the plate electrode PL is increased while the sense amplifier SA is operating. Return to 0V.

  As described above, according to the read operation of FIG. 4B, the signal amount can be increased by driving the plate electrode PL.

  In addition, in order to reduce standby power, when a transistor having a relatively large gate insulating film thickness (for example, 4 nm or more) is used for a memory cell so that gate leakage current does not become a problem, insufficient capacity of the capacitor is a problem. There is a possibility of becoming. In such a case, the embodiment shown in FIG. 4B is effective.

  The above is a method for increasing the signal amount when a transistor is used as a capacitor. However, it is possible to increase the signal amount even with a normal capacitor such as the MIM capacitor described above. The memory cell shown in FIG. 5 is an effective embodiment for that purpose.

  FIG. 5 is a diagram showing an equivalent circuit of a memory cell when a single capacitor is used. The memory cell shown in FIG. 5 is characterized by one capacitor (C0 in FIG. 5), one electrode serving as the storage node N1 (first electrode of the capacitor C0), and the other electrode serving as the storage node N2 (capacitor C0). To the second electrode). If it does in this way, the amount of signals will increase by a kind of coupling action between the electrodes of capacitor C0. The expression relating to the signal amount is described in the patent application JP01 / 010991 (PCT) of the applicant's earlier application. According to the present embodiment, since the signal amount can be increased even in the case of the MIM capacitor, it is possible to realize a memory cell having a small area and a sufficient operation margin even at a low voltage.

  In the embodiments described so far, the transistors that connect the capacitors C0, C1, and C2 and the bit lines BL and / BL are configured by the p-channel transistors MP1 and MP2, and the transistors that connect the storage nodes N1 and N2 and the power supply GND are n Channel transistors MN1 and MN2 were used. Since the transistors that connect the bit lines BL and / BL and the storage nodes N1 and N2 determine the read and write speeds, in some cases, n-channel transistors that easily obtain a large current are connected to the bit lines BL and / BL. It may be advantageous to use this for connection. In such a case, the embodiment shown in FIG. 6 is effective.

  FIG. 6 is a diagram showing an equivalent circuit in the case where an n-channel transistor and a p-channel transistor are replaced with respect to the memory cell of FIG. The memory cell shown in FIG. 6 is an example in which the n-channel transistors MN1 and MN2 and the p-channel transistors MP1 and MP2 are replaced in the circuit of FIG. 1 and the power source connected to the p-channel transistors MP1 and MP2 is Vdd. Although the embodiment of the memory cell of FIG. 1 has been described here, it is a matter of course that the roles of the transistors MN1, MN2, MP1, and MP2 can be similarly changed in the memory cells of FIG. 4 and FIG.

  In the n-channel transistor and the p-channel transistor, the on / off characteristics with respect to the gate-source voltage are reversed. Therefore, in the embodiment of FIG. 6, the word line WL is connected to the precharge period and the retention of the bit lines BL and / BL. The period is 0 V, and it is a matter of course that the potential is set to a high potential (for example, a potential obtained by adding about twice the threshold voltage of the n-channel transistor to Vdd) at the time of reading and writing.

In the embodiment of FIG. 6, since the power sources of the transistors MP1 and MP2 are Vdd, the precharge voltages of the bit lines BL and / BL are of course set to 0V. As for the information holding condition in FIG. 6, as can be easily understood from the description in the above embodiment, the holding condition of the high potential VH is:
Z (MN-off)> Z (MP-on) (5)
The holding condition of the low potential VL is
Z (MN-off) <Z (MP-off) (6)
It can be expressed as.

  In the embodiments described so far, the standby current is determined by the off-state impedance of the transistor connected to the bit line, and the standby current decreases as the impedance increases (leakage current decreases). On the other hand, as can be seen from the information retention (retention) condition, the off-state impedance of the transistor connected to the power supply needs to be further increased than the off-state impedance of the transistor connected to the bit line. Therefore, when the target standby current is small, not only a normal bulk transistor but also a TFT transistor having a very thin channel portion as shown in FIGS. 7A and 7B is used as a transistor connected to the power source. Good.

  FIGS. 7A and 7B are cross-sectional views showing the structure of a transistor having a very thin channel portion used in the memory cell described above. In the embodiment shown in FIG. 7A, the transistor is planarly formed on the element isolation region ISO formed in the semiconductor substrate SUB. In FIG. 7A, the transistor MN1 in the embodiment of FIGS. 1, 4 and 5 is taken as an example and will be described with symbols corresponding thereto, but the transistor MN2 of FIGS. 1, 4 and 5 and FIG. The transistors MP1, MP2, etc. can be configured in the same manner.

  In addition, since the current of the transistor of this embodiment increases as the thickness of the channel portion CH is increased, the transistor connected to the bit line is adjusted by adjusting the thickness of the channel portion CH so as to satisfy the above-described design condition. It is also possible to apply to the capacitors C1 and C2 of FIG.

  In FIG. 7A, the channel portion CH is a channel portion formed of thin-film polysilicon having a thickness of 8 nm or less, preferably about 5 nm or less, thereby reducing the leakage current and reducing the standby current. it can. OX is an insulating film. N1 and N2 are storage nodes, and GND represents connection to a power supply terminal having a potential of 0V. SUB is a semiconductor substrate. In this embodiment, like a normal transistor, it is formed in a plane over a substrate. For this reason, there is an advantage that a process such as wiring and contact is facilitated without a large step.

  FIG. 7B shows a preferred embodiment for realizing high integration of similar transistors, and is particularly effective when the increase in area becomes a problem in the planar structure. In this embodiment, a transistor having a vertical structure is formed inside a hole formed on polysilicon used for a gate layer of a bulk transistor. CH is a channel portion of the transistor, and is formed of a thin film such as polycrystalline silicon having a thickness of about 8 nm, preferably about 5 nm or less. The gate electrode of the transistor has a cylindrical shape, and the periphery thereof is surrounded by the oxide insulating film OX and the channel portion CH. One of the source and drain regions of the transistor is connected to polysilicon used for the gate electrode of the bulk transistor, and the potential thereof is set to the potential 0 V of the power supply GND.

  7A and 7B, when the potential of the gate electrode becomes high, the channel portion CH becomes conductive, and when the potential becomes low, the channel portion CH becomes non-conductive. Since the thickness of the channel part CH is very thin, about 8 nm or less or about 5 nm or less, the leakage current at the time of off can be made extremely small as compared with a normal transistor. While a normal transistor has a leakage current of 10 minus 10 to 12 amperes, the thin film transistor having a channel of about 5 nm or less as in the present embodiment has a quantum mechanics in the film thickness direction. Because of the effective confinement effect, it is possible to make the leakage current about 10 to the 19th power. A field effect transistor having a thin film channel having such a structure is described, for example, in US Pat. No. 6,576,943.

  As described above, by using the transistors as shown in FIGS. 7A and 7B, the standby current of the semiconductor device using the memory cell of this embodiment can be extremely reduced. In addition, if such a transistor is used, it is easy to keep the impedance at the time of off, so that it becomes easy to satisfy the information retention condition and the operation margin is increased. For example, when it is necessary to increase the range of the operating power supply voltage or the operating temperature, it is necessary to control the voltage of the word line when holding information. By controlling the voltage of the word line, the impedance when the transistor connected to the bit line is turned off can be changed according to temperature and voltage, which is effective in satisfying the information holding condition. However, when the transistors of the form shown in FIGS. 7A and 7B are used, it is not necessary or simple control can be performed even if necessary.

  Therefore, according to the semiconductor device of the present embodiment described above, a refresh operation is not required and an easy-to-use memory can be realized by the above read / write and information holding method. In addition, since rewriting is performed at the time of reading, there is no transistor design restriction for nondestructive information at the time of reading, and the operation margin is increased. Furthermore, since the information holding current can be easily reduced by the design based on the destruction of information, the standby current is extremely reduced by using a transistor having a thin channel portion and a very small leakage as described above. It becomes possible to do. Moreover, low cost is implement | achieved by using the above elements as a capacitor.

  8 to 10 show an example of the planar structure when the memory cell described so far is realized on a semiconductor substrate, and FIG. 11 shows an example of the corresponding cross-sectional structure. Here, the circuit configuration of the memory cell shown in FIG. 5 is assumed, and the case where the above-described MIM capacitor is applied as the capacitor C0 is assumed. Since the number of layers is large, in order to show a planar structure, it is divided into FIG. 8 to FIG. 10 in order from the bottom (close to the substrate). 8A, 9A, and 10A show the planar structure of the memory cell, and FIGS. 8B, 9B, and 10B show the names of the respective layers ( Symbols) and the symbols used in the plan view are shown. 8A, FIG. 9A, and FIG. 10A mainly show portions corresponding to the circuit of FIG. 5 so that the electrical correspondence with the circuit of FIG. 5 can be seen. Is shown. When the layers overlap, the lower layer is also shown so that it can be seen. However, if the layers with diagonal lines overlap like FG, SG, L in FIG. The layers only show the outline and only the top layer pattern. In the plan views of FIG. 8A, FIG. 9A, and FIG. 10A, a rough broken line on the outer periphery is a boundary region of the memory cell MC. When forming a memory array, the boundary lines may be overlapped. Note that the constraints such as the space between layers and the width of the layers depend on the manufacturing process, but here, in order to make the drawing easier to see, the dimensions and ratios of the patterns are changed.

  FIG. 8 shows the first polysilicon layer FG, the second polysilicon layer SG, the diffusion layer L, the first metal layer M1, and the contact layer CONT. The contact layer CONT is a layer for connecting the first polysilicon layer FG, the second polysilicon layer SG, or the diffusion layer L and the first metal layer M1 above them. The transistor MP1 in FIG. 5 is formed in the diffusion layer portion on the upper left in FIG. 8A, and the transistor MP2 is formed in the diffusion layer portion on the upper right. Further, the transistors MN1 and MN2 in FIG. 5 are formed in the lower part of FIG. These are TFT transistors having a very thin channel portion having the structure shown in FIG. A first polysilicon layer FG and a second polysilicon layer SG are arranged in the lower part of FIG. 8A. The second polysilicon layer SG is a gate electrode of the transistors MN1 and MN2. The channel layer of the transistor is formed under the second polysilicon layer SG so as to connect the first polysilicon layer FG.

  FIG. 9 shows a layer above the layer shown in FIG. M2, M3, VIA1, and VIA2 are a second metal layer, a third metal layer, a first via layer, and a second via layer, respectively. The first via layer VIA1 is for connecting the first metal layer M1 and the second metal layer M2, and the second via layer VIA2 is for connecting the second metal layer M2 and the third metal layer M3. Is a layer. As shown in FIG. 9A, the bit line pair BL, / BL is wired in the vertical direction of the memory cell region by the second metal layer M2. In FIG. 9A, there are two third metal layers M3. The larger one is the lower electrode of the capacitor C0 in FIG. 5, and is electrically connected to the storage node N2. The other third metal layer M3 is electrically connected to the storage node N1, and is connected to the upper electrode of the capacitor C0 as will be described later.

  FIG. 10 shows the fourth metal layer M4, the upper electrode layer MU of the capacitor C0, and the third via layer VIA3. The third via layer VIA3 is a layer for connecting the third metal layer M3 or the upper electrode layer MU of the capacitor C0 to the fourth metal layer M4. As can be seen from comparison with FIG. 9, the storage node N1 is once raised to the fourth metal layer M4 and then connected to the upper electrode layer MU of the capacitor C0 by the third via layer VIA3.

  As described above, when the memory array is formed, the memory cells may be arranged so as to overlap the cell boundary. In this case, the word line WL is connected to the first polysilicon layer FG as shown in FIG. Therefore, when many memory cells are connected in the direction of the word line WL, signal delay due to the resistance of the word line may become a problem. In such a case, a fourth metal layer M4 is newly arranged in parallel above the word line WL so that a gap is formed for each appropriate number of memory cells, and the first polysilicon corresponding to the word line WL is formed. The layer FG and the fourth metal layer M4 provided above may be shunted, or the word line WL may be hierarchized to shorten the length of the local word line formed by the first polysilicon layer FG layer. .

  FIG. 11 is a cross-sectional view taken along the line AA of FIGS. In an actual semiconductor device, the cross section of the layer does not become a true square as shown in the figure, but here, it is expressed by a true square for easy understanding of the vertical relationship of the layers. The first polysilicon layer FG and the second polysilicon layer SG shown in FIG. 8 are provided above the oxide film of the semiconductor substrate SUB and the element isolation region ISO, and the transistors MN1 and MN2 of FIG. 5 are formed in this portion. Has been. Further, an upper electrode layer MU of the capacitor C0 and a third metal layer M3 corresponding to the lower electrode are shown in the upper part of the drawing. There is an interlayer film IL between the upper electrode layer MU and the lower electrode of the capacitor C0. The interlayer film IL is actually composed of a plurality of layers such as a barrier metal layer and a tantalum pentoxide layer, as described in the above-mentioned document relating to the MIM capacitor, but is omitted in FIG.

  As described above, according to the memory cell structure shown in FIGS. 8 to 11, in the memory cell of FIG. 5, the capacitor C0 can be disposed above the transistor, so that the memory cell can be highly integrated. Therefore, according to the present embodiment, it is possible to realize a low-cost memory due to a small increase in process steps due to the formation of the planar MIM capacitor and high integration.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The invention disclosed in the present application can be applied to a semiconductor device including a memory such as an SRAM.

(A), (b) is a figure which shows the equivalent circuit of a memory cell, and its operation | movement in the semiconductor device by one embodiment of this invention. (A), (b) is a figure which shows the principle and conditions of information retention of a memory cell in the semiconductor device by one embodiment of this invention. 1 is a diagram showing a configuration of a memory array in a semiconductor device according to an embodiment of the present invention. (A), (b) is a figure which shows the equivalent circuit and operation | movement of a memory cell when a capacitor is comprised with the transistor in the semiconductor device by one embodiment of this invention. FIG. 4 is a diagram showing an equivalent circuit of a memory cell when a single capacitor is used in the semiconductor device according to the embodiment of the present invention. FIG. 2 is a diagram showing an equivalent circuit of a memory cell when an n-channel transistor and a p-channel transistor are replaced with respect to the memory cell of FIG. 1 in the semiconductor device according to the embodiment of the present invention. (A), (b) is sectional drawing which shows the structure of a transistor with a very thin channel part in the semiconductor device by one embodiment of this invention. (A), (b) is a figure which shows the planar structure to the 1st metal layer in the case of forming the memory cell of FIG. 5 on a semiconductor substrate. (A), (b) is a figure which shows the planar structure to the 3rd metal layer in the case of forming the memory cell of FIG. 5 on a semiconductor substrate. (A), (b) is a figure which shows the planar structure to the 4th metal layer in the case of forming the memory cell of FIG. 5 on a semiconductor substrate. It is sectional drawing in the AA cut surface of FIGS.

Explanation of symbols

MN1 to MN6, MP1 to MP7 Transistors C0 to C2 Capacitors N1, N2 Storage nodes WL, WL1, WLn Word lines BL, / BL, BL1, / BL1, BLm, / BLm Bit line PL Plate electrode PRG Precharge circuit PR, PSA , NSA signal line SA sense amplifier MC memory cell SUB semiconductor substrate CH channel part ISO element isolation region OX insulating film GND power supply VH high potential VL low potential M1 first metal layer M2 second metal layer M3 third metal layer M4 fourth metal Layer MU upper electrode layer IL of capacitor C0 interlayer film FG first polysilicon layer SG second polysilicon layer L diffusion layer CONT contact layer VIA1 first via layer VIA2 second via layer VIA3 third via layer

Claims (10)

A semiconductor device including a memory cell for storing information in a capacitor,
The memory cell is
A first transistor having a source / drain path connected to the first bit line and the first electrode of the first capacitor and a gate electrode connected to the word line;
A second transistor having a source / drain path connected to the second bit line and the first electrode of the second capacitor and a gate electrode connected to the word line;
A third transistor having a source / drain path connected to the first electrode of the first capacitor and a first power supply, and a gate electrode connected to the first electrode of the second capacitor;
A source and drain path connected to the first electrode of the second capacitor and the first power supply, and a fourth transistor having a gate electrode connected to the first electrode of the first capacitor;
The semiconductor device according to claim 1, wherein impedances of the first and second transistors in an off state are smaller than impedances of the third and fourth transistors in an off state. A semiconductor device including a memory cell for storing information in a capacitor,
The memory cell is
A first transistor having a source / drain path connected to the first bit line and the first electrode of the first capacitor and a gate electrode connected to the word line;
A second transistor having a source / drain path connected to the second bit line and the first electrode of the second capacitor and a gate electrode connected to the word line;
A third transistor having a source / drain path connected to the first electrode of the first capacitor and a first power supply, and a gate electrode connected to the first electrode of the second capacitor;
A source and drain path connected to the first electrode of the second capacitor and the first power supply, and a fourth transistor having a gate electrode connected to the first electrode of the first capacitor;
During a write operation, the potential of the first electrode of the first and second capacitors is set to a desired potential from the first and second bit lines through the first and second transistors,
During a read operation, the first and second transistors are turned on while the first and second bit lines are charged to a constant potential, and a change in the potential of the first and second bit lines is detected and amplified by a sense amplifier. And writing the amplified potential to the first electrodes of the first and second capacitors again,
In the non-selected state, the first and second bit lines are charged to a constant potential, and the first and second transistors are made non-conductive, whereby the first and third transistors are connected to the first bit line. The potential of the first electrodes of the first and second capacitors depends on the difference between the leakage current flowing through the first power supply and the leakage current flowing from the second bit line through the second and fourth transistors to the first power supply. The semiconductor device characterized by holding. A semiconductor device including a memory cell for storing information in a capacitor,
The memory cell is
A first transistor having a source / drain path connected to a first bit line and a first electrode of the capacitor, and a gate electrode connected to a word line;
A second transistor having a source / drain path connected to a second bit line and a second electrode of the capacitor, and a gate electrode connected to the word line;
A third transistor having a source / drain path connected to the first electrode of the capacitor and a first power supply, and a gate electrode connected to the second electrode of the capacitor;
A fourth transistor having a source / drain path connected to the second electrode of the capacitor and the first power supply, and a gate electrode connected to the first electrode of the capacitor;
The semiconductor device according to claim 1, wherein impedances of the first and second transistors in an off state are smaller than impedances of the third and fourth transistors in an off state. A semiconductor device including a memory cell for storing information in a capacitor,
The memory cell is
A first transistor having a source / drain path connected to a first bit line and a first electrode of the capacitor, and a gate electrode connected to a word line;
A second transistor having a source / drain path connected to a second bit line and a second electrode of the capacitor, and a gate electrode connected to the word line;
A third transistor having a source / drain path connected to the first electrode of the capacitor and a first power supply, and a gate electrode connected to the second electrode of the capacitor;
A fourth transistor having a source / drain path connected to the second electrode of the capacitor and the first power supply, and a gate electrode connected to the first electrode of the capacitor;
During the write operation, the potentials of the first and second electrodes of the capacitor are set to desired potentials from the first and second bit lines through the first and second transistors,
During a read operation, the first and second transistors are turned on while the first and second bit lines are charged to a constant potential, and a change in the potential of the first and second bit lines is detected and amplified by a sense amplifier. Then, the amplified potential is again written to the first and second electrodes of the capacitor,
In the non-selected state, the first and second bit lines are charged to a constant potential, and the first and second transistors are made non-conductive, whereby the first and third transistors are connected to the first bit line. The potential of the first and second electrodes of the capacitor is held by the difference between the leakage current flowing through the first power supply and the leakage current flowing from the second bit line through the second and fourth transistors to the first power supply. A semiconductor device comprising: The semiconductor device according to any one of claims 1 to 4,
The ratio L / W between the channel length L and the channel width W of the first and second transistors is smaller than the ratio L / W between the channel length L and the channel width W of the third and fourth transistors. A semiconductor device. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device according to claim 1, wherein a threshold voltage of the first and second transistors is smaller than a threshold voltage of the third and fourth transistors. The semiconductor device according to any one of claims 1 to 4,
2. The semiconductor device according to claim 1, wherein the capacitor comprises a field effect transistor. The semiconductor device according to any one of claims 1 to 4,
The third and fourth transistors are field effect transistors having a channel portion thickness of 8 nm or less. The semiconductor device according to any one of claims 1 to 4,
The third and fourth transistors are field effect transistors having a channel portion thickness of 5 nm or less. The semiconductor device according to any one of claims 1 to 4,
The semiconductor device according to claim 1, wherein both the first electrode and the second electrode of the capacitor are metal.