JP2007115335A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce leakage from a storage node in a DRAM cell so-called a gain cell. <P>SOLUTION: The semiconductor storage device has a write transistor WT, a transfer transistor TT, an amplifier transistor AT and a charge storage capacitor (storage capacitor C1). In the write transistor WT, either a source or a drain domain is connected with a write bit line WBL and the other is connected with a gate of the amplifier transistor AT, and a gate is connected with a write wordline WWL. In a transfer transistor TT, either a source or a drain domain is connected with the gate of the amplifier transistor AT and the other is connected with a storage node electrode of the storage capacitor C1, and the gate is connected with a transfer gate line TG. A drain of the amplifier transistor AT is connected with a read bit line RBL, and a source is connected with a common source line CSL. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device that performs a read operation by inputting charge from a write transistor to a storage node and turning on or off an amplifier transistor according to the voltage of the storage node.

Among memory devices classified as so-called dynamic random access memories (DRAMs), a 1T1C type DRAM is composed of one transistor and one charge storage capacitor, and is highly integrated.
However, since the 1T1C type DRAM charges and discharges the bit line, the capacity of the charge storage capacitor C needs to be as large as several tens [fF], and the manufacturing technology of the capacitor becomes complicated as the cell size becomes finer. ing.

For the above reasons, a 3T DRAM has been proposed (see, for example, Patent Document 1).
The 3T type DRAM is composed of three transistors and has a cell area that is not as large as that of the 1T1C type DRAM. However, since it has an amplifying function, it does not require a large-capacity charge storage capacitor and has good compatibility with a logic process.

FIG. 15 shows an equivalent circuit of a 3T type DRAM cell of the type proposed in Patent Document 1.
The drain of the write transistor WT is connected to the write bit line (WB), the source is connected to the gate of the amplifier transistor AT, and the gate is connected to the write word line (WW). The source of the amplifier transistor AT is grounded, and the drain is connected to the source of the selection transistor ST. The drain of the selection transistor ST is connected to the read bit line RB, and the gate is connected to the read word line RW.

The operation of this 3T DRAM will be described.
For writing, the write word line WW is turned on, that is, raised to a high level, and the write transistor WT is activated. When storing “1” data in the cell, the write bit line WB is set to the power supply voltage Vdd, and when storing “0” data in the cell, the write bit line WB is set to 0 [V]. As a result, a desired voltage is applied to the charge storage node (storage SN).
The accumulated charges are mainly accumulated in the capacitance between the source side diffusion layer and the substrate and gate of the write transistor WT and the MOS capacitance of the amplifier transistor AT.

  After writing, the write word line WW is turned off, that is, it is lowered to a low level, and the write transistor WT is turned off. As a result, the storage node SN becomes floating, and the accumulated charge is held.

At the time of reading, after the read bit line RB is precharged, the read word line RW is selected.
When “1” data is written in the cell, both the amplifier transistor AT and the selection transistor ST are turned on, so that the read bit line RB is connected to the ground voltage (GND), and the read bit line RB The voltage drops.
When “0” data is written in the cell, the selection transistor ST can be turned on. However, since the amplifier transistor AT is kept off, the read bit line RB is connected to the ground voltage (GND). In other words, the voltage of the read bit line RB does not change.
A change in the voltage of the read bit line RB is determined by a sense amplifier (not shown).

In addition to 3T DRAM, 3T1C DRAM has also been proposed (see, for example, Patent Document 2).
The 3T1C type DRAM has a configuration in which one charge storage capacitor (hereinafter referred to as a storage capacitor) is added to the 3T type DRAM. Since this storage capacitor generally uses a MOS capacitor, a complicated capacitor manufacturing process is not required.

FIG. 16 shows an equivalent circuit of a 3T1C type DRAM cell of the type described in Patent Document 2.
The drain of the write transistor WT is connected to the write bit line (WB), the source is connected to the gate of the amplifier transistor AT and one electrode of the storage capacitor C, and the gate is connected to the word line (W). The source of the amplifier transistor AT is grounded, and the drain is connected to the source of the selection transistor ST. The drain of the selection transistor ST is connected to the read bit line (RB), and the gate is connected to the word line (W).

The operation of this 3T1C type DRAM will be described.
For writing, the word line is turned on to activate the write transistor WT.
When storing “1” data in the cell, the write bit line (WB) is set to the power supply voltage Vdd. When storing “0” data in the cell, the write bit line (WB) is set to 0 [V]. Set. As a result, a desired voltage is applied to storage node SN.
The accumulated charge is accumulated mainly in the capacitance between the source side diffusion layer and the substrate and gate of the write transistor WT, the MOS capacitance of the amplifier transistor AT, and the storage capacitor C connected to the storage node SN.

  After writing, the word line is turned off to turn off the write transistor WT. As a result, the storage node SN becomes floating, and charge accumulation is maintained.

At the time of reading, a positive voltage is applied to the terminal T to which the other electrode of the storage capacitor C connected to the storage node SN is connected.
As a result, the voltage of the storage node SN is boosted. At this time, the voltage of the storage node SN rises to the extent that the amplifier transistor AT is turned on when “1” data is written in the cell, but when “0” data is written in the cell. In this case, the voltage increase amount of the storage node SN is low, and the amplifier transistor AT remains off.
When the word line is turned on, when “1” data is written in the cell, both the amplifier transistor AT and the selection transistor ST are turned on, so that the read bit line (RB) is connected to the ground voltage (GND). And the voltage of the read bit line (RB) decreases.
When “0” data is written in the cell, the selection transistor ST is turned on, but the amplifier transistor AT is kept off, so that the read bit line (RB) is connected to the ground voltage (GND). The voltage of the read bit line (RB) does not change.
A change in the voltage of the read bit line (RB) is determined by a sense amplifier (not shown).
JP-A-60-95963 Japanese Unexamined Patent Publication No. 63-894

  In any of the 3T type DRAM and the 3T1C type DRAM, it is inevitable that the voltage of the storage node leaks during data retention.

As a leak path,
(1) Off-leakage of the write transistor WT from the storage node SN to the write bit line (WB),
(2) a gate insulating film leak from the storage node SN to the gate of the write transistor WT;
(3) Junction leakage between the N-type impurity region and the substrate or the P well, which passes from the N-type impurity region of the storage node SN to the substrate (or P well)
(4) Leakage between the electrodes of the storage capacitor C that passes from the storage node SN to the substrate (or P well),
(5) There is a gate insulating film leak of the amplifier transistor AT that passes from the storage node SN to the substrate (or P well).

The junction leak from the storage node SN and the gate insulating film leak (above (3) and (5)) are related to the strength of the electric field from the storage node SN. This electric field generally tends to increase as the impurity concentration of the diffusion layer (N-type impurity region) of storage node SN increases.
Since the impurity concentration of the diffusion layer of the storage node SN is set to the same concentration as the source / drain impurity region of the transistor of the logic circuit, a leakage current similar to that of the logic circuit occurs.

When “1” data is written in the storage node SN, if the voltage of the storage node SN leaks, the gate voltage of the amplifier transistor AT decreases, so that the driving capability of the amplifier transistor AT decreases, and erroneous reading is performed. Cause.
Therefore, in order to read out the write data accurately and at high speed, it is necessary to refresh the accumulated data. If the leak current is large, the voltage of the storage node SN drops quickly, so the refresh interval must be shortened, and the power consumption increases.

  The problem to be solved by the present invention is to reduce leakage from a storage node in a so-called gain cell DRAM cell.

  A semiconductor memory device according to the present invention includes a write transistor, a transfer transistor, an amplifier transistor, and a charge storage capacitor. The write transistor has one of a source / drain region connected to a write bit line and the other of the amplifier transistor. The transfer transistor has one of source and drain regions connected to the gate of the amplifier transistor, the other connected to the storage node electrode of the charge storage capacitor, and the gate connected to the gate. Connected to the transfer gate line, the drain of the amplifier transistor is connected to the read bit line, and the source is connected to the common source line.

  Another semiconductor memory device according to the present invention includes a write transistor, a transfer transistor, an amplifier transistor, a selection transistor, and a charge storage capacitor, and the write transistor has one of source and drain regions connected to a write bit line, and the other Is connected to the gate of the amplifier transistor, the gate is connected to the write word line, and the transfer transistor has one of the source and drain regions connected to the gate of the amplifier transistor and the other connected to the storage node electrode of the charge storage capacitor. Connected, the gate is connected to the transfer gate line, the drain of the amplifier transistor is connected to the source of the selection transistor, the source is connected to the common source line, the drain of the selection transistor is connected to the read bit line, Bets are connected to the read word line.

Another semiconductor memory device according to the present invention includes a write transistor, a transfer transistor, an amplifier transistor, a select transistor, a charge storage capacitor, and a boost capacitor, and one of the source and drain regions of the write transistor is connected to a write bit line. And the other is connected to one electrode of the boost capacitor, the gate is connected to the write word line, the transfer transistor has one of the source / drain regions connected to one electrode of the boost capacitor, and the other is the charge storage Connected to the storage node electrode of the capacitor, the gate is connected to the transfer gate line, the gate of the amplifier transistor is connected to the other electrode of the amplifier transistor, the drain is connected to the source of the selection transistor, and the source is the common source line Connect to Is, the drain of the selection transistor is connected to a read bit line, a gate connected to a read word line.
Preferably, the boost capacitor includes a MOS capacitor having a gate connected to the gate of the amplifier transistor and one of a source and a drain connected to a read word line.

The semiconductor memory device having the above configuration is different from the well-known 3T DRAM cell or 3T1C DRAM cell in the position of the storage node that holds the written charge.
In the 3T type DRAM cell or 3T1C type DRAM cell, a charge corresponding to data is held at a node where the source / drain region of the write transistor and the gate of the amplifier transistor are connected.
On the other hand, in the present invention, the charge corresponding to the data is held in the electrode (storage node electrode) of the charge storage capacitor that can be electrically cut off from the node by the transfer transistor. The storage node electrode is not connected to a transistor gate which has a large tendency to increase leakage as the scaling of the MOS device structure progresses. For this reason, the gate leak path is excluded from one of the leak occurrence paths.
The connection between the node and the storage node electrode is controlled by the operation of the transfer transistor. Therefore, if the voltage of the node is high to some extent, the voltage output from the storage node electrode is added and the amplifier transistor is easily turned on.

  The three configurations have a difference between having a selection transistor and further having a boosting capacitor that boosts (boosts) the voltage of the node at the time of reading.

The selection transistor is a switch that electrically cuts off the non-selected amplifier transistor from the read bit line at the time of writing. At the time of reading, the potential of the read bit line cannot be changed unless the bias setting is such that both the selection transistor and the amplifier transistor can be turned on.
At the time of data retention, the gate potential of the amplifier transistor is in a floating state, and a large unexpected potential change is likely to occur due to some factor (for example, noise or the like). On the other hand, since the gate of the selection transistor is connected to the read word line, it is controlled to a fixed potential. The ON operation of the selection transistor can be limited to a certain period of data reading that requires this, and is less susceptible to noise and the like.

In the case of having a boost capacitor, the voltage range in which the amplifier transistor can be turned on can be optimized according to the size of the capacitor and the write word line voltage.
In particular, when the boosting capacitor is composed of a MOS capacitor, it is possible to set such that a channel is formed in the MOS capacitor when the retained data is at a high level and a channel is not formed at a low level (for example, a threshold voltage). For this reason, the voltage difference before boosting according to the data is expanded after boosting. As a result, an operation margin for reliably turning on or off the amplifier transistor is increased, and malfunction is less likely to occur.

  According to the present invention, there is an advantage that leakage from the storage node is reduced.

[First Embodiment]
FIG. 1A shows an equivalent circuit of the DRAM cell of the first embodiment.
This embodiment is an example in which the well electrically connected to either the drain or the source of the transfer transistor is an N-type semiconductor. A memory cell array is formed by arranging the cells shown in FIG. 1A in a matrix, for example.

The DRAM cell shown in FIG. 1A includes three transistors, that is, a write transistor WT, a transfer transistor TT, and an amplifier transistor AT, and one charge storage capacitor (hereinafter referred to as a storage capacitor) C1.
One of the source / drain regions of the write transistor WT is connected to the write bit line WBL, and the other is connected to the gate of the amplifier transistor AT. One of the source / drain regions of the transfer transistor TT is connected to the gate of the amplifier transistor AT, the other is connected to one electrode of the storage capacitor C1, and the gate is connected to the transfer gate line TG. The drain of the amplifier transistor AT is connected to the read bit line RBL, and the source is connected to the common source line CSL.

FIG. 1B shows a cross-sectional structure of the transfer transistor TT and the storage capacitor C1.
The transfer transistor TT and the storage capacitor C1 are formed in a P-type semiconductor (for example, P well (PW)) 10 formed on a semiconductor substrate (not shown). The P well (PW) 10 serves as the other electrode (ground side electrode) of the storage capacitor C1 and the channel formation region of the transfer transistor TT.
Two N-type impurity regions, that is, an N well (NW) 11 and a source / drain region 12 are formed in the P well (PW) 10.

A gate electrode 14 of the transfer transistor TT is formed above the P well (PW) portion between the N well (NW) 11 and the source / drain region 12 via a gate insulating film 13. Insulating sidewalls 15 are formed on both side surfaces of the gate electrode 14.
An N-type low-concentration impurity region 16 is formed from the P well (PW) portion located below one edge of the gate electrode 14 into the source / drain region 12. Similarly, an N-type low-concentration impurity region 16 is formed from the P well (PW) portion located below the other edge of the gate electrode 14 into the N well (NW) 11. In general, such a low concentration impurity region 16 is referred to as an LDD region or an extension portion.
The source / drain region 12 is connected to the source / drain region of the write transistor WT of FIG. 1A and connected to one electrode of the storage capacitor C1 at a cross-sectional portion (not shown).

On the junction surface between the low concentration impurity region 16 on the opposite side of the source / drain region 12 and the P well (PW) 10 and the junction surface between the N well (NW) 11 and the P well (PW) 10 across the gate electrode 14. The formed junction capacitance constitutes the storage capacitor C1 of FIG.
In order to increase the capacity of the charge storage capacitor, it is necessary to have a wide junction surface, and the N well (NW) 11 is formed deep as shown in the figure. However, the N well (NW) 11 may be formed shallowly according to the required charge storage capacitor capacity.

In the structure of the impurity region shown in FIG. 1B, the N-type impurity concentration is high in the source / drain region 12 (denoted as N ⁺ ) and low in the N well (NW) 11 and the low concentration impurity region 16. The N well (NW) 11 preferably has an N type impurity concentration lower than that of the low concentration impurity region 16. The reason is that the concentration of the N well (NW) 11 occupying a large junction area is lowered to reduce the leakage of the junction constituting the storage capacitor C1. In that case, only the low concentration impurity region 16 on the storage capacitor C1 side can be omitted. This is to eliminate junction leakage at this portion.

The N well (NW) 11 is formed by ion implantation of N type impurities in the P well (PW) 10 (or P type substrate). The N well (NW) 11 can be formed together with the N well of the logic process. In that case, there is almost no increase in cost because there is no additional process to the logic process. However, even in that case, it is necessary to form a mask layer for ion implantation so that the N well (NW) 11 is not formed on the side where the source / drain region 12 is formed.
On the other hand, when adjusting the characteristics of the storage capacitor C1, that is, when ion implantation conditions not included in the logic process are used, an ion implantation step and an ion implantation mask layer forming step are added. That is, after the N well (NW) 11 is formed, the transfer transistor TT is formed. At this time, the mask layer is formed so that the same N-type impurity region as the source / drain region 12 is not formed on the N well (NW) 11 side. It is necessary to ion-implant the source / drain region 12 after forming the gate electrode. However, the increase in cost due to the increase in these steps accounts for a small percentage of the overall process cost.

A low concentration N-type impurity region (low concentration impurity region 16) connecting the transfer transistor TT and the N well (NW) 11 is also formed by ion implantation. This low-concentration N-type impurity region can be formed together with the LDD of the N-type MOS transistor in the logic process. In that case, there is no increase in cost because there is no additional process to the logic process.
Although it is conceivable to adjust the N-type impurity concentration of the low-concentration impurity region 16 for reasons such as improvement of leakage characteristics, the cost increase due to this is slight.

The operation of the DRAM cell of the first embodiment shown in FIG.
When "1" data is written to the cell, "1" data is set to the write bit line WBL, that is, its voltage is set to a high level. The power supply voltage Vdd is applied to the write word line WWL, and the transfer gate line TG is turned on, that is, raised to a high level. As a result, the write transistor WT and the transfer transistor TT are turned on, and charges are accumulated in the storage capacitor C1.
When writing “0” data, “0” data is set to the write bit line WBL, that is, its voltage is set to 0 [V]. The write word line WWL and transfer gate line TG are controlled in the same way as “1” data write. At this time, since the voltage of the write bit line WBL is 0 [V], no charge is accumulated in the storage capacitor C1.
Thereafter, when the write transistor WT and the transfer transistor TT are turned off, one electrode of the storage capacitor C1, which is the storage node SN, becomes electrically floating and enters a data holding state.

At the time of reading, the read bit line RBL is precharged to be electrically floating, the write transistor WT is turned off, the transfer gate line TG is raised to a high level, the transfer transistor TT is turned on, and the storage capacitor C1 is charged. Transfer to the gate of the amplifier transistor AT.
When “1” data is written, the amplifier transistor AT is turned on and the voltage of the read bit line RBL is lowered. However, when “0” data is written, the amplifier transistor AT is turned off, so that the read bit line RBL is turned off. The voltage on line RBL does not decrease.
By amplifying the change in the voltage of the read bit line RBL by a sense amplifier (not shown), “1” or “0” of the data written in the cell is read with a determinable level difference.

In the present embodiment, the cells shown in FIG. 1A may be arranged in a matrix, but if each cell has a 3T1C configuration, the cell area per bit increases.
Therefore, in this embodiment, it is desirable that the write bit line WBL is hierarchized into a main line and a sub line, and the write transistor WT and the amplifier transistor AT are shared by a plurality of N cells (N: an arbitrary natural number of 2 or more). .

FIG. 2 shows two basic configurations of a memory cell array in which the write transistor WT and the amplifier transistor AT are shared by N cells. This basic configuration is hereinafter referred to as a unit.
The first unit 1A includes one write transistor WT, one amplifier transistor AT, N transfer transistors TT (1), TT (2),... TT (N) and N storage capacitors C1 (1), C1 (2),... C1 (N).
A write bit line connected in the first unit 1A includes a main line WBLm1 and a sub line WBLs1.

One of the source / drain regions of the write transistor WT is connected to the main line WBLm1 of the write bit line, and the other is connected to the sub-line WBLs1 of the write bit line. A transfer transistor TT (1) and a storage capacitor C1 (1) are cascade-connected between a write bit line sub-line WBLs1 and a ground voltage (common source line: not shown). Similarly, the transfer transistor TT (2) and the storage capacitor C1 (2) are cascade-connected between the write bit line sub-line WBLs1 and the ground voltage, this is repeated, and finally the transfer transistor TT (N ) And the storage capacitor C1 (N) are cascade-connected.
The amplifier transistor AT has a gate connected to the write bit line sub-line WBLs1, a drain connected to the read bit line RBL1, and a source connected to the ground voltage.

A second unit 1B is provided in a region adjacent to the first unit 1A.
Similarly to the first unit 1A, the second unit 1B includes one write transistor WT, one amplifier transistor AT, N transfer transistors TT (1), TT (2),... TT (N) and N storages. · It has capacitors C1 (1), C1 (2), ... C1 (N).
A write bit line connected in the first unit 1A includes a main line WBLm2 and a sub line WBLs2.
The connection relationship between each transistor and the charge storage capacitor and the main line WBLm2 and the sub line WBLs2 is the same as the connection relationship with respect to the main line WBLm1 and the sub line WBLs1 of the first unit 1A.

  Each of the first and second units 1A and 1B can store 4 bits in a 6T4C unit, for example, when N = 4, and halves the number of transistors per bit compared to the 3T1C cell of FIG. There is an advantage that you can.

3A to 3F show operation timing charts of the first embodiment. Here, an operation of writing and reading data in a cell in the first unit 1A connected to the transfer gate line TG (1) is shown. Here, it is assumed that N = 4.
At the time of writing, since the voltage of the write bit line WBL is transferred to the storage capacitor C1, “power supply voltage Vdd + α” is applied to the gates of the write transistor WT and the transfer transistor TT.
At the time of reading, since the voltage of the storage capacitor C1 is transferred to the gate node of the amplifier transistor AT, “power supply voltage Vdd + α” is applied to the gate of the transfer transistor TT.
Note that the control for setting the gate applied voltage to “power supply voltage Vdd + α” as described above can also be applied to the cell operation of FIG.

The operation will be described below along the timing chart of FIG. 3 with reference to FIG.
As shown in FIG. 3B, data is set in the main line WBLm1 of the write bit line at time T1.
When writing “1” data to the cell, “1” data is set to the main line WBLm1, that is, its voltage is set to the high level. When writing “0” data, “0” data is set to the main line WBLm1, that is, its voltage is set to 0 [V].

  As shown in FIG. 3A, at time T2, “power supply voltage Vdd + α” is applied to the write word line WWL. As a result, as shown in FIG. 3E, in the case of “1” data write, the write transistor WT is turned on, so that the voltage of the sub-line WBLs1 rises to a high level (power supply voltage Vdd). On the other hand, when “0” data is written, the voltage of the sub-line WBLs1 remains 0 [V].

Subsequently, as shown in FIG. 3C, at time T3, the transfer gate line TG (1) is turned on, that is, raised to a high level.
As a result, when the sub-line WBLs1 is for writing “1” data at a high level, the transfer transistor TT is turned on, charges are transferred to the storage capacitor C1, and stored in the storage node SN (see FIG. 2). When the sub line WBLs1 is at the low level, the transfer transistor TT is not turned on, and the voltage of the storage node SN remains at the ground level ("0" data write).
Thereafter, when the write transistor WT and the transfer transistor TT are turned off, one electrode of the storage capacitor C1, which is the storage node SN, becomes electrically floating and enters a data holding state. As shown in FIG. 3E, when the voltage of the transfer gate line TG (1) is lowered, the data holding state is entered from there, but the voltage of the sub-line WBLs1 gradually decreases due to leakage.

At the time of reading, as shown in FIG. 3 (F), the read bit line RBL1 is raised to a high level (precharge) at time T4 to make it electrically floating.
Thereafter, the transfer gate line TG (1) is raised to a high level at a time T5 as shown in FIG.
Thereby, in the case of holding “1” data, the transfer transistor TT is turned on, and the charge stored in the charge storage capacitor electrode which is the storage node SN is transferred to the sub line WBLs1, and as shown in FIG. The voltage on the line WBLs1 rises. On the other hand, in the case of holding “0” data, the transfer transistor TT is not turned on, and the voltage of the sub line WBLs1 remains at a low level (ground voltage).

Since the sub line WBLs1 is connected to the gate of the amplifier transistor AT, at time T5, the amplifier transistor AT is turned on when “1” data is read, and is not turned on when “0” data is read. For this reason, as shown in FIG. 3F, the voltage of the read bit line RBL1 in the floating state is lowered to the ground voltage when “1” data is read, and is not lowered when “0” data is read.
By amplifying the voltage change of the read bit line RBL1 by a sense amplifier (not shown), “1” or “0” of the data written in the cell is read with a determinable level difference.

According to the first embodiment, data written in the cell is stored in one electrode (N well) of the storage capacitor C1 formed by the N well (NW) 11 and the P well (PW) 10 shown in FIG. (NW) 11: accumulated in storage node SN). Since both N-well (NW) 11 and P-well (PW) 10 have low impurity concentrations, junction leakage is small. Therefore, the charge retention time of the storage node SN can be increased from several seconds to several hundred seconds.
Therefore, it is possible to increase the voltage increase amount of the sub-line WBLs1 at the time of reading “1” data that increases at time T5 in FIG. 3E, and to achieve reliable operation.

As shown in FIG. 1B, the transfer transistor TT and the N well (NW) 11 are electrically connected through a low impurity concentration N-type impurity region (low concentration impurity region 16). The junction leakage at this portion can be similarly reduced. If the depth of the N-well (NW) 11 is about 1 [μm], for example, the junction capacitance between the N-well (NW) 11 and the P-well (PW) 10 can be about several [fF] depending on the concentration. It is done.
The configuration of the transfer transistor TT and the charge storage capacitor C is represented by the same equivalent circuit as the well-known 1T1C type DRAM.

  In the 1T1C type DRAM cell shown in FIG. 16, in order to turn on the amplifier transistor AT in order to discharge the precharge charge of the read bit line (RB) at the time of reading “1” data, the storage capacitor C1 has several tens [fF ] Capacity is required.

On the other hand, in the present embodiment, the write bit lines are hierarchized, and at the time of reading “1” data, the capacity of the sub-line WBLs1 is charged with the accumulated charge read from the storage node SN. Since the sub-line WBLs1 is charged when “1” data is written and is in a floating state, the charge read from the storage node SN is added to the charge, and the gate bias voltage of the amplifier transistor AT is added based on the total charge amount. Is generated. That is, as shown in FIG. 3E, in the case of “1” data reading, the voltage of the sub-line WBLs1 is lowered due to leakage at a time immediately before time T5, but is at a somewhat high level, and at time T5, Further, a storage node SN voltage is added by reading the cell.
From the above, if the capacitance of the storage capacitor C1 itself is several [fF], the amplifier transistor AT can be reliably turned on when “1” data is read. Since the storage capacitor C1 exists for each cell, it is advantageous for reducing the cell area that the capacity is small.

Since charges are transferred to the sub-line WBLs1 at the time of reading, a leak from the sub-line WBLs1, that is, a junction leak, a gate insulating film leak of the amplifier transistor AT, and an off-leak of the write transistor WT occur at the time of reading.
However, since the reading time is as short as several nanoseconds, the leakage during reading does not affect the data reading operation.

Furthermore, in this case, as shown in FIG. 2, when cells are arranged in an array, the write transistor WT and the amplifier transistor AT can be shared by a plurality of cells.
The cell configuration in this case is such that a plurality of N storage portions similar to the DRAM including the transfer transistor TT and the storage capacitor C1 are connected to the gate of the amplifier transistor AT. When N = 4, the number of transistors per bit can be halved as described above. As N increases, the number of transistors per bit can be reduced accordingly, and the capacity of the sub-line WBLs1 also increases. However, the ratio of the voltage change due to “1” data reading to the gate voltage of the amplifier transistor AT is increased. As a result, the bias design for turning on or off the amplifier transistor AT becomes difficult. In that sense, the number of N needs to be optimized.

[Second Embodiment]
FIG. 4 shows an equivalent circuit of the DRAM cell of the second embodiment.
In the cell of the second embodiment, a selection transistor ST is added.
One of the source / drain regions of the select transistor ST is connected to the read bit line RBL, and the other is connected to one of the source / drain regions of the amplifier transistor AT. The other of the source / drain regions of the amplifier transistor AT is connected to the ground voltage (common source line CSL) as in the first embodiment.
The gate of the selection transistor ST is connected to the read word line RWL.
Since other structures are the same as those in FIG. 1A, description thereof is omitted here.

  In the cell of FIG. 1A without the selection transistor ST, only the amplifier transistor AT exists between the read bit line RBL and the common source line CSL. For this reason, erroneous reading may occur if the gate voltage of the amplifier transistor AT is in a floating state and deviates from a predetermined voltage range defining “1” or “0” data for some reason. Further, the amplifier transistor AT is also turned on when “1” data is written.

  In the cell shown in FIG. 4, the read bit line RBL is connected to the common source line CSL only when “1” data is read, and erroneous reading of unselected cells connected to the same read bit line RBL is prevented. A selection transistor ST is added for the purpose.

The operation of the DRAM cell of the second embodiment shown in FIG. 4 will be described.
Since the data write operation is the same as that in the case of the cell in FIG. 1A, description thereof is omitted here.

At the time of reading, the read bit line RBL is precharged to be electrically floating, the write transistor WT is turned off, the transfer gate line TG is raised to a high level, the transfer transistor TT is turned on, and the storage capacitor C1 is charged. Transfer to the gate of the amplifier transistor AT.
When “1” data is written, the amplifier transistor AT is turned on. However, since the selection transistor ST is turned off at this time, the read bit line RBL and the common source line CSL are not electrically connected. It remains. Subsequently, the voltage of the read word line RWL is raised to a high level (for example, the power supply voltage Vdd), and the selection transistor ST is turned on. As a result, the read bit line RBL and the common source line CSL become conductive, and the voltage of the read bit line RBL decreases.
On the other hand, when "0" data is written, the voltage of the read word line RWL is raised, and even if the selection transistor ST is turned on, the amplifier transistor AT remains off. Will not drop.
By amplifying the change in the voltage of the read bit line RBL by a sense amplifier (not shown), “1” or “0” of the data written in the cell is read with a determinable level difference.

  Also in the present embodiment, it is desirable that the write bit line WBL is hierarchized into a main line and a sub line as in the first embodiment. At this time, in addition to the write transistor WT and the amplifier transistor AT, the selection transistor ST is preferably shared by a plurality of N cells (N: an arbitrary natural number of 2 or more).

FIG. 5 shows a basic configuration (unit) 1C of a memory cell array in which the write transistor WT, the amplifier transistor AT, and the selection transistor ST are shared.
In the illustrated unit 1C, as compared with the first unit 1A of the first embodiment shown in FIG. 2, a selection transistor ST is added between the read bit line RBL and the amplifier transistor AT. A read word line RWL is connected to the gate of the selection transistor ST.
Other configurations are the same as those in FIG. 2, and a description thereof is omitted here.
Similar to the first embodiment, units having the same configuration as the unit 1C of FIG. 5 are arranged in a matrix to form a memory cell array.

  For example, when N = 4, the unit 1C has an advantage that four bits can be stored in a 7T4C unit, and the number of transistors per bit can be reduced by about 40% compared to the 3T1C cell of FIG.

6A to 6G show operation timing charts of the second embodiment. Here, an operation of writing and reading data in a cell in the unit 1C connected to the transfer gate line TG (1) is shown. Here, it is assumed that N = 4.
The write operation is performed as in the first embodiment.

The read operation is the same until time T5 in FIG.
That is, as shown in FIG. 6G, at time T4, the read bit line RBL is raised to a high level (precharge), and is electrically floating.
Thereafter, the transfer gate line TG (1) is raised to the high level at time T5 as shown in FIG. 6C while the write transistor WT is kept in the OFF state.
As a result, in the case of holding “1” data, the transfer transistor TT is turned on, and the charge stored in the charge storage capacitor electrode, which is the storage node SN, is transferred to the sub-line WBLs1, and as shown in FIG. The voltage on the line WBLs1 rises. On the other hand, in the case of holding “0” data, the transfer transistor TT is not turned on, and the voltage of the sub line WBLs1 remains at a low level (ground voltage).

Although the sub-line WBLs1 is connected to the gate of the amplifier transistor AT, the selection transistor ST is still turned off at time T5, so that not only “0” data reading but also “1” data reading is performed. At this time, the read bit line RBL and the common source line CSL remain non-conductive.
In the second embodiment, as a new procedure, as shown in FIG. 6E, the voltage of the read word line RWL is raised to a high level, for example, the power supply voltage Vdd at time T6.
As a result, only when “1” data is read, both the selection transistor ST and the amplifier transistor AT are turned on, and the voltage of the read bit line RBL in the floating state is lowered to the ground voltage. On the other hand, when “0” data is read, the voltage of the read bit line RBL does not decrease.
By amplifying the voltage change of the read bit line RBL1 by a sense amplifier (not shown), “1” or “0” of the data written in the cell is read with a determinable level difference.

The structure of the impurity region forming the capacitor of the second embodiment is the same as that of FIG. 1B of the first embodiment.
Therefore, the leakage of the storage node SN is small, and the charge retention time can be increased from several seconds to several hundred seconds. For this reason, the voltage increase amount of the sub-line WBLs1 at the time of reading “1” data that increases at time T6 in FIG. 6E can be increased, and reliable operation can be achieved.
Further, the impurity concentration of the low-concentration impurity region 16 is small, and the junction leakage in this portion can be similarly reduced.
As described above, the junction capacitance between the N well (NW) 11 and the P well (PW) 10 can be set to several [fF].

  Similarly to the first embodiment, the charge read from the storage node SN is added to the charge of the sub line WBLs1, and the gate bias voltage of the amplifier transistor AT is generated based on the total charge amount. Therefore, if the capacity itself of the storage capacitor C1 is several [fF], the amplifier transistor AT can be reliably turned on when “1” data is read. Since the storage capacitor C1 exists for each cell, it is advantageous for reducing the cell area that the capacity is small.

As an advantage peculiar to the second embodiment, since the selection transistor ST is provided, even when the gate voltage of the amplifier transistor AT changes beyond an assumed range for some reason, the data reading is surely performed and a malfunction is caused. Can be prevented. Further, the amplifier transistor AT is not turned on when data is written.
This selection transistor ST can be shared by a plurality of N cells together with the write transistor WT and the amplifier transistor AT. In this case, as described above, the number of transistors per bit can be reduced, and the area and cost can be reduced.

[Third Embodiment]
FIG. 7 shows an equivalent circuit of the DRAM cell of the third embodiment. FIG. 8 shows a basic configuration (unit) 1D of a memory cell array in which the write transistor WT, the amplifier transistor AT, the selection transistor ST, and the boost capacitor C2 are shared.
In the third embodiment, a boost capacitor C2 is added to the second embodiment of FIG.
The step-up capacitor C2 is composed of a MOS capacitor in this example. Specifically, the gate of the capacitor MOS transistor is connected to the gate of the amplifier transistor AT, the drain is connected to the read word line RWL, and the source is open.
The step-up transistor C2 may be formed from a normal MIM type capacitor.

By the way, since the storage capacitor C1 of the present embodiment is formed of a low concentration impurity region, the leakage current is small as described above. Further, the voltage of the amplifier transistor AT is already high to some extent before reading, and the charge from the storage node SN is added to this when reading.
For this reason, the boost capacitor C2 is used auxiliary when it is desired to further increase the voltage of the amplifier transistor AT. Therefore, the booster capacitor C2 has a relatively small capacitance value, and a MOS capacitor is sufficient, and an increase in area can be minimized.

By adding the boost capacitor C2, the gate voltage of the amplifier transistor AT at the time of writing “1” data is boosted, so that the read margin of the amplifier transistor AT is improved.
The other configuration in FIG. 7 is similar to that in FIG.

The operation of the DRAM cell of the third embodiment shown in FIG. 7 will be described.
The data write operation is the same as that in the case of the cell shown in FIG.

At the time of reading, the read bit line RBL is precharged to be electrically floating, the write transistor WT is turned off, the transfer gate line TG is raised to a high level, the transfer transistor TT is turned on, and the storage capacitor C1 is charged. Transfer to the gate of the amplifier transistor AT.
When “1” data is written, the amplifier transistor AT is turned on. However, since the selection transistor ST is turned off at this time, the read bit line RBL and the common source line CSL are not electrically connected. It remains. Subsequently, the voltage of the read word line RWL is raised to a high level (for example, the power supply voltage Vdd), and the selection transistor ST is turned on. As a result, the read bit line RBL and the common source line CSL are electrically connected, so that the voltage of the read bit line RBL decreases. At this time, the gate voltage of the amplifier transistor AT coupled to the read word line RWL via the boost capacitor C2 is boosted, and the amplifier transistor AT is more reliably turned on.
On the other hand, when "0" data is written, the voltage of the read word line RWL is raised, and even if the selection transistor ST is turned on, the amplifier transistor AT remains off. Will not drop. At this time, the gate voltage of the amplifier transistor AT is also boosted, but the amplifier transistor AT cannot be turned on because the voltage before boosting is low.

In such a read operation, the amplifier transistor AT is turned on and not turned on, but the capacitance value is determined so that the boost capacitor C2 functions properly as necessary.
By amplifying the change in the voltage of the read bit line RBL by a sense amplifier (not shown), “1” or “0” of the data written in the cell is read with a determinable level difference.

Another advantage of forming the boost capacitor C2 from a MOS capacitor is that the MOS capacitance value is variable when “1” data is read and when “0” data is read.
That is, when “1” data is written, the channel of the MOS transistor to be the boost capacitor C2 is formed, and therefore the coupling between the read word line RWL and the gate node of the amplifier transistor AT is as described above. A channel capacitance is added to the overlap capacitance between the drain and gate of the MOS transistor and the fringing capacitance caused by the coupling between the gate and the wiring of the read word line RWL, and a large coupling is generated.
On the other hand, when “0” data is written, since channel capacity is not added, the coupling is relatively small.
Therefore, the gate voltage of the amplifier transistor AT greatly increases when “1” data is read, and the gate voltage increases only slightly when “0” data is read. That is, the gate voltage margin of whether the amplifier transistor AT is turned on or off with “1” data and “0” data is expanded, and malfunction is less likely to occur.

  Also in the present embodiment, it is desirable that the write bit line WBL is hierarchized into a main line and a sub line as in the first embodiment. At this time, in addition to the write transistor WT, the amplifier transistor AT, and the select transistor ST, it is desirable that the boost capacitor C2 is also shared by a plurality of N cells (N: an arbitrary natural number of 2 or more).

Compared with the unit 1C of the second embodiment shown in FIG. 5, the unit 1D shown in FIG. 8 has an additional boost capacitor C2 between the sub-line WBLs1 connected to the gate of the amplifier transistor AT and the read word line RWL. Has been. The gate of the MOS transistor serving as the boost capacitor C2 is connected to the sub-line WBLs1, the drain is connected to the read word line RWL, and the source is open.
Other configurations are the same as those in FIG. 5, and a description thereof is omitted here.
Similar to the first embodiment, units having the same configuration as the unit 1D of FIG. 8 are arranged in a matrix to form a memory cell array.

  For example, when N = 4, the unit 1D has an advantage that four bits can be stored in an 8T4C unit, and the number of transistors per bit can be reduced by about 30% compared to the 3T1C cell of FIG.

9A to 9G show operation timing charts of the third embodiment. Here, an operation of writing and reading data in a cell in the unit 1D connected to the transfer gate line TG (1) is shown. Here, it is assumed that N = 4.
The write operation is performed as in the first embodiment.

The read operation is the same until time T5 in FIG.
That is, as shown in FIG. 9G, at time T4, the read bit line RBL is raised to a high level (precharge) to be in an electrical floating state.
Thereafter, the transfer gate line TG (1) is raised to a high level at a time T5 as shown in FIG.
Thereby, in the case of holding “1” data, the transfer transistor TT is turned on, and the charge stored in the charge storage capacitor electrode as the storage node SN is transferred to the sub-line WBLs1, and as shown in FIG. The voltage on the line WBLs1 rises. On the other hand, in the case of holding “0” data, the transfer transistor TT is not turned on, and the voltage of the sub line WBLs1 remains at a low level (ground voltage).

Next, as shown in FIG. 9E, at time T7, the voltage of the read word line RWL is raised to a high level, for example, the power supply voltage Vdd. This is the same as in the second embodiment (FIG. 6E, in this case, time T6).
However, since it is necessary to perform boosting in the third embodiment, as shown in FIG. 9C, the voltage of the transfer gate line TG (1) is lowered at the previous time T5 and the amplifier transistor AT is turned on. The gate (sub line WBLs1) is brought into a floating state.

When the read word line RWL is raised at time T7, in the case of “1” data read, the voltage of the sub-line WBLs1 further increases as shown in FIG. 9F. At this time, in the case of reading “0” data, the voltage of the sub-line WBLs1 rises, but the rise amount is slight.
As a result, only when “1” data is read, both the selection transistor ST and the amplifier transistor AT are turned on, and the voltage of the read bit line RBL in the floating state is lowered to the ground voltage. On the other hand, when “0” data is read, the voltage of the read bit line RBL does not decrease.
By amplifying the voltage change of the read bit line RBL1 by a sense amplifier (not shown), “1” or “0” of the data written in the cell is read with a determinable level difference.

The configuration of the impurity region forming the capacitor of the third embodiment is the same as that of FIG. 1B of the first embodiment.
Therefore, the leakage of the storage node SN is small, and the charge retention time can be increased from several seconds to several hundred seconds. For this reason, the voltage increase amount of the sub-line WBLs1 at the time of reading “1” data that increases at time T7 in FIG. 9E can be increased, and a reliable operation can be achieved.
Further, the impurity concentration of the low-concentration impurity region 16 is small, and the junction leakage in this portion can be similarly reduced.
As described above, the junction capacitance between the N well (NW) 11 and the P well (PW) 10 can be set to several [fF].

  Similarly to the first embodiment, the charge read from the storage node SN is added to the charge of the sub line WBLs1, and the gate bias voltage of the amplifier transistor AT is generated based on the total charge amount. Therefore, if the capacity itself of the storage capacitor C1 is several [fF], the amplifier transistor AT can be reliably turned on when “1” data is read. Since the storage capacitor C1 exists for each cell, it is advantageous for reducing the cell area that the capacity is small.

  As advantages similar to the second embodiment, since the selection transistor ST is provided, it is possible to reliably read data and prevent malfunction. Further, the amplifier transistor AT is not turned on when data is written.

The advantage peculiar to the third embodiment is that the voltage of the amplifier transistor AT is boosted through the boost capacitor C2 connected to the gate (sub line WBLs1).
When the boost capacitor C2 is composed of a MOS capacitor, the voltage difference of the gate voltage of the amplifier transistor AT can be expanded between “1” data reading and “0” data reading by boosting.
The boost capacitor C2 can be shared by a plurality of N cells together with the write transistor WT, the amplifier transistor AT, and the select transistor ST. In this case, as described above, the number of transistors per bit can be reduced, and the area and cost can be reduced.

<Modification>
10 to 14 show modified examples of the structure of the storage capacitor C1 applicable to the first to third embodiments.

In the first modification shown in FIG. 10, N-type impurities are ion-implanted into the N well (NW) 11 to form a high concentration impurity region 17 having an impurity concentration higher than that of the N well (NW) 11. .
When the high-concentration impurity region 17 is formed, the resistance from the N well (NW) 11 to the transfer transistor TT can be reduced, so that the time required for charging and discharging the charge in the N well (NW) 11 can be shortened. In order not to increase the junction leak with the P well (PW) 10, the high concentration impurity region 17 formed here is formed so as not to contact the P well (PW) 10.

  In the second modification shown in FIG. 11, a part of the gate electrode 14 of the transfer transistor TT is connected to the gate insulating film 13 so that the channel formation region of the transfer transistor TT and the N well (NW) 11 are in contact with each other. Via the N well (NW) 11. In this structure, there is no low concentration N-type impurity region (low concentration impurity region 16) connecting the transfer transistor TT and the N well (NW) 11. Therefore, junction leakage between the low concentration impurity region 16 and the P well (PW) 10 can be eliminated.

  An N inversion layer (channel) is formed on the surface of the P well (PW) 10 only when a high level voltage is applied to the gate of the transfer transistor TT at the time of writing or reading, and the N well (NW) overlapping the gate electrode 14 An N-type accumulation layer is formed in the portion 11. The charge is charged and discharged in the N well (NW) 11 through the accumulation layer.

  In the third modification shown in FIG. 12, in the second modification described above, N-type impurities are ion-implanted into the N well (NW) 11, and the impurity concentration is higher than that of the N well (NW) 11. Impurity regions 17 are formed. As a result, the time required to charge and discharge the charges in the N well (NW) 11 can be shortened. In order not to increase the junction leak with the P well (PW) 10, the N-type impurity region formed here is formed so as not to contact the P well (PW) 10.

The fourth modification shown in FIG. 13 is obtained by adding a low concentration impurity region 16 to the second modification shown in FIG.
The transfer transistor TT and the N well (NW) 11 are connected by a low concentration N-type impurity region 16, and a part of the gate electrode 14 of the transfer transistor TT is connected to the N well (NW) 11 via the gate insulating film 13. It is layered on top.

The fifth modification shown in FIG. 14 is obtained by adding a low concentration impurity region 16 to the third modification shown in FIG.
The transfer transistor TT and the N well (NW) 11 are connected by a low concentration N-type impurity region 16, and a part of the gate electrode 14 of the transfer transistor TT is connected to the N well (NW) 11 via the gate insulating film 13. It is layered on top.
Further, an N-type impurity is ion-implanted into the N well (NW) 11 to form a high concentration impurity region 17 having an impurity concentration higher than that of the N well (NW) 11. As a result, the time required to charge and discharge the charges in the N well (NW) 11 can be shortened. In order not to increase the junction leak with the P well (PW) 10, the N-type impurity region formed here is formed so as not to contact the P well (PW) 10.

  According to the embodiment of the present invention, charges are accumulated in the storage capacitor C1 connected via the transfer transistor TT. The storage capacitor C1 is formed by a P well (PW) 10 and an N well (NW) 11 formed in the P well (PW) 10. The transfer transistor TT and the N well (NW) 11 are electrically connected through an N-type impurity region having a low impurity concentration. Since both the N well (NW) 11 and the P well (PW) 10 have a low impurity concentration, the junction leakage current is small. As a result, the charge retention time becomes longer. Depending on the impurity concentration of the N well (NW) 11 and the P well (PW) 10, the size of the N well (NW) 11, and other manufacturing process conditions, the charge retention time can be several seconds to several hundred seconds. Is possible. A long charge retention time has the advantage that the refresh cycle can be lengthened, which contributes to a reduction in power consumption during data retention.

(A) is an equivalent circuit diagram of the DRAM cell of the first embodiment, and (B) is a partial sectional view of the cell. It is a circuit diagram for two units in which some transistors are shared by N cells. (A)-(F) are the operation | movement timing charts of 1st Embodiment. It is an equivalent circuit diagram of the DRAM cell of the second embodiment. It is a circuit diagram for two units in which some transistors are shared by N cells. (A)-(G) are the operation | movement timing charts of 2nd Embodiment. It is an equivalent circuit diagram of the DRAM cell of the third embodiment. It is a circuit diagram for two units in which some transistors are shared by N cells. (A)-(G) are the operation | movement timing charts of 3rd Embodiment. It is a fragmentary sectional view of the cell of the 1st modification. It is a fragmentary sectional view of the cell of the 2nd modification. It is a fragmentary sectional view of the cell of the 3rd modification. It is a fragmentary sectional view of the cell of the 4th modification. It is a fragmentary sectional view of the cell of the 5th modification. This is an equivalent circuit of a 3T type DRAM cell of the type proposed in Patent Document 1. 3 is an equivalent circuit of a 3T1C type DRAM cell of the type described in Patent Document 2.

Explanation of symbols

  1A, 1B, 1C, 1D ... unit, 10 ... P well (PW), 11 ... N well (NW), 12 ... source / drain region, 14 ... gate electrode, 16 ... low concentration impurity region, 17 ... high concentration impurity Area, WT ... write transistor, TT ... transfer transistor, AT ... amplifier transistor, ST ... select transistor, C1 ... storage capacitor, C2 ... boost capacitor, WWL ... write word line, RWL ... read word line, WBL ... write bit line , WBLm1 ... main line, WBLs1 ... sub line, RBL ... read bit line, CSL ... common source line, TG ... transfer gate line, SN ... storage node

Claims (15)

A write transistor, a transfer transistor, an amplifier transistor and a charge storage capacitor;
In the write transistor, one of a source / drain region is connected to a write bit line, the other is connected to a gate of the amplifier transistor, a gate is connected to a write word line,
In the transfer transistor, one of the source / drain regions is connected to the gate of the amplifier transistor, the other is connected to the storage node electrode of the charge storage capacitor, the gate is connected to the transfer gate line,
A semiconductor memory device, wherein a drain of the amplifier transistor is connected to a read bit line, and a source is connected to a common source line. A memory cell array including a plurality of memory cells;
Within the memory cell array,
For the node where the other source / drain region of the write transistor and the gate of the amplifier transistor are connected in common, the transfer transistor connecting one source / drain region to the node is N (N: 2 The above natural numbers) are provided in parallel,
The charge storage capacitor is connected to each of the other source / drain regions of the N transfer transistors,
The transfer transistor and the charge storage capacitor are provided for each memory cell,
The semiconductor memory device according to claim 1, wherein the write transistor and the amplifier transistor are shared by N memory cells. N memory cells sharing the write transistor and the amplifier transistor are set as one unit, and a plurality of units are arranged in a matrix in the memory cell,
The write bit line comprises a main line and a sub line,
The main line is shared by a plurality of units arranged in one direction,
The semiconductor memory device according to claim 2, wherein the sub-line constitutes the node and is provided for each unit. The transfer transistor is
A well made of a first conductivity type semiconductor;
Two source / drain regions made of a second conductivity type semiconductor opposite to the first conductivity type semiconductor and separated from each other in the well,
One of the two source / drain regions forms the storage node electrode of the charge storage capacitor;
The semiconductor memory device according to claim 1, wherein the well joined to the one source / drain region also serves as a fixed potential electrode of the charge storage capacitor. A high-concentration impurity region having the same second conductivity type as the one source / drain region forming the storage node electrode and having a higher concentration than the one source / drain region is formed in the one source / drain region. The semiconductor memory device according to claim 4, wherein the semiconductor memory device is formed at a position not in contact with the well. A part of the one source / drain region forming the storage node electrode overlaps with the gate electrode of the transfer transistor in a plane pattern, and the second conductivity type impurity concentration of the one source / drain region is set to the other source / drain region. The semiconductor memory device according to claim 4, wherein the concentration is lower than a second conductivity type impurity concentration in the drain region. A writing transistor, a transfer transistor, an amplifier transistor, a selection transistor and a charge storage capacitor;
In the write transistor, one of a source / drain region is connected to a write bit line, the other is connected to a gate of the amplifier transistor, a gate is connected to a write word line,
In the transfer transistor, one of the source / drain regions is connected to the gate of the amplifier transistor, the other is connected to the storage node electrode of the charge storage capacitor, the gate is connected to the transfer gate line,
The drain of the amplifier transistor is connected to the source of the selection transistor, the source is connected to a common source line,
A semiconductor memory device, wherein a drain of the selection transistor is connected to a read bit line, and a gate is connected to a read word line. A memory cell array including a plurality of memory cells;
Within the memory cell array,
For the node where the other source / drain region of the write transistor and the gate of the amplifier transistor are connected in common, the transfer transistor connecting one source / drain region to the node is N (N: 2 The above natural numbers) are provided in parallel,
The charge storage capacitor is connected to each of the other source / drain regions of the N transfer transistors,
The transfer transistor and the charge storage capacitor are provided for each memory cell,
The semiconductor memory device according to claim 7, wherein the write transistor, the amplifier transistor, and the selection transistor are shared by N memory cells. N memory cells sharing the write transistor, the amplifier transistor, and the selection transistor are set as one unit, and a plurality of units are arranged in a matrix in the memory cell,
The write bit line comprises a main line and a sub line,
The main line is shared by a plurality of units arranged in one direction,
The semiconductor memory device according to claim 8, wherein the sub-line constitutes the node and is provided for each unit. The transfer transistor is
A well made of a first conductivity type semiconductor;
Two source / drain regions made of a second conductivity type semiconductor opposite to the first conductivity type semiconductor and separated from each other in the well,
One of the two source / drain regions forms the storage node electrode of the charge storage capacitor;
The semiconductor memory device according to claim 7, wherein the well joined to the one source / drain region also serves as a fixed potential electrode of the charge storage capacitor. A write transistor, a transfer transistor, an amplifier transistor, a select transistor, a charge storage capacitor and a boost capacitor;
The write transistor has one of source / drain regions connected to a write bit line, the other connected to one electrode of the boost capacitor, and a gate connected to a write word line,
The transfer transistor has one of source / drain regions connected to one electrode of the boost capacitor, the other connected to a storage node electrode of the charge storage capacitor, and a gate connected to a transfer gate line,
The gate of the amplifier transistor is connected to the other electrode of the amplifier transistor, the drain is connected to the source of the selection transistor, the source is connected to a common source line,
A semiconductor memory device, wherein a drain of the selection transistor is connected to a read bit line, and a gate is connected to a read word line. The semiconductor memory device according to claim 11, wherein the boosting capacitor includes a MOS capacitor having a gate connected to a gate of the amplifier transistor and one of a source and a drain connected to a read word line. A memory cell array including a plurality of memory cells;
Within the memory cell array,
For a node where the other source / drain region of the write transistor and one electrode of the boost capacitor are commonly connected, the transfer transistor connecting one source / drain region to the node is N (N: Two or more natural numbers) in parallel,
The charge storage capacitor is connected to each of the other source / drain regions of the N transfer transistors,
The transfer transistor and the charge storage capacitor are provided for each memory cell,
The semiconductor memory device according to claim 11, wherein the write transistor, the amplifier transistor, the selection transistor, and the boost capacitor are shared by N memory cells. N memory cells sharing the write transistor, the amplifier transistor, the selection transistor, and the boost capacitor are defined as one unit, and a plurality of units are arranged in a matrix in the memory cell,
The write bit line comprises a main line and a sub line,
The main line is shared by a plurality of units arranged in one direction,
The semiconductor memory device according to claim 13, wherein the sub-line constitutes the node and is provided for each unit. The transfer transistor is
A well made of a first conductivity type semiconductor;
Two source / drain regions made of a second conductivity type semiconductor opposite to the first conductivity type semiconductor and separated from each other in the well,
One of the two source / drain regions forms the storage node electrode of the charge storage capacitor;
The semiconductor memory device according to claim 11, wherein the well joined to the one source / drain region also serves as a fixed potential electrode of the charge storage capacitor.

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