JP2020202005A - Semiconductor device - Google Patents

Abstract

To provide a novel semiconductor device with high reliability.SOLUTION: A semiconductor device includes a first transistor, a second transistor, a first capacitor element, and a second capacitor element. One of a source and a drain of the first transistor, one electrode of the first capacitor element, and a gate of the second transistor are electrically connected to each other. One of a source and a drain of the second transistor, one electrode of the second capacitor element, and a gate of the first transistor are electrically connected to each other.SELECTED DRAWING: Figure 1

Description

One aspect of the present invention relates to a semiconductor device and a display system.

One aspect of the present invention is not limited to the above technical fields. The technical fields of one aspect of the present invention disclosed in the present specification and the like include semiconductor devices, display devices, light emitting devices, power storage devices, storage devices, display systems, electronic devices, lighting devices, input devices, input / output devices, and the like. As an example, a method of driving the above or a method of manufacturing them can be mentioned.

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. Transistors, semiconductor circuits, arithmetic units, storage devices, and the like are aspects of semiconductor devices. Further, an imaging device, an electro-optical device, a power generation device (including a thin-film solar cell, an organic thin-film solar cell, etc.), and an electronic device may have a semiconductor device.

In recent years, central processing units (Central Processing U) have been applied to various electronic devices such as personal computers, smartphones, and digital cameras.
Electronic components such as nits (CPUs), storage devices, and sensors are used.

Patent Document 1 describes a storage device composed of a transistor using an oxide semiconductor and a transistor using single crystal silicon. Further, it is described that the off-current of the transistor using the oxide semiconductor is extremely small.

Japanese Unexamined Patent Publication No. 2012-256400

One aspect of the present invention is to provide a novel semiconductor device. Alternatively, one aspect of the present invention is
An object is to provide a semiconductor device having good reliability. Alternatively, one aspect of the present invention is to provide a semiconductor device having low power consumption.

It should be noted that one aspect of the present invention does not necessarily have to solve all of the above problems, as long as it can solve at least one problem. Moreover, the description of the above-mentioned problem does not prevent the existence of other problem. Issues other than these are self-evident from the description of the description, claims, drawings, etc., and from the description of the specification, claims, drawings, etc.
It is possible to extract issues other than these.

One aspect of the present invention includes a first transistor and a second transistor, a first capacitive element and a second capacitive element, and one of the source or drain of the first transistor and the first capacitive element. One electrode and the gate of the second transistor are electrically connected, and one of the source or drain of the second transistor, one electrode of the second capacitive element, and the gate of the first transistor. Is an electrically connected semiconductor device.

Further, in the semiconductor device according to one aspect of the present invention, one of the source or drain of the first transistor, one electrode of the first capacitive element, and the gate of the second transistor are connected to the first node. The source or drain of the second transistor, one electrode of the second capacitive element, and the gate of the first transistor are electrically connected at the second node. , The first potential may be held in the first node and the second potential may be held in the second node.

Further, the semiconductor device according to one aspect of the present invention does not hold the second potential when holding the first potential, and holds the first potential when holding the second potential. You don't have to.

Further, in the semiconductor device according to one aspect of the present invention, when the first potential is held, the potential is applied to one of the source and drain of the first transistor and the gate of the second transistor.
When holding the second potential, the potential may be applied to either the source or drain of the second transistor and the gate of the first transistor.

Further, in the semiconductor device according to one aspect of the present invention, the gate insulator of the first transistor may be used.
Potentials of opposite polarities are applied when the first potential is held and when the second potential is held, and the gate insulator of the second transistor is subjected to the first potential holding and the second potential. When the potential is held,
Potentials of opposite polarities may be applied.

Further, in the semiconductor device according to one aspect of the present invention, the first transistor and the second transistor may use a metal oxide.

Further, the semiconductor device according to one aspect of the present invention has a first drive circuit, a second drive circuit, and first to fourth wirings, and is the other of the source or drain of the first transistor. And the first
Is electrically connected to the wiring of the second transistor, the other of the source or drain of the second transistor, and the second
The wiring is electrically connected to the other electrode of the first capacitance element, and the third wiring is electrically connected to the other electrode of the second capacitance element, and the fourth wiring is Electrically connected, the first drive circuit has the function of controlling the potentials of the first wiring and the second wiring, and the second drive circuit is
It may have a function of controlling the potential of the third wiring and the fourth wiring.

Further, the display system according to one aspect of the present invention includes a control circuit having a frame memory using the above semiconductor device, an image processing unit, and a drive circuit, and a display unit, and the frame memory stores image data. It has a function of storing, the image processing unit has a function of performing image processing on the image data input from the frame memory and generating a video signal, and the drive circuit has the above-mentioned video signal input from the image processing unit. Has a function of outputting to the display unit.

Further, in the display system according to one aspect of the present invention, the display unit includes a first display unit and a second display unit, and the first display unit has a reflective liquid crystal element. , The second display unit may have a light emitting element.

According to one aspect of the present invention, a novel semiconductor device can be provided. Alternatively, one aspect of the present invention can provide a semiconductor device having good reliability. Alternatively, according to one aspect of the present invention, a semiconductor device having low power consumption can be provided.

The description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not necessarily have all of these effects. Effects other than these are self-evident from the description of the description, claims, drawings, etc.
It is possible to extract effects other than these from the description of claims, drawings, and the like.

The figure which shows the structural example of the semiconductor device which concerns on one aspect of this invention, and the figure which shows the structural example of the memory cell which concerns on one aspect of this invention. The figure which shows the structural example of the memory cell which concerns on one aspect of this invention. A timing chart showing an example of a data writing operation and a data reading operation of a memory cell according to one aspect of the present invention. The figure which shows the structural example of the memory cell which concerns on one aspect of this invention. The figure which shows the structural example of the storage device which concerns on one aspect of this invention. The figure which shows the structural example of the computer which concerns on one aspect of this invention. The figure which shows the structural example of the display system which concerns on one aspect of this invention. The figure explaining the structural example of the display device which concerns on one aspect of this invention. The figure explaining the configuration example of the pixel of the display device which concerns on one aspect of this invention. The figure explaining the configuration example of the pixel of the display device which concerns on one aspect of this invention. The figure which shows the structural example of the display device which concerns on one aspect of this invention. The figure which shows the structural example of the display device which concerns on one aspect of this invention. The figure which shows the structural example of the transistor which concerns on one aspect of this invention. The figure which shows the energy band structure of the transistor which concerns on one aspect of this invention. Top view of the semiconductor wafer. A flowchart and a perspective view showing a manufacturing process of electronic components. The figure which shows the structural example of the electronic device which concerns on one aspect of this invention. The figure which shows the structural example of the electronic device which concerns on one aspect of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, those skilled in the art can easily understand that the present invention is not limited to the description in the following embodiments, and that the embodiments and details can be variously changed without departing from the spirit and scope of the present invention. Will be done.
Therefore, the present invention is not construed as being limited to the description of the following embodiments.

Further, in one aspect of the present invention, a semiconductor device, a storage device, a display device, an image pickup device, an RF (Ra).
All devices are included in the category, such as the Dio Frequency) tag. The display device includes a liquid crystal display device, a light emitting device having a light emitting element typified by an organic light emitting element in each pixel, electronic paper, and a DMD (Digital Micromirror Device).
, PDP (Plasma Display Panel), FED (Field Emi)
ssion Display) etc. are included in the category.

Further, in the present specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used in the channel forming region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when the metal oxide has at least one of an amplifying action, a rectifying action, and a switching action, the metal oxide is referred to as a metal oxide semiconductor, which is a metal oxide semiconductor.
It can be abbreviated as OS. Further, when the term "OS FET" is used, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

Further, in the present specification and the like, the metal oxide having nitrogen is also a metal oxide (metal ox).
It may be generically called id). Further, a metal oxide having nitrogen is used as a metal oxynitride (me).
It may be called tal oxynitude).

Further, in the present specification and the like, CAAC (c-axis aligned crysta)
l), and CAC (cloud-aligned composite) may be described. In addition, CAAC represents an example of a crystal structure, and CAC represents an example of a function or a composition of a material.

Further, in the present specification and the like, CAC-OS or CAC-metal oxide is referred to as CAC-OS or CAC-metal oxide.
A part of the material has a conductive function, a part of the material has an insulating function, and the whole material has a function as a semiconductor. In addition, CAC-OS or CAC-metal oxide
Is used in the channel formation region of the transistor, the conductive function is the function of allowing electrons (or holes) to flow as carriers, and the insulating function is the function of allowing electrons (or holes) to flow as carriers. It is a function. By making the conductive function and the insulating function act in a complementary manner, the switching function (On / Off function) can be performed by CAC-OS or CAC.
-Can be given to metal oxide. CAC-OS or CAC-meta
In l oxide, by separating each function, both functions can be maximized.

Further, in the present specification and the like, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

Further, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region are 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm, respectively.
It may be dispersed in the material in the following sizes.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide
e is composed of a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region. In the case of this configuration, when the carrier is shed,
Carriers mainly flow in the components having a narrow gap. Further, the component having a narrow gap acts complementarily to the component having a wide gap, and the carrier flows to the component having a wide gap in conjunction with the component having a narrow gap. Therefore, the above CA
When C-OS or CAC-metal oxide is used in the channel formation region of the transistor, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the on state of the transistor.

That is, CAC-OS or CAC-metal oxide is a matrix composite material or a metal matrix composite material (metal m).
It can also be called an atomic composite).

Further, in the present specification and the like, when it is explicitly stated that X and Y are connected, the case where X and Y are directly connected and the case where X and Y are electrically connected. It is assumed that the case where X and Y are functionally connected and the case where X and Y are functionally connected are disclosed in the present specification and the like. Therefore, the connection relationship is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and the connection relationship other than the connection relationship shown in the figure or text is also described in the figure or text. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is used. Elements (eg, switches, transistors, capacitive elements, inductors) that allow an electrical connection between X and Y when the element, light emitting element, load, etc. are not connected between X and Y. , A resistance element, a diode, a display element, a light emitting element, a load, etc.), and X and Y are connected to each other.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display) that enables an electrical connection between X and Y is used. One or more elements, light emitting elements, loads, etc.) can be connected between X and Y. The switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conducting state (off state), and has a function of controlling whether or not a current flows. Alternatively, the switch has a function of selecting and switching the path through which the current flows. When X and Y are electrically connected, X and Y
It shall include the case where and is directly connected.

As an example of the case where X and Y are functionally connected, a circuit that enables functional connection between X and Y (for example, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), signal conversion) Circuits (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (
Power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes the potential level of the signal, voltage source, current source, switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier) A circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a storage circuit, a control circuit, etc.) can be connected one or more between X and Y. As an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is assumed that X and Y are functionally connected. To do. In addition, X and Y
When and are functionally connected, when X and Y are directly connected, and when X and Y are connected.
It shall include the case where and is electrically connected.

When it is explicitly stated that X and Y are electrically connected, X and Y are used.
When is electrically connected (that is, when another element or another circuit is sandwiched between X and Y), and when X and Y are functionally connected. The case (that is, the case where X and Y are functionally connected with another circuit in between) and the case where X and Y are directly connected (that is, between X and Y). (When another element or another circuit is connected without sandwiching the device) is disclosed in the present specification and the like. That is, they are electrically connected,
When it is explicitly stated, the same contents as when it is explicitly stated that it is simply connected shall be disclosed in the present specification and the like.

In addition, components having the same reference numerals between different drawings represent the same components unless otherwise specified.

Further, even when the independent components are shown to be electrically connected to each other on the drawing, one component may have the functions of a plurality of components at the same time. is there. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring function and the electrode function. Therefore, the electrical connection in the present specification also includes the case where one conductive film has the functions of a plurality of components in combination.

(Embodiment 1)
In the present embodiment, the semiconductor device and the storage device according to one aspect of the present invention will be described.

<Semiconductor device configuration example>
FIG. 1A shows a configuration example of the memory cell array 10 included in the semiconductor device according to one aspect of the present invention. The memory cell array 10 has a plurality of memory cells MC. The memory cell MC is a circuit having a function of storing data. FIG. 1A shows a configuration example in which the memory cell array 10 has a memory cell MC in m columns and n rows. Hereinafter, the memory cell MC in the x column and y row (x is an integer of 1 or more and m or less, y is an integer of 1 or more and n or less) is referred to as MC [x, y]. The plurality of memory cell MCs can be used as the memory cell array 10 of the semiconductor device.

The memory cell MC includes a plurality of wiring WLs (wiring WLa, wiring WLb) and a plurality of wiring BLs (wiring WLa, wiring WLb).
It is connected to the wiring BLa and the wiring BLb). The wiring WL has a function of supplying a potential for writing, reading, or holding data to the memory cell MC in a predetermined row.
The wiring BL has a function of supplying a potential for writing, reading, or holding data to a memory cell MC in a predetermined row. Further, the wiring BL has a function of transmitting a potential (hereinafter, also referred to as a writing potential) corresponding to the data to be written to the memory cell MC. In addition, M
The wiring WLa, wiring WLb, wiring BLa, and wiring BLb connected to C [x, y] are referred to as wiring WLa [y], wiring WLb [y], wiring BLa [x], and wiring BLb [x], respectively. ..

FIG. 1A shows a configuration example in which the wiring WL is shared by the memory cells MC in the same row and the wiring BL is shared by the memory cells MC in the same column. But these wires are
It may be provided individually for each memory cell MC.

The memory cell MC can be configured by a transistor or a capacitive element. here,
The memory cell MC is a transistor having a metal oxide in the channel formation region (hereinafter, OS).
Also called a transistor. ) Is preferably used. Since the metal oxide has a larger bandgap and a lower minority carrier density than a semiconductor such as silicon, the off-current of the transistor using the metal oxide in the channel formation region is extremely small. Therefore, when an OS transistor is used for the memory cell MC, the potential held in the memory cell MC is maintained for a long period of time as compared with the case where a transistor having silicon in the channel formation region (hereinafter, also referred to as a Si transistor) is used. Can be retained. As a result, the operation of rewriting at a predetermined cycle (refresh operation) becomes unnecessary, or the frequency of the refresh operation can be extremely reduced. Further, the data can be retained for a long period of time even during the period when the supply of the signal to the memory cell MC is stopped. Therefore, the memory cell array 1
The power consumption at 0 can be reduced.

FIG. 1B shows a part of the configuration of the memory cell MC according to one aspect of the present invention. In one aspect of the present invention, the memory cell MC has a circuit MCa and a circuit MCb. Circuit MCa, Circuit M
Each Cb has a function of storing data. The circuit MCa is a transistor Tra,
It has a capacitive element Ca. The circuit MCb includes a transistor Trb and a capacitive element Cb.

One of the source or drain of the transistor Tra is connected to one electrode of the capacitive element Ca, and the other of the source or drain is connected to the wiring L1a. The other electrode of the capacitive element Ca is connected to the wiring L2a. The wiring L1a and the wiring L2a are wirings to which a predetermined signal is supplied. Here, a node connected to one of the sources and drains of the transistor Tra and one electrode of the capacitive element Ca is referred to as a node FNa. The node FNa has a function as a potential holding unit of the memory cell MC. The circuit MCb also has the same circuit configuration as the circuit MCa.

The transistor Tra and the transistor Trb have a function as a switch for writing data. Further, the wiring L1a and the wiring L1b have a function of transmitting a writing potential. When the transistor Tra becomes conductive, the potential of the wiring L1a is supplied to the node FNa via the transistor Tra. As a result, data is written to the circuit MCa.
After that, when the transistor Tra is turned off, the node FNa is in a floating state and data is retained. In the circuit MCb, data is written and held by the same operation.

Here, it is preferable to use an OS transistor for the transistor Tra and the transistor Trb having a function as a data writing switch. As mentioned above, OS
Since the off current of the transistor is extremely small, the transistor Tra and the transistor Trb
The potentials of the node FNa and the node FNb can be maintained for an extremely long period of time in the off state. Therefore, the power consumption in the memory cell MC can be reduced.

The off-current of the OS transistor standardized by the channel width is 10 × ^10-21 A / μm (10 Zepto A / μ) when the source or drain voltage is 10 V and the room temperature (about 25 ° C.).
m) It can be as follows. O used for transistor Tra and transistor Trb
The off current of the S transistor is 1 × ^10-18 A or less or 1 at room temperature (about 25 ° C).
It is preferably × ^10-21 A or less, or 1 × ^10-24 A or less. Alternatively, the leak current is 85 ° C.
It is preferably 1 × 10 ^-15 A or less, 1 × 10 ^-18 A or less, or 1 × 10 ^-21 A or less.

The metal oxide contained in the channel forming region of the OS transistor is indium (I).
It preferably contains at least one of n) and zinc (Zn). Examples of such metal oxides include In oxide, Zn oxide, In—Zn oxide, and In—M—Zn oxide (elements M are Al, Ti, Ga, Y, Zr, La, Ce, and Nd. , Or Hf) is typical. These metal oxides reduce impurities such as hydrogen, which serves as an electron donor, and also reduce oxygen deficiency, thereby turning the metal oxide into an i-type semiconductor (intrinsic semiconductor) or an i-type semiconductor. You can get as close as you can. Such a metal oxide can be called a highly purified metal oxide. For example, the carrier density of metal oxides is less than 8 × 10 ¹⁵ cm ^-3 ,
It is preferably less than 1 × 10 ¹¹ cm ^-3 , more preferably less than 1 × 10 ¹⁰ cm ^-3 , and more than 1 × 10 ^-9 cm ^-3 .

Further, the metal oxide has a large band gap, electrons are not easily excited, and the effective mass of holes is large. Therefore, the OS transistor may be less likely to cause electron avalanche breakdown than the Si transistor. By suppressing hot carrier deterioration caused by electron avalanche breakdown, the OS transistor has a high drain withstand voltage and can be driven with a high drain voltage. Therefore, by using an OS transistor for the transistor Tra and the transistor Trb, the range of potentials held by the node FNa and the node FNb can be expanded.

In addition, a transistor other than the OS transistor may be used as the transistor Tra and the transistor Trb. For example, in a substrate having a single crystal semiconductor other than a metal oxide, a transistor having a channel formed in a part of the substrate may be used. Examples of such a substrate include a single crystal silicon substrate and a single crystal germanium substrate. Further, as the transistor Tra and the transistor Trb, a transistor in which a channel is formed in a film containing a semiconductor material other than a metal oxide may be used. Examples of such a film include an amorphous silicon film, a microcrystalline silicon film, a polycrystalline silicon film, a single crystal silicon film, an amorphous germanium film, a microcrystalline germanium film, a polycrystalline germanium film, or a single crystal germanium. Examples include membranes.

As the capacitance element of the memory cell MC, the parasitic capacitance formed by the transistors and wirings constituting the memory cell MC may be used. Further, as a capacitance element of the memory cell MC,
The capacitance formed between the gate of the transistor constituting the memory cell MC and the source or drain may be utilized. Further, two or more capacitive elements connected to the node FNa and / and the node FNb may be provided.

Here, in one aspect of the present invention, the gate of the transistor Tra is connected to the node FNb, and the gate of the transistor Trb is connected to the node FNa. Therefore, the conduction state of the transistor Tra and the transistor Trb is changed to the node FNb and the node FN, respectively.
It can be controlled by the potential of a.

Further, in one aspect of the present invention, the node FNa is connected to the wiring L2a via the capacitive element Ca. Therefore, by changing the potential of the wiring L2a, the potential of the node FNa can be controlled by utilizing the capacitive coupling of the capacitive element Ca. Similarly, wiring L2b
By changing the potential of the node FNb, the potential of the node FNb can be controlled by utilizing the capacitive coupling of the capacitive element Cb.

Here, for example, when the memory cell MC has only the circuit MCa, a constant potential is held only in the node FNa when the data of the memory cell MC is held. This means that the memory cell MC can hold either a constant positive (or negative) potential (hereinafter, also referred to as data “1”) or 0V (hereinafter, also referred to as data “0”) in the node FNa2. In the case of a value memory cell, a positive (or negative) potential is applied to only one of the source and drain of the transistor Tra when the data "1" is held, and the transistor Tra is held when the data "0" is held.
No positive (or negative) potential is applied to any of the electrodes (source, drain, gate). That is, when the memory cell MC has only the circuit MCa, the data "
At the time of holding 1 ”, only one kind of stress of positive (or negative) potential is continuously applied to one of the source and drain of the transistor Tra. Therefore, when the memory cell MC has only the circuit MCa. In some cases, the application stress caused by holding the data "1" induces and accelerates the deterioration of the transistor Tra. The deterioration causes the transistor T.
When the electrical characteristics of ra (threshold voltage, off current, etc.) fluctuate, the circuit MCa (memory cell MC)
It may interfere with the reading, writing and retention of data in.

However, in one aspect of the present invention, two circuits (circuit MCa and circuit MCb) are electrically connected as shown in FIG. 1B, and this is configured as one memory cell MC. Thereby, the deterioration of the transistor Tra described above can be suppressed. Details will be described below.

As shown in FIG. 1 (B), the gate of the transistor Tra and the node FNb are connected, and one of the source or drain of the transistor Tra and the node FNa are connected. Also. The gate of the transistor Trb and the node FNa are connected, and one of the source or drain of the transistor Trb and the node FNb are connected. Here, the combination in which the node FNa holds a constant positive potential and the node FNb holds 0V is data "1", the node FNa holds 0V, and the node FNb holds a constant positive potential. The combination to be created is redefined as data "0". For example, when the memory cell MC is a binary memory cell capable of holding either the data “1” or the data “0”, the data “
When holding 1 ”, one of the source or drain of the transistor Tra and the transistor Trb
A positive potential is applied to the gate of the transistor Trb, and when the data “0” is held, a positive potential is applied to one of the source or drain of the transistor Trb and the gate of the transistor Tra.
Considering this with the potential of one of the source or drain of each transistor as a reference (0V), it is equivalent to a negative potential being applied to the gate insulator (node FNa side) of the transistor Tra when the data "1" is held. When the data "0" is held, the transistor Tr
A state equivalent to the application of a negative potential to the gate insulator (node FNb side) of b is obtained.

That is, in the memory cell MC shown in FIG. 1 (B), a negative gate bias stress (hereinafter, also referred to as −GBS) is applied to the transistor Tra when the data “1” is held. Further, since the node FNa in which the positive potential is held is connected to the gate of the transistor Trb, the transistor Trb has a positive gate bias stress (hereinafter referred to as “)”.
Also called + GBS. ) Will be applied. Similarly, when holding data "0",
+ GBS is applied to the transistor Tra, and -GBS is applied to the transistor Trb (see Table 1).

As described above, in one aspect of the present invention, when the data “1” of the memory cell MC is held and the data “0”.
"At the time of holding, stress (+ GBS, -GBS) of opposite polarity is applied to the transistor Tra and the transistor Trb, respectively. As a result, when the data of the memory cell MC is held, the transistor Tra and the transistor Trb are subjected to + GBS or -GBS. Only the stress of one of the polarities is not applied. For example, even if the transistor Tra (transistor Trb) deteriorates due to -GBS (+ GBS) when the data "1" is held, the data "0" is held. Sometimes the transistor Tra (transistor Trb) is + GBS (-G)
By deteriorating due to BS), each deterioration can be offset.

As described above, by applying the configuration of FIG. 1 (B) to the memory cell MC, deterioration of the transistor Tra and transistor Trb and fluctuation of characteristics are reduced, and the reliability of the memory cell array 10 of FIG. 1 (A) is improved. Can be improved. Hereinafter, specific configuration examples and operation examples of the memory cell MC having the above configuration will be described in detail.

<Memory cell configuration example>
FIG. 2 shows a specific configuration example of the memory cell MC according to one aspect of the present invention. Note that, as typical examples in FIG. 2, memory cell MC [1,1], memory cell MC [2,1], and memory cell MC
Although [1, 2] and the memory cell MC [2, 2] are shown, other memory cell MCs can have the same configuration.

Memory cell MC [1,1], memory cell MC [2,1], memory cell MC [1,2],
The memory cells MC [2, 2] have a circuit MCa and a circuit MCb, respectively. Circuit MCa
Has a transistor Tra and a capacitive element Ca. The circuit MCb is a transistor Trb.
And a capacitive element Cb.

The gate of the transistor Tra is connected to the node FNb, one of the source or drain is connected to one electrode of the gate of the transistor Trb and the capacitance element Ca by the node FNa, and the other of the source or drain is connected to the wiring BLa. .. The other electrode of the capacitive element Ca is connected to the wiring WLa. The gate of the transistor Trb is connected to the node FNa, one of the source or drain is connected to one electrode of the gate of the transistor Tra and the capacitance element Cb at the node FNb, and the other of the source or drain is connected to the wiring BLb. .. The other electrode of the capacitive element Cb is connected to the wiring WLb.

In FIG. 2, memory cells MC in the same row of wiring WLa and wiring WLb (here, memory cells MC [1,1] and memory cells MC [2,1], or MC [1,2] and MC. [2,2]
), And the wiring BLa and the wiring BLb are the same row of memory cells MC (here, in this case).
Memory cell MC [1,1] and memory cell MC [1,2], or memory cell MC [2,1]
] And the memory cell MC [2,2]). However,
These wirings may be provided individually for each memory cell MC.

The wiring WLa has a function of supplying a potential for writing, reading, or holding data to the memory cell MC to the node FNa of the memory cell MC in a predetermined row. Wiring WL
Since a is connected to the node FNa via the capacitive element Ca, the potential of the node FNa can be controlled by controlling the potential of the wiring WLa by utilizing the capacitive coupling of the capacitive element Ca. Further, since the node FNa is connected to the gate of the transistor Trb, the conduction state of the transistor Trb can be controlled by controlling the potential of the wiring WLa. Similarly, by controlling the potential of the wiring WLb, the potential of the node FNb can be controlled, and the conduction state of the transistor Tra can be controlled.

The wiring BLa has a function of supplying a potential for writing, reading, or holding data to the memory cell MC to the node FNa of the memory cell MC in a predetermined row. Wiring BL
Since a is connected to the other of the source or drain of the transistor Tra, by making the transistor Tra conductive by the potential control of the wiring WLb described above, the potential from the wiring BLa is transmitted to the node FNa via the transistor Tra. Can be supplied. Similarly
The potential from the wiring BLb can be supplied to the node FNb via the transistor Trb.

In this way, by appropriately combining the potential supply from the wiring WL (wiring WLa, wiring WLb) and the potential supply from the wiring BL (wiring BLa, wiring BLb), data can be written to the memory cell MC. The potential to do so can be supplied to the nodes FNa and FNb.

As described above, since the memory cell MC according to one aspect of the present invention has the above circuit configuration, positive (or negative) potentials are supplied (written) to the node FNa and the node FNb, respectively.
And can be retained. For example, when the memory cell MC is a binary memory cell capable of holding either the data “1” or the data “0” described above, the wiring WLa uses the capacitive coupling of the capacitive element Ca when writing the data “1”. Then, it has a function of controlling the potential of the node FNa to be positive (or negative), and the wiring WLb utilizes the capacitive coupling of the capacitive element Cb to make the node FN.
It has a function of controlling the potential of b to 0V. On the other hand, when writing data "0", the wiring WL
a has a function of controlling the potential of the node FNa to 0V by utilizing the capacitive coupling of the capacitive element Ca, and the wiring WLb uses the capacitive coupling of the capacitive element Cb to make the potential of the node FNb positive (or negative). ) Has a function to control. As a result, stresses of opposite polarities (+ GBS, -GBS) are applied to the transistor Tra and the transistor Trb when the data "1" is held and when the data "0" is held in the memory cell MC. , Deterioration of the transistor Tra and the transistor Trb can be suppressed. In the following, the node FN is positive (or negative)
A specific operation example of the memory cell MC when the potential of the memory cell MC is supplied and held will be described.

<Example of memory cell operation>
FIG. 3 shows a timing chart showing an example of an operation of writing data to the memory cell MC according to one aspect of the present invention and an operation of reading the written (stored) data.

In the following, a case where 1 bit (binary value) data is stored in each of the memory cells MC in FIG. 2 will be described. Here, as a specific example, the state where the potential of the node FNa is positive and the potential of the node FNb is 0V corresponds to the state where the data “1” is stored in the memory cell MC, the potential of the node FNa is 0V, and the potential of the node FNb is 0V. Memory cell M when the potential is positive
A case corresponding to a state in which data “0” is stored in C will be described.

The potentials of the node FNa and the node FNb are not limited to the above. That is, node FN
The a and the node FNb can hold not only two values of positive and 0 but also potentials of three or more values. In this case, the amount of information that can be stored in the memory cell MC can be increased. Further, the correspondence between the potentials of the nodes FNa and the node FNb and the data is not limited to the above, and can be arbitrarily defined.

[Data writing operation]
First, using the timing chart shown in FIG. 3, the memory cells MC [1,1] shown in FIG. 2
An example of the operation of writing data to is described. In FIG. 3, the period T1 is the period for writing the data “1”, and the period T3 is the period for writing the data “0”.

Immediately before the period T1, it is assumed that the potential of 0 V is held in the node FNa and the node FNb.

First, in the period T1, a positive potential (+ V) is given to the wiring WLb [1]. Then, the transistor Tra becomes conductive, and the positive potential (+ V) given to the wiring BLa [1] is gradually supplied to the node FNa via the transistor Tra. At this time, the wiring WLa [
By setting the potentials of 1] and the wiring BLb [1] to 0V, the potential of the node FNb drops to 0V. As a result, the potential of + V is supplied to the node FNa and the potential of 0V is supplied to the node FNb, so that the data “1” is written in the memory cell MC [1,1]. In the timing chart shown in FIG. 3, the potential given to the wiring WLb [1] and the wiring BL
The potentials given to a [1] are both + V, but they may have different potentials. When the writing of the data “1” to the memory cell MC is completed, the potentials of the wiring WLb [1] and the wiring BLa [1] are returned to 0V as shown in the period T2.

Next, in the period T3, a positive potential (+ V) is given to the wiring WLa [1]. Then, the transistor Trb becomes conductive, and the positive potential (+ V) given to the wiring BLb [1] is supplied to the node FNb via the transistor Trb. By supplying the potential of + V to the node FNb, the transistor Tra also becomes conductive. At this time, since the potential of the wiring BLa [1] is 0V, the positive potential (+ V) supplied to the node FNa by writing the data “1” described above drops to 0V. In addition, in FIG. 3, the above-mentioned data "1" is written (
Node FNa and node F in writing data "0" (period T3) compared to period T1)
The fluctuation of the potential of Nb is shown sharply. This is because, in FIG. 3, since the positive potential (+ V) has already been supplied to the node FNa before writing the data “0”, the timing at which the transistor Trb becomes conductive after the potential is supplied from the wiring WLa is This is to speed up. The potential supply speed to the node FNb via the transistor Trb is increased by that amount, and the timing at which the transistor Tra becomes conductive and the timing at which the potential (0V) is supplied to the node FNa are also increased accordingly. As in the above example, since the node FNa is supplied with the potential of 0 V and the node FNb is supplied with the potential of + V, the memory cell MC [1,
Data "0" is written in 1]. In the timing chart shown in FIG. 3, the wiring W
The potential given to La [1] and the potential given to the wiring BLb [1] are both + V.
The potentials may have different magnitudes. Data "0" to memory cell MC [1,1]
"When the writing is completed, as shown in the period T4, the wiring WLa [1] and the wiring BLb [1]
] Potential is returned to 0V.

As described above, the wiring WL [1] (wiring WLa [1], wiring WLb [1]) and wiring BL
By controlling the potential of [1] (wiring BLa [1], wiring BLb [1]), the node F
Data "1" or data "0" can be written to the memory cell MC [1,1] by controlling the potentials of Na and the node FNb.

The data rewriting operation is collectively performed for the memory cells MC in the same row that share the wiring WL (wiring WLa, wiring WLb). In FIG. 3, the wiring WLa [1] and the wiring WLb [1]
] Is selected to write to the memory cell MC [1,1]. At this time, similarly, the memory cells MC [2,1] in the same row sharing the wiring WLa [1] and the wiring WLb [1].
It is preferable to write to. Wiring WLa [1] when writing a positive potential, wiring WL
The memory cell MC in the same row that shares the data "1" or the data "0" that shares b [1] may be written for each memory cell MC. Or, when writing, the wiring WLa [
1], wiring WLb [1] is raised to a positive potential (+ V) at the same time, wiring WLa [1], wiring W
A voltage corresponding to data "1" or data "0" is applied to each wiring BL for each memory cell MC in the same row that shares Lb [1], and data "1" or data "0" is simultaneously applied to each wiring BL.
May be written.

Further, when writing data in the memory cell MC of a selected row, a potential is supplied to the memory cell MC of the other non-selected rows so that the transistor Tra and the transistor Trb can be maintained in the off state. Is preferable. For example, when the memory cells MC [1,1] in FIG. 2 are selected and data is written, the memory cells MC [1,2], MC [
It is preferable to apply a certain negative potential (−V) to the wiring WLa [2] and the wiring WLb [2] connected to the wiring WLa [2] (see FIG. 3). This makes it possible to prevent unintended data fluctuations from occurring in the memory cell MC in the non-selected state. The voltage applied to the non-selected wiring WLa [2] and the wiring WLb [2] was set to −V, but the non-selected wiring WLa [2] was set.
], The voltage applied to the wiring WLb [2] is such that the non-selected memory cells MC [1, 2], the transistor Tra of the memory cell MC [2, 2], and the transistor Trb are in the data holding state of the node FNa and the node FNb. Any potential may be used as long as it can be turned off by capacitive coupling via capacitance Ca and capacitance Cb, and may be an absolute negative potential different from the positive potential (+ V) used at the time of writing. Non-selected memory cell MC [1, 2] or memory cell MC [2, 2]
If the transistor Tra and transistor Trb are off, the wiring BLa and wiring BL
The potentials of the nodes FNa and FNb of the non-selected memory cells MC [1, 2] or the memory cells MC [2, 2] in the same column of b can be separated from the potentials of the writing entering the wiring BLa and the wiring BLb, which is erroneous. Rewriting can be prevented.

[Data read operation]
Next, using the timing chart shown in FIG. 3, the memory cells MC [1,1] shown in FIG. 2 are used.
An example of the operation of reading data from is described. In FIG. 3, the period T5 to the period T7 is a period for reading the data “0” stored in the memory cell MC. That is, immediately before the period T5, the node FNa holds a potential of 0 and the node FNb holds a positive potential (+ V).

First, in the period T5, the wiring WL (wiring WLa, wiring W) connected to each memory cell MC
A negative potential (-V) is given to Lb). This is the wiring BL when precharging, which will be described later.
This is to prevent erroneous writing to the selected memory cell MC and the non-selected memory MC from the precharge potential applied to (wiring BLa, wiring BLb). Here, the above-mentioned negative potential is not limited to −V, and any potential that allows the transistor Tra and transistor Trb in the memory cell MC to be turned off regardless of the data holding state of the node FNa and the node FNb. Just do it. Although the potential is written to the node FNa and the node FNb according to the state of the data "1" or the data "0" by the writing operation, it can be said that the electric charge corresponding to the potential is actually given. Further, the node FNa and the node FNb hold an electric charge corresponding to the potential during the writing operation, and the potential of the wiring WL (wiring WLa, wiring WLb) or the like is arbitrarily combined by the capacitance coupling via the capacitance Ca and the capacitance Cb. Can be changed. Therefore, the transistor Tra and the transistor Trb are the wiring WL (wiring WLa,
A negative potential (-V) can be applied to the wiring WLb) to turn it off.

Next, in the period T6, the wiring BLa [1] connected to the selected memory cells MC [1,1]
And the wiring BLb [1] is given a positive precharge potential (+ _VP ). The precharge potential is a potential that serves as a reference for identifying whether data “1” or data “0” is stored in the selected memory cell MC [1,1]. For example, wiring BLa [1] and wiring B connected to the selected memory cells MC [1,1] by supplying an electric potential to each wiring described later.
The potential given to Lb [1] (both + _VP ) can be changed to a higher potential or a lower potential. This potential fluctuation by (in the wiring BLa [1] to the wiring BLb [1], which varies in greater potential than + V _P, Which is varied to smaller potential than + V _P.) Monitoring, selection It is possible to identify whether the data “1” or the data “0” is stored in the memory cell MC [1,1]. Incidentally, as shown in FIG. 3, + V _P is assumed to be less potential than + V.

Next, in the period T7, the wiring WLa [1] connected to the selected memory cell MC [1,1]
And a positive potential (+ V) is given to the wiring WLb [1]. Then, the selected memory cell MC [1,
Due to the capacitive coupling of the capacitive element Ca and the capacitive coupling of the capacitive element Cb in 1], the potential applied to the gate of the transistor Tra and the transistor Trb of the selected memory cell MC [1,1] rises, and both of the transistors become conductive. .. As a result, the selected memory cell MC [
Wiring BLa connecting the node FNa in [1,1] and the selected memory cell MC [1,1]
Of the capacitance Ca and the capacitance Cb between [1] and between the node FNb in the selected memory cell MC [1,1] and the wiring BLb [1] connected to the selected memory cell MC [1,1]. The capacity and the electric charge stored in the wiring capacity of the wiring BLa [1] and the wiring BLb [1] are redistributed. In the timing chart shown in FIG. 3, the data “0” is stored in the selected memory cells MC [1,1] at the time point T4 before the read operation (period T5 to period T7) is performed. That is, the node FNa of the selected memory cells MC [1,1] is supplied with a potential of 0 V, and the node FNb is supplied with a potential of + V. Therefore, the wiring B
Potential of la [1] is reduced to a small potential (+ _{V L)} than the + _{V P,} wiring BL
The potential of b [1] rises from + _VP to a higher potential (+ V _H ). By monitoring this potential fluctuation amount, it is possible to identify that the data “0” is stored in the selected memory cell MC [1,1]. Although not shown in the timing chart of FIG. 3, when the potential of the wiring BLa [1] rises to + V _H and the potential of the wiring BLb [1] falls to + _VL , the selected memory cell MC It is identified that the data "1" is stored in [1,1].

In the period T4 before the read period T5, the data "0" is stored in the selected memory cell MC [1,1], and in the case of the data "0", the node FNb is positive. Since the potential (+ V) is held, the transistor Tra is in a conductive state, and the node FNa and the wiring BLa [1] are in a conductive state. Therefore, the node FNa has the data "0".
However, the period immediately before giving a negative potential (-V) to the wiring WLb [1] in order to turn off the transistor Tra in the period T5 is a state in which the potential of 0V in the storage state of "is not necessarily held. By applying 0V to the wiring BLa [1] at T4, the potential of the node FNa can be fixed to 0V. In the case of the data “1” other than the example of FIG. 3, similarly, the node FNb
The potential of can be fixed at 0 V immediately before reading.

Further, in the period T7, a positive potential (+ V) is applied to the wiring WLa [1] and the wiring WLb [1].
Is given, the wiring BLa [1] and the wiring BL connected to the selected memory cells MC [1,1] are given.
reference potential + _{V P} precharging of b [1] is, the capacitance Ca and the capacitance Cb of the capacitance and wiring BL
The potential may fluctuate slightly higher due to capacitance coupling such as a, wiring BLb, wiring WLa, and parasitic capacitance of wiring WLb. In this case, data "1" and data "0" to the variable potential amount to the reference potential + V _P identifies the potential may be a reference to the addition.

Alternatively, in the period T7, a positive potential (+ V) is applied to the wiring WLa [1] and the wiring WLb [1].
Instead, the positive precharge potential supplied by the wiring BLa [1] and the wiring BLb [1] (
+ If _{V P)} slightly smaller potential than the (+ _{V L)} may transistor Tra and the transistor Trb in the conductive state, it may be given 0V. In the period T7 of FIG. 3, the state in which the data “0” is stored in the selected memory cells MC [1,1] is being read. In this case, the potential of 0V is in the node FNa of the selected memory cell MC [1,1], and + V is in the node FNb.
The potentials of the above are supplied, and the wiring WLa [1] and the wiring WLb [1] are 0V.
However, the transistor Tra of the selected memory cell MC [1,1] is in a conductive state. The other transistor Trb of the selected memory cell MC [1, 1], the wiring BLa [1] in that the positive precharge potential (+ _{V P)} is supplied, the node FNa via the transistor Tra is conductive A potential (+ _VL ) is supplied to the memory by redistributing the charge. This potential (+ _VL )
If the transistor Trb can be made conductive by the above, the wiring WLa [1] and the wiring WLb [1] may be 0V. When the transistor Trb becomes conductive, charge is redistributed between the node FNb and the wiring BLb [1] via the transistor Trb, and the wiring B
The potential of Lb [1] rises from + _VP to a higher potential (+ V _H ). By monitoring this potential fluctuation amount, it is possible to identify that the data “0” is stored in the selected memory cell MC [1,1]. Data "1" can also be identified in a similar manner.

By the above-mentioned data reading operation, the storage state (0V for node FNa, + V for node FNb) before reading in the selected memory cell MC [1,1] is lost (destructive reading). Therefore, for example, a sense amplifier or the like is provided outside the memory cell MC, and the selected memory cell MC [1,1] as shown in the period T8 is connected to the wiring BLa [1] corresponding to the storage state data “0” before reading. A refresh operation is performed in which + V is applied to 0V and the wiring BLb [1]. As a result, 0V is written to the node FNa corresponding to the storage state data “0” of the selected memory cell MC lost in the above-mentioned destruction read, and + V is written to the node FNb by the refresh operation, and then each wiring WL (wiring WLa, wiring) is written. WLb), each wiring BL (wiring BLa, wiring BLb)
Can be returned to 0V to restore the storage state before the destruction read (period T9).

Similar to the data writing operation described above, the data reading operation is collectively performed on the memory cells MC in the same row that share the wiring WL (wiring WLa, wiring WLb). When reading data in the memory cell MC in one row, the memory cell MC in the other row
It is preferable to supply a potential that allows the transistor Tra and the transistor Trb to be maintained in the off state. For example, when the memory cells MC [1,1] in FIG. 2 are selected and data is read, the wiring WLa [2] connected to the memory cells MC [1,2] and MC [2,2] is used.
2], it is preferable to apply a negative potential (−V) to the wiring WLb [2] (see FIG. 3).
). As a result, it is possible to prevent an unintended potential from being output from the memory cell MC in the non-selected state to the wiring BLa and the wiring BLb.

[Data retention operation]
The memory cell MC can hold the potential of the node FN regardless of whether the potential is positive (or negative) or 0.

When the data "1" is stored in the memory cell MC [1,1], a positive potential (+ V) is supplied to the node FNa and a potential of 0 V is supplied to the node FNb. Therefore, the transistor Tra is in a non-conducting state, and the potential (+ V) of the node FNa can be maintained. The transistor Trb becomes conductive due to the potential (+ V) of the node FNa, but the wiring WL [1] (wiring WLa [1], wiring WLb [1]) and wiring BL connected to the memory cell MC [1,1] If a potential of 0 V is applied to [1] (wiring BLa [1], wiring BLb [1]),
Since the potential difference between the wiring BLb [1] (potential 0V) and the node FNb (potential 0V) becomes 0V, the potential 0V supplied to the node FNb is maintained. Therefore, memory cell MC
Data "1" can be retained in [1,1] (see period T2 in FIG. 3).

When data "0" is stored in the memory cell MC [1,1], it is 0 in the node FNa.
A positive potential (+ V) is supplied to the potential of V and the node FNb. Therefore, the transistor Trb is in a non-conducting state, and the potential (+ V) of the node FNb can be maintained. The transistor Tra becomes conductive due to the potential (+ V) of the node FNb, but the wiring WL [1] (wiring WLa [1], wiring WLb [1]) and wiring BL [1] connected to the memory cell MC
1] (wiring BLa [1], wiring BLb [1]) is provided with a potential of 0V, and the wiring BL
Since the potential difference between a [1] (potential 0V) and the node FNa (potential 0V) becomes 0V, the potential 0V supplied to the node FNa is maintained. Therefore, the memory cell MC [1,1]
Data “0” can be retained in (see period T4 in FIG. 3).

Further, for example, when the data "0" is stored in the memory cell MC [1,1], FIG.
Negative potential (-) at all wiring WLs (wiring WLa, wiring WLb), such as period T5
Data can be retained even when V) is applied to turn off the transistor Tra and the transistor Trb. By making the transistor Tra and the transistor Trb non-conducting, for example, the node FNa and the node FNb hold the electric charge corresponding to the potential of 0V for the node FNa and the positive potential (+ V) for the node FNb in the data “0”. Can be done.

Hereinafter, the stress applied to the transistor Tra and the transistor Trb when the data “1” is held and the data “0” is held in the memory cell MC [1,1] described above will be described. When the data "1" of the memory cell MC [1,1] is held, a positive potential (+ V) is applied to one of the source or drain of the transistor Tra (node FNa side), and the other of the source or drain (wiring BLa [1]. ] And the gate are connected with a potential of 0V. Then, a positive potential (+ V) is applied to the gate of the transistor Trb, and a potential of 0 V is applied to the source and drain. On the other hand, when the data “0” of the memory cell MC [1,1] is held, a positive potential (+ V) is applied to the gate of the transistor Tra, and a potential of 0V is applied to the source and drain. Then, one of the source and drain of the transistor Trb (
A positive potential (+ V) is applied to the node FNb side), and the other side of the source or drain (wiring BL)
A potential of 0 V is applied to b (the side connected to [1]) and the gate. This is based on the potential of one of the source or drain of each transistor (node FNa side, node FNb side) (0V).
), Negative gate bias stress (-GBS) is applied to the gate insulator (node FNa side) of the transistor Tra when the data "1" of the memory cell MC is held, and the gate insulator of the transistor Trb is positive. The state is equivalent to the gate bias stress (+ GBS) applied. Similarly, when the data “0” of the memory cell MC is held, the gate insulator (node FNb side) of the transistor Trb has a negative gate bias stress (−G).
BS) is applied and positive gate bias stress (BS) is applied to the gate insulator of the transistor Tra.
+ GBS) is applied (see Table 1).

As described above, in one aspect of the present invention, when the data “1” of the memory cell MC is held and the data “0”.
"At the time of holding, stress (+ GBS, -GBS) of opposite polarity is applied to the transistor Tra and the transistor Trb, respectively. Therefore, when the data of the memory cell MC is held, the transistor Tra and the transistor Trb are subjected to + GBS or -GBS. Since only the stress of one of the polarities is not applied, it is possible to suppress the deterioration of the transistor Tra and the transistor Trb due to the data holding operation of the memory cell MC.

Further, when the data "1" is held (when the data "0" is held), a positive potential (+ V) is applied to the gate of the transistor Trb (transistor Tra), so that ions and particles having a negative charge, for example, are generated. It may be injected into the gate insulator of the transistor Trb (transistor Tra) and cause deterioration in which the threshold voltage of the transistor Trb (transistor Tra) changes. However, in one aspect of the present invention, when the data stored in the memory cell MC is switched from the data “1” (data “0”) to the data “0” (data “1”), the transistor Trb (transistor Tra) is used. Since a negative potential (-V) is applied to the gate, negatively charged ions and particles are transferred to the transistor Trb (transistor T).
It is released from the gate insulator of ra), and the above-mentioned deterioration can be repaired.

Considering that the probabilities that data "1" and data "0" are stored in the memory cell MC are almost equal, from Table 1, positive and negative stress (+ GB) is applied to the transistor Tra and the transistor Trb.
S and −GBS) will be applied evenly. Therefore, deterioration of the transistor Tra and the transistor Trb can be suppressed more effectively. If the retention period of specific data stored in the memory cell MC is expected to be long, the memory cell MC that stores the data is intentionally changed and applied to the transistor Tra and the transistor Trb. Voltage stress may be controlled. In this way, in one aspect of the present invention, it is possible to provide a semiconductor device having good reliability.

In order to realize the data retention of the memory cell MC for a long period of time, the off-currents of the transistors Tra and the transistors Trb constituting the memory cell MC (Vg = 0 of Vg-Id characteristic).
It may be paraphrased as Id in V. ) Should be as small as possible. In the transistor Tra and the transistor Trb according to one aspect of the present invention, by using a metal oxide in the channel forming region, the off-current of the transistor can be significantly reduced as compared with the case where Si or the like is used. Therefore, the semiconductor device according to one aspect of the present invention can retain data for an extremely long period of time. Further, since the data can be retained for a long period of time, the refresh operation of the memory cell MC becomes unnecessary, or the frequency of the refresh operation can be extremely reduced. Therefore, in one aspect of the present invention, it is possible to provide a semiconductor device having extremely low power consumption.

As described above, the memory cell array 10 according to one aspect of the present invention can realize both good reliability and low power consumption.

<Modification example of memory cell>
The circuit configuration of the memory cell MC according to one aspect of the present invention is not limited to that shown in FIG. FIG. 4 shows another configuration example of the memory cell MC according to one aspect of the present invention.

The memory cell MC shown in FIG. 4A is different from FIG. 2 in that the transistor Tra and the transistor Trb have a pair of gates. When the transistor has a pair of gates, one gate may be referred to as a first gate, a top gate, or simply a gate, and the other gate may be referred to as a second gate or a bottom gate. In the following, FIG. 4 (A)
Of the pair of gates of the transistors constituting the memory cell MC shown in FIG. 2, the gate of the transistor of FIG. 2 is simply called a gate, and the gate without it is called a bottom gate.

In the memory cell MC shown in FIG. 4A, the bottom gate of the transistor Tra is connected to the gate of the transistor, and the bottom gate of the transistor Trb is connected to the gate of the transistor. In this case, since the potential of the gate of each transistor and the potential of the bottom gate are equal, in the transistor shown in FIG. 4A, the same potential is applied to the channel forming region from both the gate and the bottom gate. Therefore, the transistor shown in FIG. 4A has better electric field controllability by the gate and the bottom gate in the channel formation region than the transistor shown in FIG. As a result, the transistor shown in FIG. 4A is easier to improve the electric field control of the gate and the bottom gate than the electric field between the source and the drain than the transistor shown in FIG. 2, and the switching characteristics of the transistor can be improved. ..

For example, when the memory cell MC shown in FIG. 4A writes data “1” (writes data “0”), a positive potential (+ V) is applied to both the gate and the bottom gate of the transistor Tra (transistor Trb). It is applied. As described above, since the electric field controllability by the gate and the bottom gate in the channel formation region of the transistor Tra (transistor Trb) is higher than that of the memory cell MC shown in FIG. 2, the transistor is more reliable than the memory cell MC shown in FIG. The Tra (transistor Trb) can be made conductive. That is, the memory cell M shown in FIG. 2 indicates that the potential (+ V) is supplied to the node FNa (node FNb).
It can be done more reliably than C.

Further, for example, when the memory cell MC shown in FIG. 4A holds data “1” (holds data “0”), a potential of 0 V is applied to both the gate and the bottom gate of the transistor Tra (transistor Trb). Will be done. As described above, since the electric field controllability by the gate and the bottom gate in the channel formation region of the transistor Tra (transistor Trb) is higher than that of the memory cell MC shown in FIG. 2, the transistor is more reliable than the memory cell MC shown in FIG. The Tra (transistor Trb) can be put into a non-conducting state. That is, node F
The potential (+ V) supplied to Na (node FNb) is the transistor Tra (transistor T).
Leakage via rb) can be more reliably prevented than in the memory cell MC shown in FIG. As a result, the memory cell MC shown in FIG. 4A can realize data retention for a longer period of time than the memory cell MC shown in FIG.

In the memory cell MC shown in FIG. 4B, the bottom gates of the transistor Tra and the transistor Trb are connected to the wiring BGL. The wiring BGL is a wiring having a function of supplying a predetermined potential to the bottom gate. By controlling the potential of the wiring BGL, the threshold voltage of the transistor Tra and the transistor Trb can be individually controlled by the bottom gate separately from the control by the gate. That is, the threshold voltage with respect to the gate of the transistor Tra and the transistor Trb can be changed and controlled by the potential of the bottom gate.

The wiring BGL connected to the transistor Tra and the wiring BGL connected to the transistor Trb can be provided individually. Further, the wiring BGL may be shared by all the memory cell MCs of the memory cell array 10, or may be shared by some memory cell MCs. In addition, the potential supplied to the wiring BGL may be a fixed potential (single potential) or a fluctuating potential (plural potentials). When supplying a fluctuating potential to the wiring BGL, for example, transistor Tra, transistor Tr
The threshold voltages of the transistor Tra and the transistor Trb may be changed by changing the potential of the wiring BGL depending on the period in which b is turned on and the period in which b is turned off.

As described above, in one aspect of the present invention, a semiconductor device having a memory cell MC composed of two transistors (transistor Tra, transistor Trb) and two capacitive elements (capacitive element Ca, capacitive element Cb). Can be provided. And, for example
When the memory cell MC is a binary memory cell capable of holding either data "1" or data "0", a predetermined potential is given to each wiring connected to the memory cell MC at an appropriate timing. , Transistor Tra and transistor Tr due to memory cell holding operation
Deterioration of b can be suppressed. Thereby, in one aspect of the present invention, it is possible to provide a semiconductor device having good reliability.

Further, in one aspect of the present invention, a transistor (OS) using a metal oxide for the memory cell MC.
By using a transistor), the off-current of the transistor can be significantly reduced as compared with the case of using Si or the like. Thereby, in one aspect of the present invention, it is possible to provide a semiconductor device having low power consumption.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 2)
In this embodiment, a configuration example of a storage device using the memory cell array 10 described in the above embodiment will be described.

FIG. 5 shows a configuration example of the storage device 100. The storage device 100 includes a cell array 110 and a drive circuit unit 120.

The cell array 110 has a plurality of memory cells MC and has a function of storing data. As the cell array 110, the memory cell array 10 described in the above embodiment can be used.

The drive circuit unit 120 includes a drive circuit 130, a drive circuit 140, a control circuit 160, and an output circuit 1.
Has 70. The drive circuit 130 has a function of controlling the potential of the wiring WL (wiring WLa, wiring WLb). The drive circuit 140 has a function of controlling the potential of the wiring BL (wiring BLa, wiring BLb).

The drive circuit 130 includes a decoder 131, a row driver 132, and a sense amplifier 133.

The decoder 131 has a function of decoding the address signal ADDR input from the outside and supplying a control signal to the row driver 132 or the sense amplifier 133.

The row driver 132 uses the wiring WLa and the wiring WLb connected to the memory cell MC in the predetermined row.
It has a function of selecting a wiring WLa and a function of supplying a potential for writing or reading data to the wiring WLa and the wiring WLb. The selection of the wiring WLa and the wiring WLb is performed based on the control signal input from the decoder 131. Also, when writing data, the wiring WL
a, The potential supplied to the wiring WLb is generated by using the data WDATA input from the outside. The data WDATA corresponds to the data to be written to the cell array 110.

The sense amplifier 133 amplifies the potential generated by the row driver 132, and the wiring WLa,
It has a function of supplying wiring WLb. If it is not necessary to amplify the potential generated by the row driver 132, the sense amplifier 133 can be omitted.

The drive circuit 140 includes a decoder 141, a row driver 142, a sense amplifier 143, and a precharge circuit 144.

The decoder 141 has a function of decoding the address signal ADDR input from the outside and supplying a control signal to the column driver 142 or the sense amplifier 143.

The column driver 142 has wiring BLa and wiring BLb connected to the memory cells MC in a predetermined row.
It has a function of selecting the above and a function of supplying a potential for writing or reading data to the wiring BLa and the wiring BLb. The selection of the wiring BLa and the wiring BLb is performed based on the control signal input from the decoder 141. Also, when writing data, the wiring BL
a, The potential supplied to the wiring BLb is generated by using the data WDATA input from the outside.

The sense amplifier 143 amplifies the potential generated by the column driver 142, and the wiring BLa,
It has a function of supplying wiring BLb. Further, the sense amplifier 143 has a function of amplifying the potential corresponding to the data stored in the cell array 110 and outputting it to the output circuit 170.
If it is not necessary to amplify the potential generated by the column driver 142 and the potential output from the cell array 110, the sense amplifier 143 can be omitted.

The precharge circuit 144 has a function of precharging the wiring BLa and the wiring BLb to a predetermined potential and a function of making the wiring BLa and the wiring BLb floating.

The control circuit 160 is a logic circuit having a function of controlling the overall operation of the drive circuit unit 120, and has a function of generating a signal for controlling the operation of the drive circuit 130 and the drive circuit 140. Specifically, the control circuit 160 has a function of generating a control signal by performing a logical operation using a signal input from the outside and supplying the control signal to the drive circuit 130 and the drive circuit 140. Examples of the signal input to the control circuit 160 include a chip enable signal, a write enable signal, a read enable signal, and the like.

The output circuit 170 has a function of controlling the output of the data read from the cell array 110 to the outside. When the data read operation is performed, the read potential is supplied from the cell array 110 to the drive circuit 140. The read potential is amplified by the sense amplifier 143 and then output to the outside as data RDATA via the output circuit 170.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 3)
In the present embodiment, application examples of the semiconductor device or the storage device described in the above-described embodiment will be described.

<Computer>
The memory cell array 10 or the storage device 100 can be used as a storage device of a computer. FIG. 6 shows a configuration example of the computer 300. The computer 300 has an input device 310, an output device 320, a central processing unit 330, and a main storage device 340.

The central processing unit 330 includes a control circuit 331, a calculation circuit 332, a storage device 333, and a storage device 334.

The input device 310 has a function of receiving data from the outside of the computer 300.
The output device 320 has a function of outputting data to the outside of the computer 300.

The control circuit 331 includes an input device 310, an output device 320, a main storage device 340, and an arithmetic circuit 3.
32, It has a function of outputting a control signal to the storage device 333 and the storage device 334. The calculation circuit 332 has a function of performing a calculation using the input data. The storage device 333 can hold the data used for the calculation in the calculation circuit 332, and has a function as a register. The storage device 334 can store a part of the data in the main storage device 340 and has a function as a cache memory.

Although the storage device 334 is provided inside the central processing unit 330 in FIG. 6, it may be provided outside the central processing unit 330, or the storage device 330 may be provided outside the central processing unit 330.
It may be provided both inside and outside the. Further, a plurality of storage devices 334 may be provided both inside and outside the central processing unit 330. When the storage device 334 is provided both inside and outside the central processing unit 330, the storage device 334 provided inside can be used as a primary cache, and the storage device 33 provided outside can be used.
4 can be used as a secondary cache.

The storage device 333 and the storage device 334 can operate at a higher speed than the main storage device 340. Further, the capacity of the main storage device 340 is larger than the capacity of the storage device 334, and the storage device 334
The capacity of is larger than the capacity of the storage device 333.

By providing the storage device 334 having a function as a cache memory, the processing speed of the central processing unit 330 can be improved.

The memory cell array 10 or the storage device 100 in the above embodiment is the storage device 334.
, Or is preferably used for the main storage device 340. As a result, a highly reliable computer can be realized.

<Display system>
The memory cell array 10 or the storage device 100 can also be used for a device other than a computer, for example, a storage device built in a circuit used to drive a display device. FIG. 7 shows a configuration example of a display system 400 having a display unit 410 and a control circuit 420 having a function of driving the display unit 410.

The control circuit 420 includes an interface 421, a frame memory 422, and a decoder 423.
, Sensor controller 424, controller 425, clock generation circuit 426, image processing unit 430, storage device 441, timing controller 442, register 443, drive circuit 450, and touch sensor controller 461.

The control circuit 420 has a function of generating a signal for displaying a predetermined video (hereinafter, also referred to as a video signal) and outputting the signal to the display unit 410. The display unit 410 has a function of displaying an image on the display unit 411 using the image signal input from the control circuit 420. Also,
The display unit 410 may have a touch sensor unit 412 having a function of obtaining information such as the presence / absence of touch and the touch position. When the display unit 410 does not have the touch sensor unit 412, the touch sensor controller 461 can be omitted.

As the display unit 411, a display unit that displays using a liquid crystal element, a display unit that displays using a light emitting element, and the like can be used. The number of display units 411 provided in the display unit 410 may be one or two or more. As an example, FIG. 7 shows a configuration in which the display unit 410 includes a display unit 411a that displays using a reflective liquid crystal element and a display unit 411b that displays using a light emitting element.

Further, a reflective display element other than the reflective liquid crystal element can be used for the display unit 411. For example, the display unit 411 has a shutter type MEMS (Micro).
Electro Mechanical System) element, optical interference type MEMS
A display element to which an element, a microcapsule method, an electrophoresis method, an electrowetting method or the like is applied can be used.

Further, as a light emitting element, for example, an OLED (Organic Light Emitt)
ing Diode), LED (Light Emitting Diode), QLE
A self-luminous light emitting element such as D (Quantum-dot Light Emitting Diode) or a semiconductor laser can be used.

The drive circuit 450 has a source driver 451. The source driver 451 is a circuit having a function of supplying a video signal to the display unit 411. In FIG. 7, the display unit 4
Since 10 has a display unit 411a and a display unit 411b, the drive circuit 450 has a source driver 451a and a source driver 451b. The source driver 451a
The source driver 451b has a function of supplying a video signal to the display unit 411a, and the source driver 451b has a function of supplying a video signal to the display unit 411b. The source driver 451 may be provided on the display unit 410.

Communication between the control circuit 420 and the host 470 is performed via the interface 421. Data corresponding to the image displayed on the display unit 410 (hereinafter, also referred to as image data), various control signals, and the like are sent from the host 470 to the control circuit 420. Also, the control circuit 420
Information such as the presence / absence of touch and the touch position acquired by the touch sensor controller 461 is sent to the host 470. Each circuit of the control circuit 420 is appropriately discarded according to the specifications of the host 470, the specifications of the display unit 410, and the like.

The frame memory 422 is a storage circuit having a function of storing image data input to the control circuit 420. When the compressed image data is sent from the host 470 to the control circuit 420, the frame memory 422 can store the compressed image data. The decoder 423 is a circuit for decompressing the compressed image data. If it is not necessary to decompress the image data, the decoder 423 does not perform any processing. The decoder 423 can also be arranged between the frame memory 422 and the interface 421.

The image processing unit 430 has a function of performing various image processing on the image data input from the frame memory 422 or the decoder 423 to generate a video signal. For example, the image processing unit 430 has a gamma correction circuit 431, a dimming circuit 432, and a toning circuit 433.

Further, when the source driver 451b has a circuit (current detection circuit) having a function of detecting the current flowing through the light emitting element of the display unit 411b, the image processing unit 430 has an E.
The L correction circuit 434 may be provided. The EL correction circuit 434 has a function of adjusting the brightness of the light emitting element based on the signal transmitted from the current detection circuit.

The video signal generated by the image processing unit 430 is output to the drive circuit 450 via the storage device 441. The storage device 441 has a function of temporarily storing image data. The source driver 451a and the source driver 451b each have a function of performing various processes on the video signal input from the storage device 441 and outputting the video signal to the display unit 411a and the display unit 411b.

The timing controller 442 includes a drive circuit 450 and a touch sensor controller 461.
, Has a function of generating a timing signal or the like used in the gate driver of the display unit 411.

The touch sensor controller 461 has a function of controlling the operation of the touch sensor unit 412. The signal including the touch information detected by the touch sensor unit 412 is processed by the touch sensor controller 461 and then processed by the host 47 via the interface 421.
It is sent to 0. The host 470 generates image data reflecting the touch information and transmits it to the control circuit 420. The control circuit 420 may have a function of reflecting touch information in the image data. Further, the touch sensor controller 461 is a touch sensor unit 4.
It may be provided in 12.

The clock generation circuit 426 has a function of generating a clock signal used in the control circuit 420. The controller 425 has a function of processing various control signals sent from the host 470 via the interface 421 and controlling various circuits in the control circuit 420. Further, the controller 425 has a function of controlling power supply to various circuits in the control circuit 420. For example, the controller 425 can temporarily cut off the power supply to the stopped circuit.

The register 443 has a function of storing data used for the operation of the control circuit 420. Examples of the data stored in the register 443 include parameters used by the image processing unit 430 to perform correction processing, parameters used by the timing controller 442 to generate waveforms of various timing signals, and the like. The register 443 can be configured by a scan chain register composed of a plurality of registers.

Further, the control circuit 420 may be provided with a sensor controller 424 connected to the optical sensor 480. The optical sensor 480 has a function of detecting external light 481 and generating a detection signal. The sensor controller 424 has a function of generating a control signal based on the detection signal. The control signal generated by the sensor controller 424 is output to, for example, the controller 425.

When the display unit 411a and the display unit 411b display the same image, the image processing unit 430 has a function of separately generating the image signal of the display unit 411a and the image signal of the display unit 411b. In this case, the reflection intensity of the reflective liquid crystal element of the display unit 411a and the emission intensity of the light emitting element of the display unit 411b are determined according to the brightness of the external light 481 measured by the optical sensor 480 and the sensor controller 424. And can be adjusted. Here, the adjustment is referred to as dimming or dimming processing. Further, the circuit that executes the process is called a dimming circuit.

For example, when displaying an image on the display unit 410 outside during the daytime on a sunny day, the display is performed only by the reflective liquid crystal element without illuminating the light emitting element, and the image is displayed on the display unit 410 at night or in a dark place. When displaying, the light emitting element can be illuminated to perform the display.

Further, the image processing unit 430 has a video signal for displaying only with the display unit 411a, a video signal for displaying only with the display unit 411b, a display unit 411a and a display unit 411b according to the brightness of the external light. Can be selected and generated from any of the video signals for display in combination with. As a result, good display can be performed in both an environment with bright outside light and an environment with dark outside light. Further, in an environment where the outside light is bright, the power consumption can be reduced by not illuminating the light emitting element or by lowering the brightness of the light emitting element.

Further, the color tone can be corrected by combining the display of the light emitting element with the display of the reflective liquid crystal element. For such color tone correction, a function for measuring the color tone of the external light 481 may be added to the optical sensor 480 and the sensor controller 424. For example, when displaying an image on the display unit 410 in a reddish environment at dusk, the B (blue) component is not sufficient only by the display by the reflective liquid crystal element, so the color tone is corrected by causing the light emitting element to emit light. be able to. Here, the correction is referred to as toning or toning processing. Further, the circuit that executes the process is called a toning circuit.

Depending on the specifications of the display unit 410, the image processing unit 430 may include an RGB-RGBW conversion circuit or the like.
It may have another processing circuit. The RGB-RGBW conversion circuit is a circuit having a function of converting RGB (red, green, blue) image data into RGBW (red, green, blue, white) image signals. That is, when the display unit 410 has RGBW 4-color pixels, W (white) in the image data.
Power consumption can be reduced by displaying the components using W (white) pixels. The RGB-RGBW conversion circuit is not limited to this, and for example, RGB-RGBY (red, green, blue,
Yellow) A conversion circuit or the like may be used.

Further, the display unit 411a and the display unit 411b can display different images. The reflective liquid crystal element has a slower operating speed than the light emitting element, and it may take time to display an image. Therefore, for example, the above problem can be solved by displaying a still image as a background on a reflective liquid crystal element and displaying a moving image on a light emitting element. Further, at this time, the frequency of rewriting the image displayed on the reflective liquid crystal element is reduced, and the source driver 451a and the display unit 41 are used during the period when the image is not rewritten.
The operation of the gate driver included in 1a can be stopped. As a result, both smooth moving image display and low power consumption can be achieved at the same time. In this case, the frame memory 422 is provided with an area for storing the video signal supplied to the reflective liquid crystal element and an area for storing the video signal supplied to the light emitting element.

As the frame memory 422 or the storage device 441 in FIG. 7, the memory cell array 10 or the storage device 100 described in the above embodiment can be used. Thereby, a highly reliable control circuit or display system can be realized.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 4)
In the present embodiment, a configuration example of a display device that can be used in the display system described in the third embodiment will be described. The display device described below can be used for the display unit 410 in FIG. Here, in particular, a display device capable of performing display using a reflective liquid crystal element and a light emitting element will be described.

FIG. 8A is a block diagram showing an example of the configuration of the display device 500. Display device 500
Has a plurality of pixel units 502 arranged in a matrix in the pixel unit 501. Also,
The display device 500 includes a drive circuit 503a and a drive circuit 503b, and a drive circuit 504a and a drive circuit 504b. Further, the display device 500 includes a plurality of pixel units 5 arranged in the direction R.
02, a plurality of wiring GLa connected to the drive circuit 503a, a plurality of pixel units 502 arranged in the direction R, and a plurality of wiring GLb connected to the drive circuit 503b. Further, the display device 500 includes a plurality of pixel units 502 arranged in the direction C and a drive circuit 50.
It has a plurality of wiring SLas connected to 4a, a plurality of pixel units 502 arranged in the direction C, and a plurality of wiring SLbs connected to the drive circuit 504b.

The drive circuit 504a and the drive circuit 504b are the source drivers 451 in FIG. 7, respectively.
a, corresponds to the source driver 451b. That is, the display device 500 corresponds to the configuration in which the source driver 451a and the source driver 451b in FIG. 7 are provided in the display unit 410. However, the drive circuit 504a and the drive circuit 504b may be provided in the control circuit 420 in FIG. 7.

The pixel unit 502 includes a reflective liquid crystal element and a light emitting element. Pixel unit 502
In the above, the liquid crystal element and the light emitting element have portions that overlap each other.

FIG. 8B1 shows a configuration example of the conductive layer 530b included in the pixel unit 502. The conductive layer 530b functions as a reflective electrode of the liquid crystal element in the pixel unit 502. Further, the conductive layer 530b is provided with an opening 540.

In FIG. 8 (B1), the light emitting element 520 located in the region overlapping the conductive layer 530b is shown by a broken line. The light emitting element 520 is arranged so as to overlap the opening 540 of the conductive layer 530b. As a result, the light emitted by the light emitting element 520 is emitted toward the display surface side through the opening 540.

In FIG. 8 (B1), the pixel units 502 adjacent to the direction R are pixels corresponding to different colors. At this time, as shown in FIG. 8B, it is preferable that the two pixels adjacent to the direction R are provided at different positions of the conductive layer 530b so that the openings 540 are not arranged in a row. As a result, the two light emitting elements 520 can be separated from each other, and the light emitting element 520 can be separated.
It is possible to suppress a phenomenon (also referred to as crosstalk) in which the light emitted by the light is incident on the colored layer of the adjacent pixel unit 502. Further, since the two adjacent light emitting elements 520 can be arranged apart from each other, a high-definition display device can be realized even when the EL layer of the light emitting element 520 is formed separately by a shadow mask or the like.

Further, the arrangement may be as shown in FIG. 8 (B2).

If the value of the ratio of the total area of the opening 540 to the total area of the non-opening is too large, the display using the liquid crystal element becomes dark. Further, if the value of the ratio of the total area of the opening 540 to the total area of the non-opening is too small, the display using the light emitting element 520 becomes dark.

Further, if the area of the opening 540 provided in the conductive layer 530b functioning as the reflective electrode is too small, the efficiency of the light that can be extracted from the light emitted by the light emitting element 520 is lowered.

The shape of the opening 540 can be, for example, a polygon, a quadrangle, an ellipse, a circle, a cross, or the like. Further, it may have an elongated streak shape, a slit shape, or a checkered pattern shape. Further, the opening 540 may be arranged close to the adjacent pixel. Preferably, the aperture 540 is placed closer to other pixels displaying the same color. As a result, crosstalk can be suppressed.

<Circuit configuration example>
FIG. 9 is a circuit diagram showing a configuration example of the pixel unit 502. FIG. 9 shows two adjacent pixel units 502. The pixel unit 502 has pixels 505a and pixels 505b, respectively.

The pixel 505a includes a switch SW1, a capacitance element C10, and a liquid crystal element 510, and the pixel 50
Reference numeral 5b includes a switch SW2, a transistor M, a capacitance element C20, and a light emitting element 520. Further, the pixel 505a is connected to the wiring SLa, the wiring GLa, and the wiring CSCOM, and the pixel 505b is connected to the wiring GLb, the wiring SLb, and the wiring ANO. Note that FIG. 9
Shows the wiring VCOM1 connected to the liquid crystal element 510 and the wiring VCOM2 connected to the light emitting element 520. Further, FIG. 9 shows an example in which a transistor is used for the switch SW1 and the switch SW2.

The gate of the switch SW1 is connected to the wiring GLa, and one of the source and drain is the wiring S.
It is connected to La, and the other of the source or drain is connected to one electrode of the capacitive element C10 and one electrode of the liquid crystal element 510. The other electrode of the capacitive element C10 is the wiring CSCO.
It is connected to M. The other electrode of the liquid crystal element 510 is connected to the wiring VCOM1.

The gate of the switch SW2 is connected to the wiring GLb, and one of the source and the drain is the wiring S.
It is connected to Lb, and the other of the source or drain is connected to one electrode of the capacitive element C20, the gate of the transistor M. The other electrode of the capacitive element C20 is connected to one of the source or drain of the transistor M, the wiring ANO. The other of the source or drain of the transistor M is connected to one electrode of the light emitting element 520. The other electrode of the light emitting element 520 is connected to the wiring VCOM2.

FIG. 9 shows an example in which the transistor M has a pair of gates and these are connected to each other. As a result, the current that can be passed through the transistor M can be increased.

A predetermined potential can be supplied to each of the wiring VCOM 1 and the wiring CSCOM. Further, the wiring VCOM2 and the wiring ANO can each be supplied with a potential for generating a potential difference that enables the light emitting element 520 to emit light.

The pixel unit 502 shown in FIG. 9 is wired GL when, for example, displaying a reflection mode.
By driving the pixel 505a with the signals supplied to the a and the wiring SLa, it is possible to display an image by utilizing the optical modulation by the liquid crystal element 510. Further, when the display is performed in the transmission mode, the light emitting element 520 can be made to emit light and the image can be displayed by driving the pixel 505b by the signals supplied to the wiring GLb and the wiring SLb. When driving in both modes, the pixels 505a and the pixel 505b can be driven by the signals supplied to the wiring GLa, the wiring GLb, the wiring SLa, and the wiring SLb, respectively.

Note that FIG. 9 shows an example in which one pixel unit 502 has one liquid crystal element 510 and one light emitting element 520, but the present invention is not limited to this. For example, as shown in FIG. 10A, the pixel 505b may have a plurality of sub-pixels 506b (sub-pixels 506br, sub-pixels 506bb, sub-pixels 506bb, sub-pixels 506bw). Sub-pixel 506br, sub-pixel 506
The pg, the sub-pixel 506 bb, and the sub-pixel 506 bw are the light emitting element 520r and the light emitting element 5, respectively.
It has 20 g, a light emitting element 520b, and a light emitting element 520w. Unlike FIG. 9, the pixel unit 502 shown in FIG. 10A is a pixel capable of displaying full color with one pixel unit.

In FIG. 10A, wiring GLba, wiring GLbb, wiring SLba, wiring SLbb, and wiring ANO are connected to the pixel 505b.

In the example shown in FIG. 10 (A), for example, four light emitting elements 520 are red (R).
, Green (G), blue (B), and white (W) can be used. Further, as the liquid crystal element 510, a reflective liquid crystal element exhibiting white color can be used. As a result, when displaying the reflection mode, it is possible to display white with high reflectance.
Further, when the display is performed in the transmission mode, the display with high color rendering property can be performed with low power.

Further, FIG. 10B shows a configuration example of the pixel unit 502. Pixel unit 5
02 has a light emitting element 520w that overlaps with the opening of the conductive layer 530, a light emitting element 520r arranged around the conductive layer 530, a light emitting element 520g, and a light emitting element 520b.
It is preferable that the light emitting element 520r, the light emitting element 520 g, and the light emitting element 520b have substantially the same light emitting area.

<Display device configuration example>
FIG. 11 is a schematic perspective view of the display device 500 according to one aspect of the present invention. The display device 500
It has a structure in which a substrate 551 and a substrate 561 are bonded together. In FIG. 11, the substrate 561 is shown by a broken line.

The display device 500 has a display area 562, a circuit 564, wiring 565, and the like. Board 551
Is provided with, for example, a circuit 564, wiring 565, and a conductive layer 530b that functions as a pixel electrode. Further, FIG. 11 shows an example in which the IC 573 and the FPC 57 2 are mounted on the substrate 551. Therefore, the configuration shown in FIG. 11 can be said to be a display module having a display device 500, FPC572, and IC573.

As the circuit 564, for example, a circuit that functions as a drive circuit 504 can be used.

The wiring 565 has a function of supplying signals and electric power to the display area 562 and the circuit 564. The signal and electric power are input to the wiring 565 from the outside or from the IC 573 via the FPC 572.

Further, in FIG. 11, the substrate 551 is used by a COG (Chip On Glass) method or the like.
An example in which the IC 573 is provided is shown. The IC573 is, for example, a drive circuit 503,
Alternatively, an IC having a function as a drive circuit 504 or the like can be applied. When the display device 500 includes a circuit that functions as a drive circuit 503 and a drive circuit 504, or when the drive circuit 503
A circuit that functions as a drive circuit 504 is provided externally, and a display device 50 is provided via the FPC 57
In the case of inputting a signal for driving 0, the IC 573 may not be provided. Further, the IC573 is used in the FPC5 by the COF (Chip On Film) method or the like.
It may be mounted on 72.

FIG. 11 shows an enlarged view of a part of the display area 562. In the display area 562, the conductive layers 530b of the plurality of display elements are arranged in a matrix. The conductive layer 530b has a function of reflecting visible light, and functions as a reflecting electrode of the liquid crystal element 510 described later.

Further, as shown in FIG. 11, the conductive layer 530b has an opening. Further, the light emitting element 520 is provided on the substrate 551 side of the conductive layer 530b. The light from the light emitting element 520 is the conductive layer 53.
It is ejected to the substrate 561 side through the opening of 0b.

12 shows a part of the display device illustrated in FIG. 11 including the FPC 572, circuit 564.
An example of a cross section when a part of the area including the display area 562 and a part of the area including the display area 562 are cut is shown.

The display device 500 has an insulating layer 720 between the substrate 551 and the substrate 561. Further, between the substrate 551 and the insulating layer 720, a light emitting element 520, a transistor 701, and a transistor 70
5. It has a transistor 706, a colored layer 634, and the like. Further, a liquid crystal element 510, a colored layer 631 and the like are provided between the insulating layer 720 and the substrate 561. Further, the substrate 561 and the insulating layer 720 are bonded via the adhesive layer 641, and the substrate 551 and the insulating layer 720 are bonded via the adhesive layer 642.

The transistor 706 is connected to the liquid crystal element 510, and the transistor 705 is connected to the light emitting element 520. Since both the transistor 705 and the transistor 706 are formed on the surface of the insulating layer 720 on the substrate 551 side, they can be manufactured by using the same process.

The substrate 561 is provided with a colored layer 631, a light-shielding layer 632, an insulating layer 621, a conductive layer 613 that functions as a common electrode for the liquid crystal element 510, an alignment film 633b, an insulating layer 617, and the like. The insulating layer 617 functions as a spacer for holding the cell gap of the liquid crystal element 510.

Insulating layers such as an insulating layer 711, an insulating layer 712, an insulating layer 713, an insulating layer 714, an insulating layer 715, and an insulating layer 716 are provided on the substrate 551 side of the insulating layer 720. The insulating layer 711 is
A part of it functions as a gate insulator for each transistor. Insulation layer 712, insulation layer 713
, And the insulating layer 714 is provided so as to cover each transistor. Further, an insulating layer 716 is provided so as to cover the insulating layer 714. The insulating layer 714 and the insulating layer 716 have a function as a flattening layer. Here, the case where three layers of the insulating layer 712, the insulating layer 713, and the insulating layer 714 are provided as the insulating layer covering the transistor and the like is shown, but the present invention is not limited to this.
It may have more than one layer, a single layer, or two layers. Further, the insulating layer 714 that functions as a flattening layer may not be provided if it is unnecessary.

Further, in the transistor 701, the transistor 705, and the transistor 706, a conductive layer 721 partially functions as a gate and a conductive layer 7 partially functions as a source or drain.
22. It has a semiconductor layer 731. Here, the same hatching pattern is attached to a plurality of layers obtained by processing the same film.

The liquid crystal element 510 is a reflective liquid crystal element. The liquid crystal element 510 has a structure in which the conductive layer 530a, the liquid crystal 612, and the conductive layer 613 are laminated. Further, a conductive layer 530b that reflects visible light is provided in contact with the substrate 551 side of the conductive layer 530a. The conductive layer 530b has an opening 54
Has 0. Further, the conductive layer 530a and the conductive layer 613 include a material that transmits visible light. Further, an alignment film 633a is provided between the liquid crystal 612 and the conductive layer 530a, and the liquid crystal 612 and the conductive layer 61 are provided.
An alignment film 633b is provided between the three. Further, on the outer surface of the substrate 561, a polarizing plate 6 is formed.
Has 30.

In the liquid crystal element 510, the conductive layer 530b has a function of reflecting visible light, and the conductive layer 61
Reference numeral 3 has a function of transmitting visible light. The light incident from the substrate 561 side is polarized by the polarizing plate 630, passes through the conductive layer 613 and the liquid crystal 612, and is reflected by the conductive layer 530b. Then, it passes through the liquid crystal 612 and the conductive layer 613 again and reaches the polarizing plate 630. At this time, the conductive layer 5
The orientation of the liquid crystal can be controlled by the voltage applied between the 30b and the conductive layer 613, and the optical modulation of light can be controlled. That is, the intensity of the light emitted through the polarizing plate 630 can be controlled. Further, the light is absorbed by the colored layer 631 in a wavelength region other than the specific wavelength region, so that the extracted light becomes, for example, red light.

The light emitting element 520 is a bottom emission type light emitting element. The light emitting element 520 has a structure in which the conductive layer 691, the EL layer 692, and the conductive layer 693b are laminated in this order from the insulating layer 720 side. Further, the conductive layer 693a is provided so as to cover the conductive layer 693b. Conductive layer 693
b contains a material that reflects visible light, and the conductive layer 691 and the conductive layer 693a include a material that transmits visible light. The light emitted by the light emitting element 520 includes a colored layer 634, an insulating layer 720, and an opening 540.
It is ejected to the substrate 561 side via the conductive layer 613 and the like.

Here, as shown in FIG. 12, it is preferable that the opening 540 is provided with a conductive layer 530a that transmits visible light. As a result, even in the region overlapping the opening 540, the liquid crystal 612 is oriented in the same manner as in the other regions, so that it is possible to prevent the liquid crystal from being misaligned at the boundary between these regions and causing unintended light leakage. ..

Here, a linear polarizing plate may be used as the polarizing plate 630 arranged on the outer surface of the substrate 561, but a circular polarizing plate may also be used. As the circular polarizing plate, for example, a linear polarizing plate and a 1/4 wavelength retardation plate laminated can be used. Thereby, the reflection of external light can be suppressed. Further, the desired contrast may be realized by adjusting the cell gap, orientation, driving voltage, etc. of the liquid crystal element used for the liquid crystal element 510 according to the type of the polarizing plate.

Further, an insulating layer 717 is provided on the insulating layer 716 that covers the end portion of the conductive layer 691. The insulating layer 717 has a function as a spacer that prevents the insulating layer 720 and the substrate 551 from coming closer to each other than necessary. Further, when the EL layer 692 or the conductive layer 693a is formed by using a shielding mask (metal mask), it has a function as a mask gapper for suppressing the shielding mask from coming into contact with the surface to be formed. May be good. The insulating layer 717 may not be provided if it is unnecessary.

One of the source and drain of the transistor 705 is a light emitting element 5 via a conductive layer 724.
It is connected to 20 conductive layers 691.

One of the source and drain of the transistor 706 is a conductive layer 53 via the connection portion 707.
It is connected to 0b. The conductive layer 530b and the conductive layer 530a are provided in contact with each other, and they are connected to each other. Here, the connecting portion 707 is a portion that connects the conductive layers provided on both sides of the insulating layer 720 via the openings provided in the insulating layer 720.

A connecting portion 704 is provided in a region of the substrate 551 that does not overlap with the substrate 561. The connection portion 704 is connected to the FPC 572 via the connection layer 742. The connection unit 704 has the same configuration as the connection unit 707. On the upper surface of the connecting portion 704, the conductive layer obtained by processing the same conductive film as the conductive layer 530a is exposed. As a result, the connection part 704 and FPC57
2 can be connected via the connection layer 742.

A connecting portion 752 is provided in a part of the region where the adhesive layer 641 is provided. Connection part 7
In 52, the conductive layer obtained by processing the same conductive film as the conductive layer 530a, and the conductive layer 61.
A part of 3 is connected by the connecting body 743. Therefore, the signal or potential input from the FPC 57 2 connected to the substrate 551 side can be supplied to the conductive layer 613 formed on the substrate 561 side via the connecting portion 752.

As the connecting body 743, for example, conductive particles can be used. As the conductive particles, those obtained by coating the surface of particles such as organic resin or silica with a metal material can be used. It is preferable to use nickel or gold as the metal material because the contact resistance can be reduced. Further, it is preferable to use particles in which two or more kinds of metal materials are coated in layers, such as nickel being further coated with gold. Further, it is preferable to use a material that is elastically deformed or plastically deformed as the connecting body 743. At this time, the connecting body 743, which is a conductive particle, may have a shape that is crushed in the vertical direction as shown in FIG. By doing so, the contact area between the connecting body 743 and the conductive layer electrically connected to the connecting body 743 can be increased, the contact resistance can be reduced, and the occurrence of defects such as poor connection can be suppressed.

The connecting body 743 is preferably arranged so as to be covered with the adhesive layer 641. For example, the connector 743 may be sprayed after applying a paste or the like to be the adhesive layer 641.

FIG. 12 shows an example in which the transistor 701 is provided as the circuit 564.

In FIG. 12, as an example of the transistor 701 and the transistor 705, a configuration in which the semiconductor layer 731 on which a channel is formed is sandwiched by a pair of gates is applied. One gate is composed of a conductive layer 721, and the other gate is composed of a conductive layer 723 that overlaps with the semiconductor layer 731 via an insulating layer 712. With such a configuration, the threshold voltage of the transistor can be reliably controlled. At this time, the transistor may be driven by connecting two gates and supplying the same signal to them. Such a transistor can increase the on-current as compared with other transistors, and can increase the field effect mobility. As a result, a circuit capable of high-speed driving can be manufactured. Moreover,
It is possible to reduce the occupied area of the circuit unit. By applying a transistor with a large on-current, it is possible to reduce the signal delay in each wiring even if the number of wirings increases when the display device is enlarged or has high definition, and display unevenness is suppressed. can do.

The transistor included in the circuit 564 and the transistor included in the display area 562 are
It may have the same structure. Further, the plurality of transistors included in the circuit 564 may all have the same structure, or transistors having different structures may be used in combination. Further, the plurality of transistors included in the display area 562 may all have the same structure, or transistors having different structures may be used in combination.

For at least one of the insulating layer 712 and the insulating layer 713 covering each transistor, it is preferable to use a material in which impurities such as water and hydrogen are difficult to diffuse. That is, the insulating layer 712 or the insulating layer 713 can function as a barrier film. With such a configuration,
It is possible to effectively suppress the diffusion of impurities from the outside to the transistor, and it is possible to realize a highly reliable display device.

On the substrate 561 side, an insulating layer 621 is provided so as to cover the colored layer 631 and the light-shielding layer 632. The insulating layer 621 may have a function as a flattening layer. Since the surface of the conductive layer 613 can be made substantially flat by the insulating layer 621, the orientation state of the liquid crystal 612 can be made uniform.

An example of a method for manufacturing the display device 500 will be described. For example, the conductive layer 530a, the conductive layer 530b, and the insulating layer 720 are formed in this order on the support substrate having the release layer, and then the transistor 705, the transistor 706, the light emitting element 520, and the like are formed, and then the adhesive layer 642 is used. The substrate 551 and the support substrate are bonded together. Then, the support substrate and the peeling layer are removed by peeling at the respective interfaces of the peeling layer and the insulating layer 720, and the peeling layer and the conductive layer 530a. Separately from this, a substrate 561 on which a colored layer 631, a light-shielding layer 632, a conductive layer 613, and the like are previously formed is prepared. Then, the liquid crystal 612 is dropped onto the substrate 551 or the substrate 561, and the substrate 551 and the substrate 561 are bonded to each other by the adhesive layer 641, so that the display device 500 can be manufactured.

As the release layer, a material that causes release at the interface between the insulating layer 720 and the conductive layer 530a can be appropriately selected. In particular, as the release layer, a layer containing a refractory metal material such as tungsten and a layer containing an oxide of the metal material are laminated and used, and as an insulating layer 720 on the release layer, silicon nitride, silicon oxide nitride, or oxidation oxide is used. It is preferable to use a layer in which a plurality of layers such as silicon are laminated. When a refractory metal material is used for the release layer, it is possible to raise the formation temperature of the layer to be formed later, reduce the concentration of impurities, and realize a highly reliable display device.

As the conductive layer 530a, it is preferable to use a metal oxide, a metal nitride, or the like. When a metal oxide is used, a material in which at least one of the concentrations of hydrogen, boron, phosphorus, nitrogen, and other impurities and the amount of oxygen deficiency is higher than that of the semiconductor layer used for the transistor is used in the conductive layer 530a. It may be used for.

In the following, each component shown above will be described.

[substrate]
A material having a flat surface can be used for the substrate of the display device. A material that transmits the light is used for the substrate on the side that extracts the light from the display element. For example, materials such as glass, quartz, ceramics, sapphire, and organic resins can be used.

By using a thin substrate, it is possible to reduce the weight and thickness of the display device. Further, by using a substrate having a thickness sufficient to have flexibility, a display device having flexibility can be realized.

Further, since the substrate on the side that does not emit light does not have to have translucency, a metal substrate or the like can be used in addition to the substrates listed above. Since the metal substrate has high thermal conductivity and can easily conduct heat to the entire substrate, it is possible to suppress a local temperature rise of the display device, which is preferable. In order to obtain flexibility and bendability, the thickness of the metal substrate is preferably 10 μm or more and 200 μm or less, and more preferably 20 μm or more and 50 μm or less.

The material constituting the metal substrate is not particularly limited, and for example, a metal such as aluminum, copper, or nickel, an aluminum alloy, an alloy such as stainless steel, or the like can be preferably used.

Further, a substrate that has been subjected to an insulating treatment by oxidizing the surface of the metal substrate or forming an insulating film on the surface may be used. For example, an insulating film may be formed by using a coating method such as a spin coating method or a dip method, an electrodeposition method, a vapor deposition method, a sputtering method, or the like, or the insulating film may be left in an oxygen atmosphere or heated, or may be anodized. An oxide film may be formed on the surface of the substrate by such means.

Examples of the material having flexibility and transparency to visible light include glass having a thickness sufficient to have flexibility, polyester resin such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), and polyacrylonitrile resin. , Polyimide resin, Polymethyl methacrylate resin, Polycarbonate (PC) resin, Polyester sulfone (PE)
S) Resin, polyamide resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyvinyl chloride resin, polytetrafluoroethylene (PTFE) resin and the like can be mentioned. In particular, it is preferable to use a material having a low coefficient of thermal expansion, for example, a coefficient of thermal expansion of 30.
Polyamide-imide resin, polyimide resin, PET and the like having a value of × ^10-6 / K or less can be preferably used. Further, a substrate in which glass fibers are impregnated with an organic resin or a substrate in which an inorganic filler is mixed with an organic resin to reduce the coefficient of thermal expansion can also be used. Since a substrate using such a material is light in weight, a display device using the substrate can also be made lightweight.

When a fiber body is contained in the above material, a high-strength fiber of an organic compound or an inorganic compound is used as the fiber body. The high-strength fiber specifically refers to a fiber having a high tensile elasticity or young ratio, and typical examples thereof include polyvinyl alcohol-based fiber, polyester-based fiber, polyamide-based fiber, polyethylene-based fiber, and aramid-based fiber. Polyparaphenylene benzobisoxazole fiber, glass fiber, or carbon fiber can be mentioned. As glass fibers, E glass and S
Examples thereof include glass fibers using glass, D glass, Q glass and the like. These may be used in the state of a woven fabric or a non-woven fabric, and a structure obtained by impregnating the fiber body with a resin and curing the resin may be used as a flexible substrate. It is preferable to use a structure made of a fibrous body and a resin as the flexible substrate because the reliability against breakage due to bending or local pressing is improved.

Alternatively, glass, metal, or the like thin enough to have flexibility can be used for the substrate. Alternatively, a composite material in which glass and a resin material are bonded by an adhesive layer may be used.

On a flexible substrate, a hard coat layer (for example, silicon nitride, aluminum oxide, etc.) that protects the surface of the display device from scratches, and a layer of a material that can disperse pressure (for example, aramid resin, etc.). Etc. may be laminated. Further, in order to suppress a decrease in the life of the display element due to moisture or the like, an insulating film having low water permeability may be laminated on the flexible substrate. For example, silicon nitride, silicon oxide, silicon nitride, aluminum oxide,
Inorganic insulating materials such as aluminum nitride can be used.

The substrate can also be used by stacking a plurality of layers. In particular, when the structure has a glass layer, the barrier property against water and oxygen can be improved, and a highly reliable display device can be obtained.

[Transistor]
The transistor has a conductive layer that functions as a gate electrode, an insulating layer that functions as a gate insulator, a semiconductor layer, a conductive layer that functions as a source electrode, and a conductive layer that functions as a drain electrode. The above shows the case where a transistor having a bottom gate structure is applied.

The structure of the transistor included in the display device of one aspect of the present invention is not particularly limited. For example, it may be a planar type transistor, a stagger type transistor, or an inverted stagger type transistor. Further, either a top gate type or bottom gate type transistor structure may be used. Alternatively, gate electrodes may be provided above and below the semiconductor layer on which the channel is formed.

[Semiconductor layer]
The crystallinity of the material used for the semiconductor layer of the transistor is not particularly limited, and is an amorphous semiconductor, a semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor having a partially crystalline region). Any of the above may be used. It is preferable to use a semiconductor having crystallinity because deterioration of transistor characteristics can be suppressed.

Further, for the semiconductor layer of the transistor, for example, a material such as a Group 14 element (silicon, germanium, etc.) or a metal oxide can be used. Typically, a semiconductor containing silicon, a semiconductor containing gallium arsenide, a metal oxide containing indium, or the like can be applied.

In particular, it is preferable to apply a metal oxide having a bandgap larger than that of silicon.
It is preferable to use a semiconductor material having a larger bandgap and a smaller carrier density than silicon because the current in the off state of the transistor can be reduced.

A transistor using a metal oxide having a bandgap larger than that of silicon can retain the electric charge accumulated in the capacitance connected in series with the transistor for a long period of time due to its low off-current. By applying such a transistor to a pixel, it is possible to stop the drive circuit while maintaining the gradation of the image displayed in each display area. As a result, it is possible to realize a display device with extremely reduced power consumption.

The semiconductor layer is represented by, for example, an In-M-Zn-based oxide containing at least indium, zinc and M (metals such as aluminum, titanium, gallium, germanium, ittrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium). It is preferable to include a film to be used. Further, in order to reduce variations in the electrical characteristics of the transistor using the semiconductor layer, it is preferable to include a stabilizer together with them.

Examples of the stabilizer include gallium, tin, hafnium, aluminum, zirconium and the like, including the metal described in M above. Other stabilizers include lanthanoids such as lanthanide, cerium, placeodimium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

Examples of the metal oxide constituting the semiconductor layer include In-Ga-Zn-based oxide and In-A.
l-Zn-based oxide, In-Sn-Zn-based oxide, In-Hf-Zn-based oxide, In-La
-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-
Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Z
n-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn
Oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn oxides, In-Sn-Ga-Zn oxides , In-Hf-G
a-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide Can be used.

Here, the In-Ga-Zn-based oxide means an oxide containing In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn does not matter. Also, In, Ga and Z
A metal element other than n may be contained.

Further, the semiconductor layer and the conductive layer may have the same metal element among the above oxides. By forming the semiconductor layer and the conductive layer having the same metal element, the manufacturing cost can be reduced. For example, by using a metal oxide target having the same metal composition when forming the semiconductor layer and the conductive layer, the manufacturing cost can be reduced. Further, an etching gas or an etching solution for processing the semiconductor layer and the conductive layer can be commonly used. However, the semiconductor layer and the conductive layer may have different compositions even if they have the same metal element. For example, during the manufacturing process of a transistor and a capacitive element, the metal element in the film may be desorbed to have a different metal composition.

The metal oxide constituting the semiconductor layer has a band gap of 2 eV or more, preferably 2.5 e.
It is preferably V or more, more preferably 3 eV or more. As described above, by using a metal oxide having a large bandgap, the off-current of the transistor can be reduced.

When the metal oxide constituting the semiconductor layer is In-M-Zn oxide, the atomic number ratio of the metal element of the sputtering target used for forming the In-M-Zn oxide is In ≥ M.
It is preferable that Zn ≧ M is satisfied. As the atomic number ratio of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn =
3: 1: 2, 4: 2: 4.1 and the like are preferable. The atomic number ratio of the semiconductor layer to be formed includes an error of plus or minus 40% of the atomic number ratio included in the sputtering target.

It is preferable to use a metal oxide having a low carrier density for the semiconductor layer. For example, the semiconductor layer has a carrier density of 1 × 10 ¹⁷ / cm ³ or less, preferably 1 × 10 ¹⁵ / cm ³ or less, more preferably 1 × 10 ¹³ / cm ³ or less, and more preferably 1 × 10 ¹¹ / cm. ³
Hereinafter, more preferably, a metal oxide having a carrier density of less than 1 × 10 ¹⁰ / cm ³ and a carrier density of 1 × 10 ^-9 / cm ³ or more can be used. Such a semiconductor layer has a low impurity concentration and a low defect level density, and thus provides stable electrical characteristics of the transistor.

Not limited to these, a semiconductor layer having an appropriate composition may be used according to the required electrical characteristics of the transistor (field effect mobility, threshold voltage, etc.). Further, in order to obtain the required electrical characteristics of the transistor, it is preferable that the carrier density, impurity concentration, defect density, atomic number ratio of metal element and oxygen, interatomic distance, density, etc. of the semiconductor layer are appropriate. ..

If silicon or carbon, which is one of the Group 14 elements, is contained in the metal oxide constituting the semiconductor layer, oxygen deficiency may increase in the semiconductor layer, resulting in n-type formation. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm.
It is preferably ³ or less.

Further, alkali metals and alkaline earth metals may generate carriers when combined with metal oxides, and the off-current of a transistor using the metal oxides in the semiconductor layer may increase. Therefore, the concentration of the alkali metal or alkaline earth metal obtained by the secondary ion mass spectrometry in the semiconductor layer should be 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. Is preferable.

Further, when nitrogen is contained in the metal oxide constituting the semiconductor layer, electrons as carriers are generated, the carrier density is increased, and the n-type is easily formed. As a result, a transistor using a metal oxide containing nitrogen in the semiconductor layer tends to have a normally-on characteristic. Therefore, the nitrogen concentration obtained by the secondary ion mass spectrometry in the semiconductor layer is 5 × 10 ¹⁸ atoms.
/ Cm ³ is preferably not more than.

Further, the semiconductor layer may have a non-single crystal structure, for example. Non-single crystal structures include, for example, polycrystalline structures, microcrystal structures, or amorphous structures. Among the non-single crystal structures, the amorphous structure has the highest defect level density.

Amorphous metal oxides, for example, have a disordered atomic arrangement and do not have a crystalline component.
Alternatively, the oxide film having an amorphous structure has, for example, a completely amorphous structure and has no crystal portion.

The semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystal structure region, a polycrystalline structure region, and a single crystal structure region. The mixed film may have, for example, a single-layer structure or a laminated structure including any two or more of the above-mentioned regions.

Alternatively, it is preferable to use silicon for the semiconductor layer on which the channel of the transistor is formed. Amorphous silicon may be used as the silicon, but it is particularly preferable to use crystalline silicon. For example, it is preferable to use microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like. In particular, polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and higher reliability than amorphous silicon. By applying such a polycrystalline semiconductor to a pixel, the aperture ratio of the pixel can be improved. Further, even in the case of an extremely high-definition display unit, the drive circuit can be formed on the same substrate as the pixels, and the number of components constituting the electronic device can be reduced.

The transistor having a bottom gate structure illustrated in the present embodiment is preferable in that the manufacturing process can be reduced. In addition, by using amorphous silicon for the semiconductor layer, it can be formed at a lower temperature than polycrystalline silicon, so it is possible to use materials with low heat resistance for wiring, electrodes, substrates, etc. below the semiconductor layer. You can expand your choice. For example
An extremely large area glass substrate or the like can be used. On the other hand, a transistor having a top gate structure is preferable in that it easily forms an impurity region in a self-aligned manner and can reduce variations in electrical characteristics. In particular, when polycrystalline silicon, single crystal silicon, or the like is used for the semiconductor layer, a transistor having a top gate structure is suitable.

[Conductive layer]
Materials that can be used for conductive layers such as transistor gates, sources and drains, as well as various wirings and electrodes that make up display devices include aluminum, titanium, and chromium.
Examples thereof include metals such as nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, or alloys containing the same as a main component. In addition, a film containing these materials can be used as a single layer or as a laminated structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, and a copper film on a copper-magnesium-aluminum alloy film. Two-layer structure for laminating, two-layer structure for laminating copper film on titanium film, two-layer structure for laminating copper film on tungsten film, titanium film or titanium nitride film, and aluminum film or copper film on top of it A three-layer structure, a molybdenum film or a molybdenum nitride film, on which a titanium film or a titanium nitride film is formed, and an aluminum film or a copper film are laminated on the molybdenum film or a molybdenum film. There is a three-layer structure that forms a molybdenum nitride film. Oxides such as indium oxide, tin oxide, and zinc oxide may be used. Further, it is preferable to use copper containing manganese because the controllability of the shape by etching is improved.

Further, as the conductive material having translucency, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide to which gallium is added, or graphene can be used. Alternatively, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or an alloy material containing the metal material can be used. Alternatively, a nitride of the metal material (for example, titanium nitride) or the like may be used. When a metal material or an alloy material (or a nitride thereof) is used, it may be made thin enough to have translucency. Further, the laminated film of the above material can be used as the conductive layer. For example, it is preferable to use a laminated film of an alloy of silver and magnesium and an indium tin oxide because the conductivity can be enhanced. They are,
It can also be used as a conductive layer such as various wirings and electrodes constituting a display device, and a conductive layer (a conductive layer that functions as a pixel electrode or a common electrode) of a display element.

[Insulation layer]
Examples of the insulating material that can be used for each insulating layer include resins having a siloxane bond such as acrylic and epoxy, and resins having a siloxane bond such as silicone, as well as silicon oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, and aluminum oxide. Inorganic insulating materials such as, etc. can also be used.

Further, the light emitting element is preferably provided between a pair of insulating films having low water permeability. As a result, it is possible to suppress the intrusion of impurities such as water into the light emitting element, and it is possible to suppress a decrease in the reliability of the device.

Examples of the insulating film having low water permeability include a film containing nitrogen and silicon such as a silicon nitride film and a silicon oxide film, and a film containing nitrogen and aluminum such as an aluminum nitride film. Also,
A silicon oxide film, a silicon nitride film, an aluminum oxide film or the like may be used.

For example, water vapor permeability of less water permeable insulating ^{film, 1 × 10 -5 [g /} (m 2 · day)
] Or less, preferably 1 × ^10-6 [g / (m ² · day)] or less, more preferably 1 × 1
^{0 -7 [g / (m 2} · day)] or less, more preferably ^{1 × 10 -8 [g / (} m 2 · d
ay)] The following.

[Liquid crystal element]
As the liquid crystal element, for example, vertical orientation (VA: Vertical Alignment)
A liquid crystal element to which the mode is applied can be used. The vertical orientation mode is MVA (
Multi-Domain Vertical Element) mode, PVA (
Patterned Vertical Alignment mode, ASV (Adv)
Anced Super View) mode and the like can be used.

Further, as the liquid crystal element, a liquid crystal element to which various modes are applied can be used. For example, in addition to VA mode, TN (Twisted Nematic) mode, IPS (In)
-Plane-Switching mode, FFS (Fringe Field Sw)
switching) mode, ASM (Axially Symmetrical indicator)
d Micro-cell mode, OCB (Optically Compensat)
ed Birefringence mode, FLC (Ferroelectric L)
quid Crystal) mode, AFLC (Antiferroelectric)
A liquid crystal element to which the Liquid Crystal) mode or the like is applied can be used.

The liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). The liquid crystal element includes a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, and a polymer dispersed liquid crystal (PDLC: Polymer).
Liquid crystals such as Dispersed Liquid Crystal), ferroelectric liquid crystals, and antiferroelectric liquid crystals can be used. Depending on the conditions, these liquid crystal materials have a cholesteric phase,
It shows a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like.

Further, as the liquid crystal material, either a positive type liquid crystal or a negative type liquid crystal may be used.
The optimum liquid crystal material may be used according to the applicable mode and design.

Further, in order to control the orientation of the liquid crystal, an alignment film can be provided. When the transverse electric field method is adopted, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response rate and has optical isotropic properties. Further, the liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent does not require an orientation treatment and has a small viewing angle dependence. Further, since it is not necessary to provide an alignment film, the rubbing treatment becomes unnecessary, and the electrostatic breakdown caused by the rubbing treatment can be prevented.
It is possible to reduce defects and damage of the liquid crystal display device during the manufacturing process.

Further, as the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a semi-transmissive liquid crystal element, or the like can be used. In one aspect of the present invention, it is particularly preferable to use a reflective liquid crystal element.

When a transmissive type or semi-transmissive type liquid crystal element is used, two polarizing plates are provided so as to sandwich the pair of substrates. In addition, a backlight is provided outside the polarizing plate. As a backlight,
It may be a direct type backlight or an edge light type backlight. It is preferable to use a direct-type backlight provided with an LED (Light Emitting Diode) because local dimming can be facilitated and contrast can be increased. Further, it is preferable to use an edge light type backlight because the thickness of the module including the backlight can be reduced.

When a reflective liquid crystal element is used, a polarizing plate is provided on the display surface side. In addition to this, it is preferable to arrange the light diffusing plate on the display surface side because the visibility can be improved.

Further, when a reflective or semi-transmissive liquid crystal element is used, a front light may be provided outside the polarizing plate. As the front light, it is preferable to use an edge light type front light. It is preferable to use a front light provided with an LED (Light Emitting Diode) because power consumption can be reduced.

[Light emitting element]
As the light emitting element, an element capable of self-luminous light can be used, and an element whose brightness is controlled by a current or a voltage is included in the category. For example, LED, organic EL element, inorganic EL
Elements and the like can be used.

The light emitting element includes a top emission type, a bottom emission type, and a dual emission type. A conductive film that transmits visible light is used for the electrode on the side that extracts light. Further, it is preferable to use a conductive film that reflects visible light for the electrode on the side that does not take out light. In one aspect of the present invention, it is particularly preferable to use a bottom emission type light emitting device.

The EL layer has at least a light emitting layer. The EL layer is a layer other than the light emitting layer, which is a substance having high hole injection property, a substance having high hole transport property, a hole blocking material, a substance having high electron transport property, a substance having high electron transfer property, or a bipolar substance. It may further have a layer containing a substance (a substance having high electron transport property and hole transport property) and the like.

Either a low molecular weight compound or a high molecular weight compound can be used for the EL layer, and an inorganic compound may be contained. The layers constituting the EL layer include a thin-film deposition method (including a vacuum vapor deposition method).
), Transfer method, printing method, inkjet method, coating method and the like.

When a voltage higher than the threshold voltage of the light emitting element is applied between the cathode and the anode, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer, and the luminescent substance contained in the EL layer emits light.

When a white light emitting element is applied as the light emitting element, it is preferable that the EL layer contains two or more kinds of light emitting substances. For example, white light emission can be obtained by selecting a light emitting substance so that the light emission of each of two or more light emitting substances has a complementary color relationship. For example, a luminescent substance that emits light such as R (red), G (green), B (blue), Y (yellow), O (orange), or spectral components of two or more colors of R, G, and B, respectively. Among luminescent substances showing luminescence including
It is preferable to contain 2 or more. Further, it is preferable to apply a light emitting element having two or more peaks in the spectrum of light emitted from the light emitting element within the wavelength range of the visible light region (for example, 350 nm or more and 750 nm or less). Further, the emission spectrum of the material having a peak in the yellow wavelength region is preferably a material having a spectral component also in the green and red wavelength regions.

The EL layer preferably has a structure in which a light emitting layer containing a light emitting material that emits one color and a light emitting layer containing a light emitting material that emits another color are laminated. For example, the plurality of light emitting layers in the EL layer may be laminated in contact with each other, or may be laminated via a region that does not contain any of the light emitting materials. For example, a region is provided between the fluorescent light emitting layer and the phosphorescent light emitting layer, which contains the same material as the fluorescent light emitting layer or the phosphorescent light emitting layer (for example, a host material or an assist material) and does not contain any light emitting material. May be good. This facilitates the fabrication of the light emitting element and reduces the drive voltage.

Further, the light emitting element may be a single element having one EL layer, or may be a tandem element in which a plurality of EL layers are laminated via a charge generation layer.

The conductive film that transmits visible light can be formed by using, for example, indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide added with gallium, or the like. Further, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, alloys containing these metal materials, or nitrides of these metal materials (for example, Titanium nitride) or the like can also be used by forming it thin enough to have translucency. Further, the laminated film of the above material can be used as the conductive layer. For example, it is preferable to use a laminated film of an alloy of silver and magnesium and indium tin oxide because the conductivity can be enhanced. Moreover, graphene or the like may be used.

As the conductive film that reflects visible light, for example, a metal material such as aluminum, gold, platinum, silver, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, or palladium, or an alloy containing these metal materials should be used. Can be done. Further, lanthanum, neodymium, germanium or the like may be added to the above metal materials or alloys. Further, an alloy containing titanium, nickel, or neodymium and aluminum (aluminum alloy) may be used. Also copper,
Alloys containing palladium, magnesium and silver may be used. Alloys containing silver and copper are preferable because they have high heat resistance. Further, by laminating the metal film or the metal oxide film in contact with the aluminum film or the aluminum alloy film, oxidation can be suppressed. Such a metal film,
Examples of the material of the metal oxide film include titanium and titanium oxide. Further, the conductive film that transmits visible light and the film made of a metal material may be laminated. For example, a laminated film of silver and indium tin oxide, a laminated film of an alloy of silver and magnesium and indium tin oxide, and the like can be used.

The electrodes may be formed by a vapor deposition method or a sputtering method, respectively. In addition, it can be formed by using a ejection method such as an inkjet method, a printing method such as a screen printing method, or a plating method.

The above-mentioned light emitting layer and the layer containing a substance having a high hole injecting property, a substance having a high hole transporting property, a substance having a high electron transporting property, a substance having a high electron injecting property, a bipolar substance, etc. Each of them may have an inorganic compound such as a quantum dot or a polymer compound (oligoform, dendrimer, polymer, etc.). For example, by using quantum dots in the light emitting layer, it can function as a light emitting material.

The quantum dot materials include colloidal quantum dot materials, alloy-type quantum dot materials, and the like.
A core-shell type quantum dot material, a core type quantum dot material, or the like can be used. Further, a material containing an element group of groups 12 and 16, 13 and 15 or 14 and 16 may be used. Or cadmium, selenium, zinc, sulfur, phosphorus, indium, tellurium, lead,
Quantum dot materials containing elements such as gallium, arsenide, and aluminum may be used.

[Adhesive layer]
As the adhesive layer, various curable adhesives such as a photocurable adhesive such as an ultraviolet curable type, a reaction curable type adhesive, a thermosetting type adhesive, and an anaerobic type adhesive can be used. Materials for these adhesives include epoxy resin, acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, and PVB (polyvinyl butyral).
Examples thereof include resins and EVA (ethylene vinyl acetate) resins. In particular, a material having low moisture permeability such as an epoxy resin is preferable. Further, a two-component mixed type resin may be used. Moreover, you may use an adhesive sheet or the like.

Further, the resin may contain a desiccant. For example, a substance that adsorbs water by chemical adsorption can be used, such as an oxide of an alkaline earth metal (calcium oxide, barium oxide, etc.). Alternatively, a substance that adsorbs water by physical adsorption, such as zeolite or silica gel, may be used. When a desiccant is contained, impurities such as water can be suppressed from entering the element, and the reliability of the display device is improved, which is preferable.

Further, the light extraction efficiency can be improved by mixing the resin with a filler having a high refractive index or a light scattering member. For example, titanium oxide, barium oxide, zeolite, zirconium and the like can be used.

[Connection layer]
As the connecting layer, an anisotropic conductive film (ACF: Anisotropic Condu)
ctive Film) and anisotropic conductive paste (ACP: Anisotropic C)
Onducive Paste) and the like can be used.

[Colored layer]
Examples of the material that can be used for the colored layer include a metal material, a resin material, a resin material containing a pigment or a dye, and the like.

[Shading layer]
Materials that can be used as a light-shielding layer include carbon black, titanium black, and so on.
Examples thereof include metals, metal oxides, and composite oxides containing solid solutions of a plurality of metal oxides. The light-shielding layer may be a film containing a resin material or a thin film of an inorganic material such as metal. Further, as the light-shielding layer, a laminated film of a film containing a material of a colored layer can also be used. For example, a laminated structure of a film containing a material used for a colored layer that transmits light of a certain color and a film containing a material used for a colored layer that transmits light of another color can be used. By using the same material for the colored layer and the light-shielding layer, it is preferable because the device can be shared and the process can be simplified.

The above is a description of each component.

[Example of manufacturing method]
Next, an example of a method for manufacturing a display device using a flexible substrate will be described.

Here, a layer including a display element, a circuit, a wiring, an electrode, an optical member such as a coloring layer or a light-shielding layer, and an insulating layer is collectively referred to as an element layer. For example, the element layer includes a display element and
In addition to the display element, an element such as a wiring electrically connected to the display element, a pixel, or a transistor used in a circuit may be provided.

Further, here, a member that supports the element layer and has flexibility at the stage when the display element is completed (the manufacturing process is completed) is referred to as a substrate. For example, the substrate also includes an extremely thin film having a thickness of 10 nm or more and 300 μm or less.

As a method of forming an element layer on a substrate having flexibility and having an insulating surface, there are typically the following two methods. One is a method of forming an element layer directly on the substrate. The other is a method in which the element layer is formed on a support base material different from the substrate, the element layer and the support base material are peeled off, and the element layer is transposed to the substrate. Although not described in detail here, the above 2
In addition to the above methods, there is also a method of forming an element layer on a non-flexible substrate and thinning the substrate by polishing or the like to give flexibility.

When the material constituting the substrate has heat resistance to the heat applied to the element layer forming process, it is preferable to form the element layer directly on the substrate because the process is simplified. At this time, it is preferable to form the element layer in a state where the substrate is fixed to the supporting base material because it is easy to carry the element layer in and between the devices.

Further, when the method of transferring the element layer to the substrate after forming the element layer on the support base material is used, first, the release layer and the insulating layer are laminated on the support base material, and the element layer is formed on the insulating layer. Subsequently, it is peeled off between the support base material and the element layer, and the element layer is transposed to the substrate. At this time, a material that causes peeling at the interface between the support base material and the release layer, the interface between the release layer and the insulating layer, or the release layer may be selected. In this method, by using a material having high heat resistance for the supporting base material and the release layer, the upper limit of the temperature applied when forming the element layer can be raised, and the element layer having a more reliable element is formed. It is preferable because it can be done.

For example, as the release layer, a layer containing a refractory metal material such as tungsten and a layer containing an oxide of the metal material are laminated and used, and as an insulating layer on the release layer, silicon oxide, silicon nitride, silicon oxide and silicon oxide are used. , It is preferable to use a layer in which a plurality of layers such as silicon nitride are laminated. In the present specification, the oxide nitride refers to a material having a higher oxygen content than oxygen as its composition, and the nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Point to.

Examples of the method of peeling the element layer and the supporting base material include applying a mechanical force, etching the peeling layer, and infiltrating a liquid into the peeling interface. Alternatively, the peeling may be performed by heating or cooling by utilizing the difference in thermal expansion of the two layers forming the peeling interface.

Further, if peeling is possible at the interface between the supporting base material and the insulating layer, the peeling layer may not be provided.

For example, glass can be used as the supporting base material, and an organic resin such as polyimide can be used as the insulating layer. At this time, a part of the organic resin is locally heated by using a laser beam or the like, or a part of the organic resin is physically cut or penetrated by a sharp member to form a starting point of peeling. Peeling may be performed at the interface between the glass and the organic resin.

Alternatively, a heat generating layer may be provided between the supporting base material and the insulating layer made of an organic resin, and the heat generating layer may be heated to perform peeling at the interface between the heat generating layer and the insulating layer. As the heat generating layer, various materials such as a material that generates heat by passing an electric current, a material that generates heat by absorbing light, and a material that generates heat by applying a magnetic field can be used. For example, the heat generating layer can be selected from semiconductors, metals, and insulators.

In the above method, the insulating layer made of an organic resin can be used as a substrate after peeling.

The above is an example of a method for manufacturing a display device using a flexible substrate.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 5)
In this embodiment, a configuration example of an OS transistor that can be used in the above embodiment will be described.

<Transistor configuration example>
FIG. 13A is a top view showing a configuration example of the transistor. FIG. 13 (B) is FIG.
(A) is a cross-sectional view taken along the line X1-X2, and FIG. 13 (C) is a cross-sectional view taken along the line Y1-Y2. Here, the direction of the X1-X2 line may be referred to as the channel length direction, and the direction of the Y1-Y2 line may be referred to as the channel width direction. FIG. 13B is a diagram showing a cross-sectional structure of the transistor in the channel length direction, and FIG. 13C is a diagram showing a cross-sectional structure of the transistor in the channel width direction. In addition, it should be noted
In order to clarify the device structure, some components are omitted in FIG. 13 (A).

The semiconductor device according to one aspect of the present invention includes an insulating layer 812 to an insulating layer 820, and a metal oxide film 8.
It has 21 to a metal oxide film 824 and a conductive layer 850 to a conductive layer 853. Transistor 8
01 is formed on the insulating surface. FIG. 13 illustrates a case where the transistor 801 is formed on the insulating layer 811. The transistor 801 is covered with an insulating layer 818 and an insulating layer 819.

The insulating layer, metal oxide film, conductive layer, and the like constituting the transistor 801 may be a single layer or a laminated layer of a plurality of films. For these fabrications, sputtering method, electron beam epitaxy method (MBE method), pulse laser ablation method (PLD method)
, CVD method, atomic layer deposition method (ALD method) and various other film forming methods can be used. The CVD method includes a plasma CVD method, a thermal CVD method, an organometallic CVD method, and the like.

In the transistor 801 the conductive layer 850 (conductive layer 850a, conductive layer 850b) is
It has a region that functions as a gate electrode. The conductive layer 851 and the conductive layer 852 have a region that functions as a source electrode or a drain electrode. Conductive layer 853 (conductive layer 853a, conductive layer 8)
53b) has a region that functions as a bottom gate electrode. The insulating layer 817 has a region that functions as a gate insulator on the gate electrode side, and the insulating layer composed of a laminate of the insulating layer 814 to the insulating layer 816 has a region that functions as a gate insulator on the bottom gate electrode side. Have.
The insulating layer 818 has a function as an interlayer insulating layer. The insulating layer 819 has a function as a barrier layer.

The metal oxide film 821 to the metal oxide film 824 are collectively referred to as an oxide layer 830. FIG. 13
As shown in (B) and FIG. 13 (C), the oxide layer 830 has a region in which the metal oxide film 821, the metal oxide film 822, and the metal oxide film 824 are laminated in this order. Further, the pair of metal oxide films 823 are located on the conductive layer 851 and the conductive layer 852, respectively. Transistor 8
When 01 is on, the channel region is mainly the metal oxide film 822 of the oxide layer 830.
Is formed in.

The metal oxide film 824 includes a metal oxide film 821 to a metal oxide film 823, a conductive layer 851, and the like.
It covers the conductive layer 852. The insulating layer 817 is located between the metal oxide film 824 and the conductive layer 850. The conductive layer 851 and the conductive layer 852 each have a region overlapping with the conductive layer 850 via the metal oxide film 823, the metal oxide film 824, and the insulating layer 817.

The conductive layer 851 and the conductive layer 852 are made of a hard mask for forming the metal oxide film 821 and the metal oxide film 822. Therefore, the conductive layer 851 and the conductive layer 852
Does not have a region in contact with the side surfaces of the metal oxide film 821 and the metal oxide film 822. For example, through the following steps, the metal oxide film 821, the metal oxide film 822, and the conductive layer 851
, The conductive layer 852 can be manufactured. First, a conductive film is formed on the two laminated metal oxide films. This conductive film is processed (etched) into a desired shape to form a hard mask. The hard mask is used to process the shape of the two-layer metal oxide film to form the laminated metal oxide film 821 and the metal oxide film 822. Next, the hard mask is processed into a desired shape to form the conductive layer 851 and the conductive layer 852.

The insulating materials used for the insulating layer 811 to the insulating layer 818 include aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum nitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon nitride nitride, and gallium oxide. There are germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate and so on. The insulating layer 811 to the insulating layer 818 are composed of a single layer or a laminate made of these insulating materials. Insulation layer 811
The layer constituting the insulating layer 818 may contain a plurality of insulating materials.

In order to suppress the increase in oxygen deficiency of the oxide layer 830, the insulating layer 816 to the insulating layer 818 are
It is preferably an insulating layer containing oxygen. It is more preferable that the insulating layer 816 to the insulating layer 818 are formed of an insulating film (hereinafter, also referred to as "insulating film containing excess oxygen") from which oxygen is released by heating. By supplying oxygen to the oxide layer 830 from the insulating film containing excess oxygen,
The oxygen deficiency of the oxide layer 830 can be compensated. As a result, the electrical characteristics and reliability of the transistor 801 can be improved.

The insulating film containing excess oxygen is TDS (Thermal Desorption Speed).
In ctroscopy: temperature-temperature desorption gas spectroscopy), the surface temperature of the film is 100 ° C. or higher and 70 ° C.
The amount of oxygen molecules released in the range of 0 ° C or lower, or 100 ° C or higher and 500 ° C or lower is 1 × 10 ^1.
The membrane is ⁴ molecules / cm ² or more. The amount of oxygen molecules released is 1 × 10 ¹⁵
More preferably, it is molecules / cm ² or more.

The insulating film containing excess oxygen can be formed by performing a treatment of adding oxygen to the insulating film. The treatment for adding oxygen can be performed by using heat treatment in an oxygen atmosphere, an ion implantation method, an ion doping method, a plasma imaging ion implantation method, a plasma treatment, or the like. As the gas for adding oxygen, oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , nitrous oxide gas, ozone gas, or the like can be used.

In order to prevent an increase in the hydrogen concentration in the oxide layer 830, it is preferable to reduce the hydrogen concentration in the insulating layer 812 to the insulating layer 819. In particular, it is preferable to reduce the hydrogen concentration in the insulating layer 813 to the insulating layer 818. Specifically, the hydrogen concentration is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, and 1 × 10 ¹⁹ atoms.
More preferably s / cm ³ or less, and even more preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

In order to prevent an increase in the nitrogen concentration of the oxide layer 830, it is preferable to reduce the nitrogen concentration in the insulating layer 813 to the insulating layer 818. Specifically, the nitrogen concentration is 5 × 10 ¹⁹ atoms /
Less than cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ and 1 × 10 ^1
8 atoms / cm ³ or less is more preferable, and 5 × 10 ¹⁷ atoms / cm ³ or less is further preferable.

The hydrogen concentration and nitrogen concentration listed above are the secondary ion mass spectrometry (SIMS: Secondary).
It is a value measured by Ion Mass Spectrometer).

The transistor 801 preferably has a structure in which the oxide layer 830 is surrounded by an insulating layer having a barrier property against oxygen and hydrogen (hereinafter, also referred to as a barrier layer).
With such a structure, oxygen is released from the oxide layer 830, and the oxide layer 83
It is possible to suppress the invasion of hydrogen into 0. As a result, the electrical characteristics and reliability of the transistor 801 can be improved.

For example, the insulating layer 819 functions as a barrier layer, and the insulating layer 811 and the insulating layer 812,
At least one of the insulating layers 814 may function as a barrier layer. The barrier layer can be formed of a material such as aluminum oxide, aluminum nitride, gallium oxide, gallium oxide, yttrium oxide, yttrium oxide, hafnium oxide, hafnium oxide, and silicon nitride.

A configuration example of the insulating layer 811 to the insulating layer 819 will be described. In this example, the insulating layer 811 and the insulating layer 8
12, the insulating layer 815, and the insulating layer 819 each function as a barrier layer. Insulation layer 81
6 to the insulating layer 818 is an oxide layer containing excess oxygen. The insulating layer 811 is silicon nitride, the insulating layer 812 is aluminum oxide, and the insulating layer 813 is silicon oxide.
Insulation layer 814 to insulation layer 816 having a function as a gate insulator on the bottom gate electrode side
Is a laminate of silicon oxide, aluminum oxide, and silicon oxide. The insulating layer 817 that functions as a gate insulator on the gate (top gate) side is silicon oxide.
The insulating layer 818 having a function as an interlayer insulating layer is silicon oxide. The insulating layer 819 is aluminum oxide.

The conductive materials used for the conductive layer 850 to 853 include metals such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium.
Alternatively, there are metal nitrides (tantallum nitride, titanium nitride, molybdenum nitride, tungsten nitride) containing the above-mentioned metal as a component. For example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. A conductive material such as indium tin oxide can be used.

A configuration example of the conductive layer 850 to the conductive layer 853 will be described. The conductive layer 850 is a tantalum nitride single layer or a tungsten single layer. Alternatively, the conductive layer 850 is a laminate made of tantalum nitride and tungsten. The conductive layer 851 is a single layer of tantalum nitride or a laminate of tantalum nitride and tungsten. The structure of the conductive layer 852 is the same as that of the conductive layer 851. The conductive layer 853 is a laminate made of tantalum nitride and tungsten.

In order to reduce the off-current of the transistor 801 it is preferable that the metal oxide film 822 has a large band gap, for example. The band gap of the metal oxide film 822 is 2.5e.
It is V or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3.0 eV or more and 3.5 eV or less.

The oxide layer 830 preferably has crystalline properties. At least metal oxide film 822
Is preferably crystalline. With the above configuration, a transistor 801 with good electrical characteristics and reliability can be realized.

The oxide applicable to the metal oxide film 822 is, for example, In-Ga oxide, In-Zn oxide, or In-M-Zn oxide (M is Al, Ga, Y, or Sn). Metal oxide film 8
22 is not limited to the oxide film containing In. The metal oxide film 822 is, for example, Zn—S.
It can be formed of n oxide, Ga—Sn oxide, Zn—Mg oxide and the like. The metal oxide film 821, the metal oxide film 823, and the metal oxide film 824 can also be formed of the same oxide as the metal oxide film 822. In particular, the metal oxide film 821, the metal oxide film 823, and the metal oxide film 824 can each be formed of Ga oxide.

The transistor 801 can form a channel region not only in the metal oxide film 822 but also in the vicinity of the interface between the metal oxide film 822 and the metal oxide film 821. Therefore, for example, when an interface state is formed at the interface, the threshold voltage of the transistor 801 may fluctuate. Therefore, the metal oxide film 821 preferably contains at least one of the metal elements constituting the metal oxide film 822 as a component. As a result, an interface state is less likely to be formed at the interface between the metal oxide film 822 and the metal oxide film 821, and it is possible to reduce variations in electrical characteristics such as the threshold voltage in the transistor 801.

The metal oxide film 824 preferably contains at least one of the metal elements constituting the metal oxide film 822 as a component. As a result, the metal oxide film 822 and the metal oxide film 8
At the interface with 24, interfacial scattering of carriers is less likely to occur, and the movement of carriers is less likely to be hindered, so that the field effect mobility of the transistor 801 can be increased.

Of the metal oxide film 821 to the metal oxide film 824, the metal oxide film 822 preferably has the highest carrier mobility. As a result, a channel region is formed in the metal oxide film 822 separated from the insulating layer 816 (gate insulator on the bottom gate electrode side of the transistor 801) and the insulating layer 817 (gate insulator on the gate electrode side of the transistor 801). can do.

For example, an In-containing metal oxide such as an In-M-Zn oxide can increase the carrier mobility by increasing the In content. In the In-M-Zn oxide, the s orbitals of heavy metals mainly contribute to carrier conduction, and by increasing the In content, more s orbitals overlap, so the oxide with a high indium content. Has a higher carrier mobility than an oxide having a low In content. Therefore, the carrier mobility can be increased by using an oxide having a high In content in the metal oxide film.

Therefore, for example, the metal oxide film 822 is formed of In-Ga-Zn oxide, and the metal oxide film 821, the metal oxide film 823, and the metal oxide film 824 are formed of Ga oxide. For example, when the metal oxide film 821 to the metal oxide film 824 is formed from In-M-Zn oxide, the In content of the metal oxide film 822 is adjusted to the metal oxide film 821 and the metal oxide film 823. , The content of each In of the metal oxide film 824 is set to be higher than the content of each In. When the In—M—Zn oxide is formed by the sputtering method, the In content can be changed by changing the atomic number ratio of the target.

For example, the atomic number ratio In: M: Zn of the target used for forming the metal oxide film 822 is
It is preferably 1: 1: 1, 3: 1: 2, or 4: 2: 4.1. For example, metal oxide film 821
, Atomic number ratio of target used for film formation of metal oxide film 823 and metal oxide film 824 In:
M: Zn is preferably 1: 3: 2 or 1: 3: 4. In: M: Zn = 4: 2: 4.1
The atomic number ratio of the In—M—Zn oxide formed with the target of is approximately In: M: Zn = 4.
: 2: 3.

In order to impart stable electrical characteristics to the transistor 801 it is preferable to reduce the impurity concentration of the oxide layer 830. In metal oxides, metal elements other than hydrogen, nitrogen, carbon, silicon, and the main component are impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase carrier density. Silicon and carbon also contribute to the formation of impurity levels in metal oxides. Impurity levels can become traps and degrade the electrical properties of the transistor.

For example, the oxide layer 830 has a region having a silicon concentration of 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less. The same applies to the carbon concentration of the oxide layer 830.

For example, the oxide layer 830 has a region having an alkali metal concentration of 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less. The same applies to the alkaline earth metal concentration of the oxide layer 830.

For example, the oxide layer 830 has a nitrogen concentration of less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / c.
It has a region of m ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

For example, the oxide layer 830 has a hydrogen concentration of less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / c.
It has a region of less than m ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

The impurity concentration of the oxide layer 830 described above is a value obtained by SIMS.

When the metal oxide film 822 has an oxygen deficiency, hydrogen may enter the oxygen deficient site to form a donor level. As a result, it may cause a decrease in the on-current of the transistor 801. It should be noted that oxygen-deficient sites are more stable when oxygen is introduced than when hydrogen is added. Therefore, it may be possible to increase the on-current of the transistor 801 by supplying oxygen into the metal oxide film 822 to reduce oxygen deficiency in the film. Further, reducing hydrogen in the metal oxide film 822 to prevent hydrogen from entering the oxygen-deficient sites in the film is also effective in improving the on-characteristics of the transistor 801.

Hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to become water, so
Oxygen deficiency may form in metal oxides. And when hydrogen enters the oxygen deficiency,
Electrons that are carriers may be generated. In addition, a part of hydrogen may combine with oxygen bonded to a metal atom to generate an electron as a carrier. In the transistor 801 according to one aspect of the present invention, since the channel region is mainly formed in the metal oxide film 822, if the metal oxide film 822 contains hydrogen, the transistor 801 tends to have a normally-on characteristic. Therefore, it is preferable that hydrogen in the metal oxide film 822 is reduced as much as possible.

FIG. 13 shows an example in which the oxide layer 830 has a four-layer structure, but one aspect of the present invention is not limited to this. For example, the oxide layer 830 may have a three-layer structure without the metal oxide film 821 or the metal oxide film 823. Alternatively, between arbitrary films of the oxide layer 830 (metal oxide film 821 to metal oxide film 824), the metal oxide is placed at any two or more locations above the oxide layer 830 and below the oxide layer 830. One or more layers of the same metal oxide film as the film 821 to the metal oxide film 824 can be provided.

With reference to FIG. 14, the effect obtained by laminating the metal oxide film 821, the metal oxide film 822, and the metal oxide film 824 will be described. FIG. 14 is a schematic diagram of an energy band structure in the channel formation region of the transistor 801.

In FIG. 14, Ec816e, Ec821e, Ec822e, Ec824e, Ec8
Reference numeral 17e indicates the energy of the lower end of the conduction band of the insulating layer 816, the metal oxide film 821, the metal oxide film 822, the metal oxide film 824, and the insulating layer 817, respectively.

Here, the difference between the vacuum level and the energy at the lower end of the conduction band (also referred to as electron affinity) is obtained by subtracting the band gap from the difference between the vacuum level and the energy at the upper end of the valence band (also referred to as ionization potential). It becomes a value. The band gap is a spectroscopic ellipsometer (HORIB).
It can be measured using A JOBIN YVON UT-300). In addition, the energy difference between the vacuum level and the upper end of the valence band is determined by ultraviolet photoelectron spectroscopy (UPS: Ultraviolet).
Photoemission Spectroscopy) equipment (PHI Vers)
It can be measured using aProbe).

Since the insulating layer 816 and the insulating layer 817 are insulators, Ec816e and Ec817e are E.
It is closer to the vacuum level than c821e, Ec822e, and Ec824e (electron affinity is small).

The metal oxide film 822 has a higher electron affinity than the metal oxide film 821 and the metal oxide film 824. For example, the difference in electron affinity between the metal oxide film 822 and the metal oxide film 821 and the difference in electron affinity between the metal oxide film 822 and the metal oxide film 824 are 0.07 eV, respectively.
It is 1.3 eV or less. The difference in electron affinity is preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less.

When a voltage is applied to the gate electrode (conductive layer 850) of the transistor 801, the channel is mainly connected to the metal oxide film 822 having the highest electron affinity among the metal oxide film 821, the metal oxide film 822, and the metal oxide film 824. A region is formed.

In-Ga oxide has a small electron affinity and high oxygen blocking property. for that reason,
It is preferable that the metal oxide film 824 contains an In-Ga oxide. Ga atom ratio [Ga / (In
+ Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

Further, a mixed region of the metal oxide film 821 and the metal oxide film 822 may exist between the metal oxide film 821 and the metal oxide film 822. Further, a mixed region of the metal oxide film 824 and the metal oxide film 822 may exist between the metal oxide film 824 and the metal oxide film 822. The interface state density in the mixed region is the metal oxide film 821 and the insulating layer 816.
It is lower than the interface state density between the metal oxide film 824 and the insulating layer 817. Therefore, the region where the metal oxide film 821, the metal oxide film 822, and the metal oxide film 824 are laminated has a band structure in which the energy continuously changes (also referred to as continuous bonding) in the vicinity of the respective interfaces. ..

In the oxide layer 830 having such an energy band structure, electrons as carriers mainly move through the metal oxide film 822. Therefore, even if there are levels at the interface between the metal oxide film 821 and the insulating layer 816 or the interface between the metal oxide film 824 and the insulating layer 817, these interface levels cause the oxide layer 830 to contain levels. Since the movement of electrons moving in the transistor 801 is less likely to be hindered, the on-current of the transistor 801 can be increased.

Further, as shown in FIG. 14, the trap level Et826e caused by impurities and defects is located near the interface between the metal oxide film 821 and the insulating layer 816 and near the interface between the metal oxide film 824 and the insulating layer 817, respectively. Although the trap level Et827e can be formed, the metal oxide film 821 and the metal oxide film 824 cause the metal oxide film 822 to be trapped at the trap level Et827.
It can be separated from the trap level Et827e at 826e. Therefore, the electrons moving on the metal oxide film 822 are less likely to be captured by the trap level Et826e and the trap level Et827e, and the electron capture is prevented from adversely affecting the electrical characteristics and reliability of the transistor 801 (described later). be able to.

When the difference between Ec821e and Ec822e is small, the electrons in the metal oxide film 822 may exceed the energy difference and reach the trap level Et826e. Trap level E
When an electron is captured by t826e, a negative fixed charge is generated at the interface of the insulating layer 816, and the threshold voltage of the transistor 801 is shifted in the positive direction. Ec822e and Ec8
The same applies when the energy difference from 24e is small.

In order to reduce the fluctuation of the threshold voltage of the transistor 801 and improve the electrical characteristics of the transistor 801, the difference between Ec821e and Ec822e, Ec824e and Ec822e
The difference between the above and the above is preferably 0.1 eV or more, and more preferably 0.15 eV or more.

The transistor 801 may have a structure that does not have a bottom gate electrode (conductive layer 853).

<CAC-OS>
Next, CAC-OS will be described. The CAC-OS may be included in the channel forming region of the OS transistor.

CAC-OS is, for example, a composition of a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size close thereto. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element is 0.5 nm or more and 10 nm or less, preferably 1 nm or more 2
The state of being mixed in a size of nm or less or in the vicinity thereof is also referred to as a mosaic shape or a patch shape.

The metal oxide preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from the above may be included.

For example, CAC-OS in In-Ga-Zn oxide (In-OS among CAC-OS)
Ga-Zn oxide may be particularly referred to as CAC-IGZO. ) Means indium oxide (hereinafter, InO _X1 (X1 is a real number larger than 0)) or indium zinc oxide (hereinafter, In _X2 Zn _Y2 O _Z2 (hereinafter, X2, Y2, and Z2 are from 0)). (A large real number)) and a gallium oxide (hereinafter, GaO _X3 (X3 is a real number larger than 0)).
) Or gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers larger than 0)) and the like, resulting in a mosaic shape. In O _X1 or In _X2 Zn _Y2 O _Z2 is uniformly distributed in the film (hereinafter, also referred to as cloud-like).

That is, the CAC-OS has a region in which GaO _X3 is the main component and In _X2 Zn _Y2 O _Z2.
, Or the region in which InO _X1 is the main component is a composite metal oxide having a structure in which it is mixed. In the present specification, for example, the atomic number ratio of In to the element M in the first region is larger than the atomic number ratio of In to the element M in the second region. 2
It is assumed that the concentration of In is higher than that of the region of.

In addition, IGZO is a common name, and may refer to one compound consisting of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In ₍₁ ).
_{+ X0)} Ga _(1-x0) O ₃ (ZnO) A crystalline compound represented by _m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number) can be mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. In addition, it should be noted
The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without being oriented on the ab plane.

On the other hand, CAC-OS relates to the material composition of metal oxides. CAC-OS is In, G
In the material composition containing a, Zn, and O, a region partially observed as nanoparticles containing Ga as a main component and a region partially observed as nanoparticles containing In as a main component are observed. , Each of which is randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

It should be noted that CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component, is not included.

It may be difficult to observe a clear boundary between the region containing GaO _X3 as the main component and the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as the main component.

Instead of gallium, select from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. When one or more of these are contained, CAC-OS has a region observed in the form of nanoparticles containing the metal element as a main component and a nano having In as a main component. The regions observed in the form of particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.

The CAC-OS can be formed, for example, by a sputtering method under the condition that the substrate is not intentionally heated. When CAC-OS is formed by a sputtering method, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as the film forming gas. Good. Further, the lower the flow rate ratio of the oxygen gas to the total flow rate of the film-forming gas at the time of film formation is preferable. For example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less. ..

CAC-OS is characterized in that no clear peak is observed when measured using a θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Has. That is, from the X-ray diffraction, it can be seen that the orientation of the measurement region in the ab plane direction and the c-axis direction is not observed.

In addition, CAC-OS is an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam).
In the electron diffraction pattern obtained by irradiating with, a ring-shaped region with high brightness and
A plurality of bright spots are observed in the ring region. Therefore, from the electron diffraction pattern, CAC
-The crystal structure of OS has no orientation in the plane direction and the cross-sectional direction, nc (nan).
It can be seen that it has an o-crystal) structure.

In addition, for example, in CAC-OS in In-Ga-Zn oxide, energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectrum)
By EDX mapping acquired using oscopy), the region containing GaO _X3 as the main component and the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as the main component are unevenly distributed and have a mixed structure. Can be confirmed.

CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and I
It has different properties from the GZO compound. That is, the CAC-OS is phase-separated into a region containing GaO _X3 or the like as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component, and a region containing each element as a main component. Has a mosaic-like structure.

Here, the region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component is GaO _X3.
This is a region with high conductivity as compared with the region where the main component is. That is, In _X2 Zn _Y
When a carrier flows through a region containing ₂ O _Z2 or InO _X1 as a main component, conductivity as a metal oxide is exhibited. Therefore, In _X2 Zn _Y2 O _Z2 or In O _X1
Since the region containing the main component is distributed in the metal oxide in a cloud shape, the semiconductor device using the metal oxide can realize high field effect mobility.

On the other hand, the region in which GaO _X3 or the like is the main component is In _X2 Zn _Y2 O _Z2 or InO _X.
This is a region having high insulating properties as compared with the region in which ₁ is the main component. That is, since the region containing GaO _X3 or the like as the main component is distributed in the metal oxide, the semiconductor element using the metal oxide can suppress the leakage current and realize a good switching operation.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _X3 or the like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act in a complementary manner. The semiconductor device can realize a good switching operation having both high on-current and field-effect mobility and low leakage current.

Moreover, the semiconductor element using CAC-OS has good reliability. Therefore, CA
C-OS is most suitable for application to various semiconductor devices.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 6)
In the present embodiment, an example in which the semiconductor device or the like described in the above embodiment is applied to an electronic component and an example of an electronic device capable of including the electronic component will be described with reference to FIGS. 15 to 18.

<Wafer chip>
FIG. 15A shows a top view of the substrate 1001 before the dicing process is performed. As the substrate 1001, for example, a semiconductor substrate (also referred to as a semiconductor wafer) can be used. A plurality of circuit regions 1002 are provided on the substrate 1001. Circuit area 1
002 may be provided with the semiconductor device or the like shown in the above embodiment.

Each of the plurality of circuit regions 1002 is surrounded by a separation region 1003. Separation area 1
A separation line (also referred to as a dicing line) 1004 is set at a position overlapping with 003. The chip 1 including the circuit area 1002 by cutting the substrate 1001 along the separation line 1004.
005 can be cut out from the substrate 1001. FIG. 15B shows an enlarged view of the chip 1005.

Further, a conductive layer or a semiconductor layer may be provided in the separation region 1003. By providing a conductive layer or a semiconductor layer in the separation region 1003, ESD (Electro-S) that may occur during the dicing process
It is possible to alleviate the titic discharge (electrostatic discharge) and prevent a decrease in yield due to the dicing process. Further, in general, the dicing step is performed while flowing pure water in which carbon dioxide gas or the like is dissolved to reduce the specific resistance for the purpose of cooling the substrate, removing shavings, preventing antistatic, and the like. By providing a conductive layer or a semiconductor layer in the separation region 1003, the amount of pure water used can be reduced. Therefore, the production cost of the semiconductor device can be reduced. Moreover, the productivity of the semiconductor device can be increased.

The semiconductor layer provided in the separation region 1003 has a bandgap of 2.5 eV or more and 4.2.
It is preferable to use a material of eV or less, preferably 2.7 eV or more and 3.5 eV or less. By using such a material, the electric charge accumulated on the substrate 1001 can be slowly discharged, so that the rapid movement of the electric charge due to ESD is suppressed, and electrostatic destruction of each element in the chip 1005 occurs. It can be made difficult.

<Electronic components>
An example of applying the chip 1005 to an electronic component will be described with reference to FIG. The electronic component is also referred to as a semiconductor package or an IC package. There are a plurality of standards and names for electronic components depending on the terminal take-out direction and the shape of the terminal.

In the assembly process (post-process), the electronic component is completed by combining the semiconductor device shown in the above embodiment and a component other than the semiconductor device.

The post-process will be described with reference to the flowchart shown in FIG. 16 (A). In the previous step, after the element substrate having the semiconductor device shown in the above embodiment is completed, a "backside grinding step" is performed to grind the back surface (the surface on which the semiconductor device or the like is not formed) of the element substrate (step). S1). By thinning the element substrate by grinding, it is possible to reduce the warp of the element substrate and reduce the size of the electronic component.

Next, a "dicing step" for separating the element substrate into a plurality of chips is performed (step S2).
.. Then, each of the separated chips is picked up and a "die bonding step" of joining them onto the lead frame is performed (step S3). For the bonding between the chip and the lead frame in the die bonding process, a method suitable for the product is appropriately selected, such as bonding with resin or bonding with tape. The chip may be bonded on the interposer substrate instead of the lead frame.

Next, a "wire bonding step" is performed in which the leads of the lead frame and the electrodes on the chip are electrically connected by a thin metal wire (wire) (step S4). A silver wire or a gold wire can be used as the thin metal wire. Further, as the wire bonding, ball bonding or wedge bonding can be used.

The wire-bonded chips are subjected to a "sealing step (molding step)" in which they are sealed with an epoxy resin or the like (step S5). By performing the sealing process, the inside of the electronic component is filled with resin, the circuit part built in the chip and the wire connecting the chip and the lead can be protected from mechanical external force, and the characteristics due to moisture and dust. Deterioration (decrease in reliability) can be reduced.

Next, a "lead plating step" for plating the leads of the lead frame is performed (step S6). The plating process prevents reeds from rusting, and soldering can be performed more reliably when the reeds are later provided on the printed circuit board. Next, a "molding process" for cutting and molding the lead is performed (step S7).

Next, a "marking step" of printing (marking) the surface of the package is performed (step S8). Then, the "inspection process" to check the quality of the appearance and the presence or absence of malfunctions
Through (step S9), the electronic component is completed.

Further, a schematic perspective view of the completed electronic component is shown in FIG. 16 (B). FIG. 16B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. The electronic component 1101 shown in FIG. 16B shows a semiconductor device with a lead. As the semiconductor device, the semiconductor device shown in the above embodiment can be used.

The electronic component 1101 shown in FIG. 16B is provided on, for example, the printed circuit board 1102. A plurality of such electronic components 1101 are combined, and each of them is a printed circuit board 1102.
By being electrically connected above, the substrate 1103 provided with electronic components is completed. The completed substrate 1103 is used for electronic devices and the like.

<Electronic equipment>
The above board 1103 is used for digital signal processing, software defined radio, avionics (electronic equipment related to aviation such as communication equipment, navigation systems, autopilots, flight management systems, etc.), AS.
Applicable to electronic components (IC chips) in a wide range of fields such as IC prototyping, medical image processing, voice recognition, encryption, bioinformatics (bioinformatics), mechanical device emulators, and radio telescopes in radio astronomy. It is possible to do. Examples of such electronic devices include cameras (video cameras, digital still cameras, etc.), display devices, personal computers (PCs), mobile phones, game machines including portable types, portable information terminals (smartphones, tablet type information terminals, etc.). ), Electronic book terminals, wearable information terminals (clock type, head mount type, goggles type, eyeglass type, arm badge type, bracelet type, necklace type, etc.), navigation system, sound reproduction device (car audio, digital audio player, etc.) , Copiers, facsimiles, printers, printer compound machines, automatic cash deposit / payment machines (ATMs), vending machines, household appliances, etc.

Below, a configuration example of an electronic device is shown with reference to FIGS. 17 and 18. It is preferable to use a touch panel device having a touch sensor for the display unit of the electronic device. By using the touch panel device, the display unit can also function as an input unit of an electronic device.

17 (A) and 17 (B) show an example of the mobile information terminal 2000. Mobile information terminal 2
000 includes a housing 2001, a housing 2002, a display unit 2003, a display unit 2004, a hinge unit 2005, and the like.

The housing 2001 and the housing 2002 are connected by a hinge portion 2005. Mobile information terminal 2
000 can open the housing 2001 and the housing 2002 as shown in FIG. 17 (B) from the folded state as shown in FIG. 17 (A).

For example, document information can be displayed on the display unit 2003 and the display unit 2004.
The mobile information terminal 2000 can also be used as an electronic book terminal. In addition, the display unit 200
A still image or a moving image can be displayed on the display unit 2004 and the display unit 2004. In addition, the display unit 200
3 may have a touch panel.

In this way, the mobile information terminal 2000 can be folded when it is carried.
Excellent versatility.

The housing 2001 and the housing 2002 include a power button, an operation button, and an external connection port.
It may have a speaker, a microphone, and the like.

The mobile information terminal 2000 uses a touch sensor provided on the display unit 2003 to be used.
It may have a function of identifying characters, figures, and images. In this case, for example, for an information terminal that displays a collection of questions for learning mathematics or language, the answer is written with a finger or a stylus pen, and the mobile information terminal 2000 is used to determine the correctness. It can be carried out. Further, the mobile information terminal 2000 may have a function of decoding voice. In this case, for example, the mobile information terminal 2000 can be used to learn a foreign language. Such a personal digital assistant is suitable for use as a teaching material such as a textbook or a notebook.

FIG. 17C shows an example of a mobile information terminal. Mobile information terminal 2010 shown in FIG. 17 (C)
Has a housing 2011, a display unit 2012, an operation button 2013, an external connection port 2014, a speaker 2015, a microphone 2016, a camera 2017, and the like.

The mobile information terminal 2010 includes a touch sensor on the display unit 2012. All operations such as making a phone call or inputting characters can be performed by touching the display unit 2012 with a finger or a stylus.

Further, by operating the operation button 2013, it is possible to switch the power on / off operation and the type of the image displayed on the display unit 2012. For example, the mail composition screen can be switched to the main menu screen.

Further, by providing a detection device such as a gyro sensor or an acceleration sensor inside the mobile information terminal 2010, the orientation (vertical or horizontal) of the mobile information terminal 2010 can be determined and the display unit 2012 can be determined.
The orientation of the screen display can be automatically switched. To switch the screen display orientation, touch the display unit 2012, operate the operation buttons 2013, or use the microphone 2.
It can also be performed by voice input using 016 or the like.

The mobile information terminal 2010 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, and the like. For example, the mobile information terminal 2010 can be used as a smartphone. In addition, the mobile information terminal 2010 can execute various applications such as mobile phone, e-mail, text viewing and creation, music playback, video playback, Internet communication, and games.

FIG. 17 (D) shows an example of a camera. The camera 2020 includes a housing 2021 and a display unit 20.
It has 22, an operation button 2023, a shutter button 2024, and the like. Also camera 2020
A removable lens 2026 is attached to the lens.

Here, the camera 2020 has a configuration in which the lens 2026 can be removed from the housing 2021 and replaced, but the lens 2026 and the housing 2021 may be integrated.

The camera 2020 can capture a still image or a moving image by pressing the shutter button 2020. Further, the display unit 2022 has a function as a touch panel, and it is possible to take an image by touching the display unit 2022.

The camera 2020 can be separately equipped with a strobe device, a viewfinder, and the like. Alternatively, these may be incorporated in the housing 2021.

The notebook PC (personal computer) 2050 shown in FIG. 18A has a housing 205.
1. It has a display unit 2052, a keyboard 2053, and a pointing device 2054.
The notebook PC 2050 can also be operated by touching the display unit 2052.

The portable game machine 2110 shown in FIG. 18B includes a housing 2111, a display unit 2112, a speaker 2113, an LED lamp 2114, an operation key button 2115, a connection terminal 2116, a camera 2117, a microphone 2118, and a recording medium reading unit 2119. Have.

The automobile 2170 shown in FIG. 18C has a vehicle body 2171, wheels 2172, dashboard 2173, lights 2174, and the like. The automobile 2170 may have a display unit.

The various electronic devices described above may be provided with a storage device, a computer, or the like according to one aspect of the present invention. As a result, a highly reliable electronic device can be realized. Further, a highly reliable display system is provided by providing the above-mentioned electronic device with a control circuit equipped with a storage device according to one aspect of the present invention and providing a display unit according to one aspect of the present invention in the display unit of the electronic device. Can be realized.

This embodiment can be appropriately combined with the description of other embodiments.

10 Memory cell array 100 Storage device 110 Cell array 120 Drive circuit section 130 Drive circuit 131 Decoder 132 Line driver 133 Sense amplifier 140 Drive circuit 141 Decoder 142 Column driver 143 Sense amplifier 144 Precharge circuit 160 Control circuit 170 Output circuit 300 Computer 310 Input device 320 Output device 330 Central calculation processing device 331 Control circuit 332 Calculation circuit 333 Storage device 334 Storage device 340 Main storage device 400 Display system 410 Display unit 411 Display unit 411a Display unit 411b Display unit 412 Touch sensor unit 420 Control circuit 421 Interface 422 Frame memory 423 Decoder 424 Sensor controller 425 Controller 426 Clock generation circuit 430 Image processing unit 431 Gamma correction circuit 432 Dimming circuit 433 Color matching circuit 434 EL correction circuit 441 Storage device 442 Timing controller 443 Register 450 Drive circuit 451 Source driver 451a Source driver 451b Source Driver 461 Touch sensor Controller 470 Host 480 Optical sensor 481 External light 500 Display 501 Pixel unit 502 Pixel unit 503 Drive circuit 503a Drive circuit 503b Drive circuit 504 Drive circuit 504a Drive circuit 504b Drive circuit 505a Pixel 505b Pixel 506b Sub-pixel 506b Sub-pixel 506b Sub-pixel 506br Sub-pixel 506b Sub-pixel 510 Liquid crystal element 520 Light-emitting element 520b Light-emitting element 520g Light-emitting element 520r Light-emitting element 520w Light-emitting element 530 Conductive layer 530a Conductive layer 530b Conductive layer 540 Opening 551 Board 561 Board 562 Display area 565 FPC
573 IC
612 Liquid crystal 613 Conductive layer 617 Insulation layer 621 Insulation layer 630 Plate plate 631 Colored layer 632 Light-shielding layer 633a Alignment film 633b Alignment film 634 Colored layer 641 Adhesive layer 642 Adhesive layer 691 Conductive layer 692 EL layer 693a Conductive layer 693b Conductive layer 701 Transistor 704 Connection 705 Transistor 706 Transistor 707 Connection 711 Insulation layer 712 Insulation layer 713 Insulation layer 714 Insulation layer 715 Insulation layer 716 Insulation layer 717 Insulation layer 720 Insulation layer 721 Conduction layer 722 Conduction layer 723 Conduction layer 724 Conduction layer 731 Semiconductor layer 742 Connection Layer 743 Connection 752 Connection 801 Transistor 81 Insulation layer 812 Insulation layer 813 Insulation layer 814 Insulation layer 815 Insulation layer 816 Insulation layer 817 Insulation layer 818 Insulation layer 819 Insulation layer 820 Insulation layer 821 Metal oxide film 822 Metal oxide film 823 Metal oxide film 824 Metal oxide film 830 Oxide layer 850 Conductive layer 850a Conductive layer 850b Conductive layer 851 Conductive layer 852 Conductive layer 853 Conductive layer 853a Conductive layer 853b Conductive layer 1001 Substrate 1002 Circuit area 1003 Separation area 1004 Separation line 1005 Chip 1101 Electronic parts 1102 Print board 1103 Board 2000 Mobile information terminal 2001 Housing 2002 Housing 2003 Display 2004 Display 2005 Hinging 2010 Mobile information terminal 2011 Housing 2012 Display 2013 Operation button 2014 External connection port 2015 Speaker 2016 Microphone 2017 Camera 2020 Camera 2021 Housing 2022 Display 2023 Operation Button 2024 Shutter Button 2026 Lens 2050 Notebook PC
2051 Housing 2052 Display 2053 Keyboard 2054 Pointing device 2110 Portable game machine 2111 Housing 2112 Display 2113 Speaker 2114 LED lamp 2115 Operation key button 2116 Connection terminal 2117 Camera 2118 Microphone 2119 Recording medium reading 2170 Automobile 2171 Body 2172 Wheel 2173 Dashboard 2174 lights

Claims (1)

It has a first transistor and a second transistor, and a first capacitive element and a second capacitive element.
One of the source or drain of the first transistor, one electrode of the first capacitive element, and the gate of the second transistor are electrically connected.
A semiconductor device characterized in that one of the source or drain of the second transistor, one electrode of the second capacitive element, and the gate of the first transistor are electrically connected.