JP6299554B2 - Power-on reset circuit - Google Patents

Description

  The present invention relates to a power-on reset circuit.

  The power-on reset circuit keeps the circuit operation in the reset state and resets after the operating power is secured in order to avoid the unstable operation of the circuit when the power supply voltage cannot be secured immediately after the power is turned on. The state is released. In recent years, in a circuit to be subjected to power-on reset, as the miniaturization progresses, the threshold voltage of a transistor incorporated in the circuit is lowered, and a sufficient reset pulse width may not be ensured.

  Recently, for example, an IC having a two power supply configuration such as an IC interface of 5V and a control circuit of 1.8V is becoming mainstream. As a power-on reset circuit for a two-power supply, for example, a 5V power-on reset circuit has been conventionally used. The same type of circuit is also applied to the 1.8V system, and the logic is finally obtained through a level shift from 1.8V to 5V to obtain a reset signal. However, this has the problem that there are two reset detection units and the circuit scale becomes large.

JP 2004-350126 A

  The present invention has been made in consideration of the above circumstances, and its purpose is to ensure a sufficient reset pulse width for a circuit driven by a plurality of power supplies even when the threshold voltage of a low-voltage transistor is low. Another object of the present invention is to provide a power-on reset circuit capable of reliably releasing a reset in a state where a plurality of power supplies are activated.

  The power-on reset circuit according to claim 1 is intended for a circuit that operates by receiving supply of a high voltage and a low voltage, and is supplied with a high voltage and the gate voltage is a first threshold value. A P-channel type first switching element that is turned on when the voltage exceeds a voltage, a resistive element that is supplied with a high power supply voltage and applies a gate voltage to the first switching element, and a high voltage via the resistive element Is supplied to the high-voltage side terminal, and when the gate voltage of the gate connected to the high-voltage side terminal becomes equal to or higher than the second threshold voltage, the N-channel type second switching element that is turned on, and the high-voltage power supply voltage are An N-channel type which is applied via a resistive element and the second switching element and which is turned on when a gate voltage applied from a low-voltage power supply is equal to or higher than a third threshold voltage A third switching element and a low-voltage power supply voltage are supplied, a reset signal for resetting the low-voltage circuit is output when the first switching element is in an off state, and when the first switching element is turned on, a low-voltage reset signal is output. And a low voltage output circuit.

  By adopting the above configuration, when the low voltage and the high power supply voltage are supplied, the third switching element is supplied with the gate voltage from the low voltage power supply and is turned on when the voltage exceeds the third threshold voltage. The second switching element is turned on when a high voltage rises and exceeds the second threshold voltage in a state where a low voltage is applied, and a current flows through the resistive element. As a result, when the terminal voltage of the resistive element becomes equal to or higher than the first threshold voltage, the first switching element is turned on and a current flows through the resistive element. The low voltage output circuit stops the low voltage reset signal when the first switching element is turned on. As a result, the reset signal can be stopped when both the high voltage and the low voltage rise, so that a sufficient reset pulse width can be secured even when the threshold voltage of the low voltage transistor is low, and a plurality of power supplies Reset can be reliably canceled in the standing state.

Electrical configuration diagram showing the first embodiment Time chart showing the transition of the voltage of each part when the low voltage rises first Time chart showing the transition of the voltage of each part of the case where the high voltage rises first Time chart showing the transition of the voltage of each part when the power supply rises sharply Time chart showing the voltage transition of each part of the case where the power supply starts up slowly Electrical configuration diagram showing the second embodiment Electrical configuration diagram showing the third embodiment Electrical configuration diagram showing the fourth embodiment Electrical configuration diagram showing the fifth embodiment Electrical configuration diagram showing the sixth embodiment Electrical configuration diagram showing the seventh embodiment Electrical configuration diagram showing the eighth embodiment

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. In this embodiment, a description will be given using an IC that operates by supplying power from the high voltage VDH and the low voltage VDL as a power supply having a high voltage VDH of 5 V and a low voltage VDL of 1.8 V as an operation power supply. Note that the high voltage and low voltage referred to here represent relatively the magnitude relationship of the voltages, and do not indicate the so-called high voltage or low voltage range or voltage level. It means that it exists.

  FIG. 1 shows a power-on reset circuit 1 that can generate both power-on reset signals in a circuit that uses the power sources of the high voltage VDH and the low voltage VDL described above. A high-voltage power supply terminal VDH of 5 V is connected to a ground terminal via a resistor 2 as a resistive element and N-channel MOSFETs 3 and 4 in series. The N-channel MOSFET 3 functions as a second switching element, and the drain and gate are short-circuited. The N-channel type MOSFET 4 functions as a third switching element, and a 1.8 V power supply terminal VD2, which is a low voltage, is connected to the gate.

  The power supply terminal VDH is connected to a ground terminal via a P-channel type MOSFET 5 and a capacitor 6 in series. MOSFET 5 and capacitor 6 constitute a time constant circuit. Further, the power supply terminal VDH is connected to the ground terminal via a P-channel type MOSFET 7 and a resistor 8 which is a resistive element in series. The gates of the MOSFETs 5 and 7 are connected to a common connection point between the resistor 2 and the MOSFET 3. The MOSFET 7 functions as a first switching element. The MOSFET 5 functions as a fourth switching element.

  The drain terminals of the MOSFETs 5 and 7 are connected to the two input terminals of the AND circuit 9. An output terminal of the AND circuit 9 is connected to an output terminal that outputs a high-voltage power-on reset signal PORH through serially connected high-voltage (5V) NAND circuits 10 and 11. The inverter circuit 11 functions as a high voltage output circuit. Note that both the AND circuit 9 and the inverter circuits 10 and 11 are supplied with power from the high voltage VDH.

  The level shift circuit 12 is provided in an output stage that outputs a power-on reset signal PORL for low voltage. The level shift circuit 12 includes two N-channel MOSFETs 12a and 12b, two P-channel MOSFETs 12c and 12d, and a low-voltage (1.8V) inverter circuit 12e. The level shift circuit 12 functions as a low voltage output circuit.

  The drain of the MOSFET 12a is connected to the low voltage VDL via the drain-source of the MOSFET 12c, and is also connected to the gate of the MOSFET 12d. The gate of the MOSFET 12a is connected to the input terminal of the inverter circuit 11, and the source is connected to the ground.

  The drain of the MOSFET 12b is connected to the low voltage VDL via the drain-source of the MOSFET 12d, and is connected to the gate of the MOSFET 12c and the input terminal of the inverter circuit 12e. The gate of the MOSFET 12b is connected to the input terminal of the inverter circuit 10, and the source is connected to the ground. The inverter circuit 12e is supplied with power from the low voltage VDL, and its output terminal is connected to an output terminal that outputs a power-on reset signal PORL for low voltage.

  Next, the operation of the above configuration will be described with reference to FIGS. In the following description, (a) the case where the low voltage VDL rises first according to which of the two power supply voltages, the high voltage VDH and the low voltage VDL rises first, and (b) the high voltage VDH first. It will be explained in the case of standing up. In addition, in the case where the low voltage VDL rises first in (a), in addition to the general operation, (1) the case where the high voltage VDH rises sharply and (2) the case where the high voltage VDH rises slowly will be described.

  For the sake of explanation, the connection points (nodes) of each part are determined as follows. The common connection point of MOSFET 5 and capacitor 6 is node A, the common connection point of MOSFET 7 and resistor 8 is node B, the common connection point of AND circuit 9 and inverter circuit 10 is node C, and the common connection point of inverter circuits 10 and 11 is the node. D.

(A) Case where the low voltage VDL rises first The operation in this case will be described with reference to FIG. In the initial state, the output terminals that output the high-voltage power-on reset signal PORH and the low-voltage power-on reset signal PORL both output a low-level reset signal. Holds the reset state.

  When the low voltage VDL is applied in this state, the MOSFET 4 is turned on by applying the gate voltage (third threshold voltage). This state is the state at the start time in FIG. Next, when the high voltage VDH is applied in this state, the applied voltage levels are the threshold voltage Vt (3) (second threshold voltage) of the MOSFET 3 and the threshold voltage Vt (5) (first threshold voltage) of the MOSFET 5. ) And the voltage Va (= Vt (3) + Vt (5)), the current flows through the resistor 2. As a result, the voltage between the terminals of the resistor 2 rises, and when the threshold voltage of the MOSFET 5 is exceeded, the charging operation to the capacitor 6 is started and the potential V (A) of the node A rises.

  Thereafter, when the level of the applied high voltage VDH further increases, the potential between the gate and the source of the MOSFET 7 increases, so that the on-resistance Ron (7) of the MOSFET 7 decreases. The potential V (B) of the node B is a potential determined by the resistor 8 and the on-resistance Ron (7) of the MOSFET 7. When both the potential V (A) of the node A and the potential V (B) of the node B exceed the threshold voltage Vt (9) of the AND circuit 9, the output of the AND circuit 9 is inverted to a high level. As a result, the high voltage power-on reset signal PORH is inverted from the low level to the high level, and the power-on reset state of the high voltage circuit system is released.

  The low voltage power-on reset signal PORL is a low-level signal that indicates the reset state in the initial state. In this state, the high voltage power-on reset signal PORH outputs a low level. At this time, the node C is at a low level and the node D is at a high level. As a result, in the level shift circuit 12, the MOSFET 12a is on and the MOSFET 12b is off, and the low-voltage power-on reset signal PORL is at a low level.

  When the high-voltage power-on reset signal PORH changes to high level, the node C changes to high level and the node D changes to low level, so that the MOSFET 12a is turned off and the MOSFET 12b is turned on. As a result, the low voltage power-on reset signal PORL also shifts to a high level. Thus, when both the high voltage VDH and the low voltage VDL reach a predetermined voltage, both the power-on reset signals PORH and PORL can be shifted to a high level to release the reset state.

(B) Case where high voltage VDH rises first The operation of this case will be described with reference to FIG. In this case, the high voltage VDH has already been raised and applied, and the low voltage VDL rises in this state. In a state where the high voltage VDH is applied, the MOSFET 4 is in a state where the high voltage VDH is applied to the drain terminal via the resistor 2 and the MOSFET 3. When the low voltage VDL is applied and the gate voltage of the MOSFET 4 rises and reaches the threshold voltage Vt (4), the MOSFET 4 shifts to the on state and current flows.

  As a result, a voltage drop of the resistor 2 occurs, and the MOSFETs 5 and 7 are turned on. Then, the capacitor 6 starts to be charged through the MOSFET 5, and the voltage V (A) at the node A gradually increases. The voltage V (B) at the node B rises to near the high voltage VDH simultaneously with the turning on of the MOSFET 7.

  Thereafter, when the voltage V (A) of the node A exceeds the threshold voltage Vt (9) of the AND circuit 9 due to the progress of charging of the capacitor 6, the output of the AND circuit 9 is spotted at a high level. As a result, the high voltage VDH power on reset signal PORH is inverted from the low level to the high level, and the power on reset of the high voltage circuit system is released.

  When the high voltage power-on reset signal PORH changes to high level, the MOSFET 12a is turned off and the MOSFET 12b is turned on, and the low voltage power-on reset signal PORL is also shifted to high level. Thus, when both the high voltage VDH and the low voltage VDL reach a predetermined voltage, both the power-on reset signals PORH and PORL can be shifted to a high level to release the power-on reset state.

(1) Case where the high voltage VDH rises sharply with the low voltage VDL rising Next, when the high voltage VDH is applied in the case (a) above, that is, the state where the low voltage VDL has risen first The case where the high voltage VDH rises sharply will be described with reference to FIG.

  In this case, as shown in FIG. 4A, the high voltage VDH changes so as to reach the voltage VDH in a short time. Thereafter, in the same manner as described above, when the level of the high voltage VDH exceeds the sum of the voltage Va of the threshold voltage Vt (3) of the MOSFET 3 and the threshold voltage Vt (5) of the MOSFET 5, the resistance 2 Current will flow. As a result, the voltage between the terminals of the resistor 2 increases, and when the threshold voltage Vt (5) of the MOSFET 5 is exceeded, the charging operation to the capacitor 6 is started and the potential V (A) of the node A increases (FIG. 4). (C)).

  The voltage V (A) at the node A gradually rises due to the charging operation of the capacitor 6, but the voltage V (B) at the node B rises sharply as the high voltage VDH rises as shown in FIG. As shown, since the voltage level almost the same as the high voltage VDH is reached in a short time, the threshold voltage Vt (9) of the AND circuit 9 is reached first. When the terminal voltage of the capacitor 6 rises and the potential V (A) of the node A reaches the threshold voltage Vt (9), the output of the AND circuit 9 is inverted to a high level. As a result, as shown in FIG. 4D, the high voltage power-on reset signal PORH is inverted from the low level to the high level, and the high voltage power-on reset state is released.

(2) Case where the high voltage VDH rises slowly with the low voltage VDL rising Next, a case where the high voltage VDH rises slowly after the low voltage VDL has risen will be described with reference to FIG. . In this case, as shown in FIG. 5A, for example, it is assumed that the increase in the high voltage VDH is slower than the voltage increase at the node A due to the charging of the capacitor 6 described above.

  As shown in FIG. 5A, the high voltage VDH rises with a gentle slope, and the level of the high voltage VDH is the sum of the threshold voltage Vt (3) of the MOSFET 3 and the threshold voltage Vt (5) of the MOSFET 5. When the voltage Va is exceeded, a current flows through the resistor 2. As a result, the voltage between the terminals of the resistor 2 increases, and when the threshold voltage Vt (5) of the MOSFET 5 is exceeded, the charging operation to the capacitor 6 is started and the potential V (A) of the node A increases (FIG. 5). (B)). When the high voltage VDH rises slowly as described above, the logic cell in the circuit is close to an unstable state where the state is not yet determined.

  Then, the voltage V (A) at the node A rises slowly by the charging operation of the capacitor 6 to catch up with the rising high voltage VHD and rises with the voltage of the high voltage VDH because the rise of the high voltage VDH is slow. I will do it. On the other hand, the voltage V (B) at the node B is determined by the on-resistance Ron (7) of the MOSFET 7 and the resistance value of the resistor 8 because the high voltage VDH rises slowly. It rises more slowly (FIG. 5 (c)).

  Then, the threshold voltage Vt (9) of the AND circuit 9 is set to a voltage Vb in which the voltage V (B) at the node B is higher than the sum voltage Va of the threshold voltage Vt (3) of the MOSFET 3 and the threshold voltage Vt (5) of the MOSFET 5. Since it crosses, the output can be inverted to a high level. As a result, as shown in FIG. 5D, the power-on reset signal PORH of the high voltage VDH system is inverted from the low level to the high level, and the power-on reset of the high voltage circuit system is performed in a state where the logic cell state is stable. Can be released.

  According to the present embodiment, since the power-on reset circuit 1 described above is configured for an IC that operates with two power supplies of a low voltage VDL (for example, 1.8 V) and a high voltage VDH (for example, 5 V), By sharing the power reset detection circuit, the circuit can be downsized as a whole, and the CR time constant after the low voltage VDL rises can be configured with high voltage VDH elements to ensure the reset pulse width. Thus, stable operation can be performed on the target circuit.

(Second Embodiment)
FIG. 6 shows the second embodiment, and the following description will be focused on differences from the first embodiment. The power-on reset circuit 21 in this embodiment is not provided with the MOSFET 5 and the capacitor 6 but is provided with a buffer circuit 22 instead of the AND circuit 9.

  In this configuration, the premise is that the power supply IC that supplies the high voltage VDH and the low voltage VDL rises at a predetermined slew rate. In this case, the high voltage VDH system power-on reset signal PORH and the low voltage VDL system power-on reset signal PORL are reset by the same operation as in the first embodiment without providing a time constant circuit by the MOSFET 5 and the capacitor 6. Since the pulse width can be secured, stable operation can be performed on the target circuit.

(Third embodiment)
FIG. 7 shows the third embodiment. Hereinafter, parts different from the first embodiment will be described. The power-on reset circuit 31 in this embodiment is configured to include a MOSFET 32 as a discharge circuit for discharging the charge of the capacitor 6. The P-channel type MOSFET 32 is connected between both terminals of the capacitor 6, and the gate is connected to the drain of the MOSFET 7.

  In the case where the above configuration operates in the same manner as in the first embodiment, portions related to the operation of the MOSFET 32 will be described. When the MOSFET 7 is turned on as in the first embodiment, the MOSFET 32 is turned off because the gate is raised to a high level. Since this state is equivalent to a state in which the MOSFET 32 is not provided, the same operation as in the first embodiment can be performed. As a result, a reset pulse width can be ensured and a stable operation can be performed.

  Then, in the state where the high voltage VDH and the low voltage VDL are applied and the reset pulse is also released as described above, a situation may occur in which the voltage temporarily decreases due to the influence of power supply fluctuation or the like. In this case, the potential of the node B is lowered by turning off the MOSFET 7 regardless of whether the low voltage VDL is lowered or the high voltage VDH is lowered.

  As a result, the P-channel MOSFET 32 is turned on when the gate potential is lowered, and the terminals of the capacitor 6 are short-circuited to rapidly discharge the charge. As a result, the potential of the node A also decreases. Since the output of the AND circuit 9 is inverted to a low level, the high voltage system power-on reset signal PORH is inverted to a low level, and the low voltage system power-on reset signal PORL is also inverted to a low level. Thereby, the reset state of the target circuit is formed.

  Thereafter, when the power is restored, the capacitor 6 is discharged, so that the power-on reset signals PORH and PORL can be released with the reset pulse width secured through the same operation as described above.

  According to the third embodiment, it is possible to obtain the same effect as that of the first embodiment, and by providing the MOSFET 32 as the discharge circuit, due to power fluctuation after the power-on reset is released. A power-on reset operation can be ensured even in the case of a temporary voltage drop.

(Fourth embodiment)
FIG. 8 shows the fourth embodiment. Hereinafter, parts different from the third embodiment will be described. The power-on reset circuit 41 in this embodiment corresponds to a target circuit such as an IC to which the low voltage VDL of 3.3 V is applied instead of the low voltage VDL of 1.8 V used in the third embodiment. Is.

  In this configuration, the low voltage VDL of 3.3 V is input to the gate of the N-channel MOSFET 42 that is separately provided with respect to the low voltage VDL of 1.8 V that is directly connected to the gate of the MOSFET 4. The MOSFET 42 has a drain connected to the high voltage VDH and a source connected to the ground via a series circuit of resistors 43 and 44. The resistors 43 and 44 constitute a voltage dividing circuit, and the common connection point is connected to the gate of the MOSFET 4. The MOSFET 42 used in this embodiment is a depletion type, and the threshold voltage Vt (42) is 0V. The resistors 43 and 44 are set to have a resistance value R (43) = R (44).

  The sum of the threshold voltage of the low-voltage P-channel MOSFET and the threshold voltage of the N-channel MOSFET is about 1.2V, and the threshold voltage of the high-voltage N-channel MOSFET is 0.7V. In the configuration shown in one embodiment, a reliable power-on reset cannot be expected.

  Therefore, this embodiment solves this problem by configuring as described above. That is, a low voltage VDL of 3.3 V is applied to the gate of the depletion type N-channel MOSFET 42. As a result, a low voltage VDL of 3.3 V is supplied to the series circuit of the resistors 43 and 44. Here, if resistances 43 and 44 having the same resistance value are used, the power-on reset operation can be reliably performed by the same operation principle as in the first embodiment.

  In this embodiment, the configuration in which the low voltage VDL of 3.3 V is applied via the MOSFET 42 is to prevent a state in which a current always flows through the power-on reset circuit 41 in a power supply application state. . This has an advantage that current can be prevented from flowing in a stationary state, for example, in IDDQ inspection (static current inspection) performed by a CMOS circuit or the like.

  Also in this embodiment, as in the third embodiment, by providing the MOSFET 32 as a discharge circuit, power-on can be ensured even in a temporary voltage drop due to power fluctuation after the power-on reset is released. A reset operation can be secured.

(Fifth embodiment)
FIG. 9 shows the fifth embodiment. Hereinafter, parts different from the first embodiment will be described. The power-on reset circuit 51 in this embodiment is obtained by adding a circuit that limits the current path and reduces power consumption to the configuration of the first embodiment.

  An analog switch 52 is interposed between the gate and source of the N-channel MOSFET 3, and the gate is connected to the ground via the drain and source of the N-channel MOSFET 53. The NOR circuit 54 is provided such that a steady current cut signal is given to one input terminal. The output terminal of the NOR circuit 54 is connected to one gate of the analog switch, and is connected to the other gate of the analog switch and the gate of the MOSFET 53 via the inverter circuit 55. The NOR circuit 54 functions as a current path control circuit.

  Instead of the AND circuit 9, a NAND circuit 56 is provided. An input terminal of the NAND circuit 56 is connected to the node A and the node B. The output terminal of the NAND circuit 56 is connected to the input terminal of the NAND circuit 57. The NAND circuit 57 is a three-input circuit, and the output terminals of the NOR circuit 54 are connected to the remaining two input terminals, and inverter circuits 58 and 59 are connected in series from the output terminal of the NOR circuit 54. Yes.

  The output terminal of the inverter circuit 58 is connected to the ground via the capacitor 60. The output terminal of the NAND circuit 57 is connected to the input terminal (node C portion) of the inverter circuit 10. The output terminal of the inverter circuit 11 outputs a high-voltage power-on reset signal PORH, and this terminal is connected to the ground through a series circuit of a resistor 61 and a capacitor 62. The common connection point of the resistor 61 and the capacitor 62 is connected to the other input terminal of the NOR circuit 54, and is connected to the power supply terminal of the high voltage VDH via the diode 63 in the forward direction. A resistor 61 and a capacitor 62 constitute a signal holding circuit.

  In the above configuration, when the low-level steady-state current cut signal is input to the NOR circuit 54, the output is at a high level while the low-level signal is also input to the other input terminals. In this state, the analog switch 52 is on and the MOSFET 53 is off, and the configuration is the same as that in the first embodiment.

  In this state, the inverter circuits 11 and 12e output a high level (reset release) signal after outputting a low level (reset state) signal for a certain period of time by performing substantially the same operation as in the first embodiment. As a result, the power-on reset signal is released.

  When the power-on reset signal PORH becomes high level and the reset state is released, in this circuit configuration, charging of the capacitor 62 functioning as a signal holding circuit is started, and the terminal voltage of the capacitor 62 rises to increase the NOR circuit. A high level signal is input to 54. As a result, the output of the NOR circuit 54 is inverted to a low level, the analog switch 52 shifts to the off state, and the MOSFET 53 shifts to the on state.

  Then, the MOSFET 3 shifts to the off state, and accordingly, the MOSFETs 5 and 7 also shift to the off state. In this state, since the high voltage VDH and the low voltage VDL are normally applied, the output of the power-on reset circuit 51 is kept at a high level.

  Thus, in a state where the power-on reset signal is canceled after the power-on reset circuit 51 is operated, the MOSFETs 3, 4, 7 and the like can be turned off, so that the steady current is automatically cut off. Can do.

In this configuration, when the high voltage VDH decreases for some reason, the charge of the capacitor 62 is discharged through the diode 63, so that the power-on reset signals PORH and PORL are inverted to a low level and reset. It can be a signal indicating a state. Thus, when the high voltage VDH is restored, the power-on reset can be surely performed by operating in the same manner as described above.
Also according to the fifth embodiment, it is possible to obtain the same effect as that of the first embodiment, and it is possible to cut the steady current, so that power saving can be achieved.

(Sixth embodiment)
FIG. 10 shows the sixth embodiment. Hereinafter, parts different from the second embodiment will be described. The power-on reset circuit 71 in this embodiment has a configuration in which MOSFETs 72 and 73 functioning as resistive elements are provided in place of the resistors 2 and 8. The MOSFET 72 is a P-channel type, and its gate is connected to the ground. The MOSFET 73 is an N-channel type, and the gate is connected to the high voltage VDH. The MOSFETs 72 and 73 are both always on and function as resistors.

  Therefore, even with such a configuration, it is possible to obtain the same operational effects as in the second embodiment. A configuration in which MOSFETs 72 and 73 are provided instead of resistors 2 and 8 and a function as a resistor is provided. It can be.

(Seventh embodiment)
FIG. 11 shows the seventh embodiment. Hereinafter, parts different from the second embodiment will be described. The power-on reset circuit 81 in this embodiment has a configuration in which a resistor 82 is interposed in series between the resistor 2 and the MOSFET 3. The basic operation of the power-on reset circuit 81 is the same as that of the second embodiment.

  With this configuration, the current that flows as the MOSFETs 3 and 4 are turned on flows through the resistor 2 and the resistor 82, and the voltage generated between the terminals of the resistor 2 can be changed. That is, the power-on reset release voltage can be set high.

  Therefore, according to the seventh embodiment as well, the same effect as that of the second embodiment can be obtained, and the resistor 82 is added to increase (change) the release voltage of the power-on reset. ) Will be able to.

(Eighth embodiment)
FIG. 12 shows the eighth embodiment. Hereinafter, parts different from the second embodiment will be described. The power-on reset circuit 91 in this embodiment constitutes a circuit that outputs a power-on reset signal to an IC that uses power supplies of three different voltages. The three power supplies are a high voltage VDH and low voltages VDL1 and VDL2. The low voltages VDL1 and VDL2 indicate different voltages. The low voltage VDL2 is assumed to be a power supply having a voltage higher than the low voltage VDL1 and lower than the high voltage VDH.

  In this configuration, the low voltage VDL of the configuration in the second embodiment is set as the low voltage VDL1, and a circuit for newly applying the low voltage VDL2 is added. As a circuit configuration, an N-channel MOSFET 92 for detecting the rise of the low voltage VDL2 is connected between the MOSFET 3 and the MOSFET 4 for setting the operation threshold voltage.

  The circuit for inputting the low voltage VDL2 is a series circuit of an N-channel type MOSFET 93 provided separately and resistors 94 and 95 connected in series thereto. The low voltage VDL2 is input to the gate of the MOSFET 93. The MOSFET 93 has a drain connected to the high voltage VDH and a source connected to the ground via a series circuit of resistors 94 and 95. A common connection point between the resistors 94 and 95 is connected to the gate of the MOSFET 92. The MOSFET 93 used in this embodiment is a depletion type, and the threshold voltage Vt (93) is 0V. The operating conditions of the MOSFET 92 are set by setting the resistance values of the resistors 94 and 95 to a predetermined ratio.

  As a result, the MOSFETs 4 and 92 operate when both the low voltages VDL1 and VDL2 rise, and the MOSFET 7 operates when the threshold voltages of the MOSFETs 92, 4 and 3 are exceeded. After this, since the operation is the same as in the second embodiment, the power-on reset signal can be canceled when all of the three power supplies, the high voltage VDH and the low voltages VDL1 and VDL2, are started up. .

(Other embodiments)
In addition, this invention is not limited only to one embodiment mentioned above, It can apply to various embodiment in the range which does not deviate from the summary, For example, it can deform | transform or expand as follows. .

As the resistive element, an element such as a bipolar transistor or a diode can be used in addition to the resistor and the MOSFET.
Different configurations can be adopted for the level shift circuit. A general inverter circuit, a circuit having a memory function such as a flip-flop, or the like can be used.

A MOSFET 32 can be provided as a discharge circuit in the configuration of the fifth embodiment.
The sixth to eighth embodiments can also be applied to the configuration of the first embodiment.
In addition, each said embodiment can be comprised combining suitably.

  In the drawing, 1, 21, 31, 41, 51, 71, 81, 91 are power-on reset circuits, 2, 8 are resistors (resistive elements), 3 is an N-channel MOSFET (second switching element), 4 Is an N-channel MOSFET (third switching element), 5 is a P-channel MOSFET (fourth switching element, time constant circuit), 6 is a capacitor (time constant circuit), and 7 is a P-channel MOSFET (first switching element). Switching element), 9 an AND circuit, 10 an inverter circuit, 11 an inverter circuit (high voltage output circuit), 12 a level shift circuit (low voltage output circuit), and 32 a P channel type MOSFET (discharge circuit) , 42 is an N-channel MOSFET (fifth switching element), 43 and 44 are resistors (voltage dividing circuit), and 54 is a NOR circuit (current path). Control circuit), 61 is the resistance (signal holding circuit), 62 denotes a capacitor (signal holding circuit), 72 and 73 are MOSFET (resistive element), 82 resistance (resistive element), 93 and 94 denote resistors.

Claims (9)

A power-on reset circuit intended for a circuit that operates by receiving supply of a high voltage and a low voltage,
A P-channel first switching element (7) that is turned on when the high-voltage power supply voltage is supplied and the gate voltage is equal to or higher than the first threshold voltage;
A resistive element (2, 72) that is supplied with the high-voltage power supply voltage and applies a gate voltage to the first switching element;
The high power supply voltage is applied to the high-voltage side terminal via the resistive element (2, 72), and N is turned on when the gate voltage of the gate connected to the high-voltage side terminal is equal to or higher than the second threshold voltage. A channel-type second switching element (3);
The N-channel type third that is turned on when the high-voltage power supply voltage is applied through the resistive element and the second switching element, and the gate voltage applied from the low-voltage power supply exceeds a third threshold voltage. A switching element (4);
The low-voltage power supply voltage is supplied, a reset signal for resetting a low-voltage circuit is output when the first switching element is in an off state, and the low-voltage reset signal is stopped when the first switching element is turned on. A power-on reset circuit (1, 21, 31, 41, 51, 71, 81, 91). The power-on reset circuit according to claim 1,
A high voltage that is supplied with the high-voltage power supply voltage, outputs a high-voltage reset signal when the first switching element is off, and stops the high-voltage reset signal when the first switching element is turned on. Power-on reset circuit (1, 21, 31, 41, 51, 71, 81, 91), characterized in that an output circuit (11) is provided. The power-on reset circuit according to claim 1 or 2,
A P-channel type fourth switching element (5) which is turned on when the high power supply voltage is supplied and a gate voltage is supplied from the resistive load (2, 72) and becomes equal to or higher than the first threshold voltage; ,
A capacitor (6) to which the high power supply voltage is supplied via the fourth switching element;
The fourth switching element (5) is turned on to start the charging operation to the capacitor (6), and in response to the operation of stopping the reset signal by the high voltage output circuit (11), 6) a power-on circuit comprising: a time constant circuit (5, 6) which is invalidated when the terminal voltage of 6) is less than a fourth threshold voltage and is activated when the terminal voltage of the capacitor becomes equal to or higher than the fourth threshold voltage. Reset circuit (1, 31, 41, 51). The power-on reset circuit according to claim 3,
A power-on reset circuit (31, 41) comprising a discharge circuit (32) provided to discharge the charge of the capacitor when the first switching element is in an off state. The power-on reset circuit according to any one of claims 1 to 4,
A fifth switching element (42) to which the high power supply voltage is supplied and the low power supply voltage is applied as a gate voltage;
A voltage dividing circuit (43, 44) connected in series to the fifth switching element and dividing a terminal voltage appearing in an ON state of the fifth switching element and outputting the divided voltage as a gate voltage of the third switching element; A power-on reset circuit (41). The power-on reset circuit according to claim 5,
A power-on reset circuit (41), wherein the fifth switching element (42) has a threshold voltage of zero. The power-on reset circuit according to any one of claims 1 to 6,
A signal holding circuit (61, 62) for holding the output level of the reset signal of the high voltage output circuit;
A current path control circuit (54) for turning off the first switching element, the second switching element, and the third switching element when the output state of the signal holding circuit holds the reset signal stop state; A power-on reset circuit (51). The power-on reset circuit according to any one of claims 1 to 7,
A power-on reset circuit (71) using the resistive element (2, 8) or a transistor (72, 73) connected as a resistive load. The power-on reset circuit according to any one of claims 1 to 8,
A reset stop voltage adjusting resistive element (82) for setting a high voltage for stopping the reset signal on the high voltage side is connected in series between the resistive element (2) and the second switching element (3). A power-on reset circuit (81) provided.

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