JPH06112792A - Reset circuit - Google Patents

Abstract

PURPOSE:To prescribe the generation timing of a reset release signal by a voltage. CONSTITUTION:In the reset circuit which automatically releases reset on the way of reaching the supply voltage to a prescribed voltage, a detecting transistor TR 17 which is turned on at the time of impressing of a voltage higher than a threshold value is connected to a power terminal 11, and voltage dividing resistances 12 and 13 are connected between the power terminal 11 and the output of the detecting TR 17, and an output TR 14 is connected to a middle point (a) of voltage dividing resistances 12 and 13, and the reset release signal is outputted from the output TR 14 when a voltage higher than the threshold value is generated between the base of the output TR 14 and the power terminal 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset circuit, and more particularly to a reset circuit which automatically releases a reset of a system when an integrated circuit incorporated in an electronic device is powered on.

[0002]

2. Description of the Related Art For example, since a system is automatically reset when a power supply of an integrated circuit incorporated in an electronic device is turned on, a circuit is set to an initial state when the power supply voltage is low after the power is turned on. A reset circuit is used that generates a reset release signal when the voltage is reached.

A conventional example of this reset circuit will be described with reference to FIG.

The reset circuit includes a CMOS buffer (1), and the CMOS buffer (1) is provided in front of the CMOS buffer (1).
A resistor (3) and a capacitor (4) connected to the power supply terminal (2) are provided. In the figure, (5) is a diode for rapidly discharging the electric charge charged in the capacitor (4) when the power is off, and (6) is an output terminal.

Here, FIG. 5 shows the power supply voltage V _CC , the terminal voltage V _A of the capacitor (4), the threshold voltage V _{Q of} the CMOS buffer (1), and the output voltage V _OUT of the CMOS buffer (1).
The relationship of the above is shown, and based on this, the operation of the reset circuit having the above configuration will be described below.

First, when the power supply is turned on, the power supply voltage V _CC rises, and at the same time, the capacitor (4) passes through the resistor (3).
Will be charged. On the other hand, the threshold voltage V _Q of the CMOS buffer (1) is set while maintaining a relationship of approximately 1/2 with respect to the power supply voltage V _CC , and the capacitor (4)
Is charged, the terminal voltage V _A of the capacitor (4) becomes
When the threshold voltage V _Q of the OS buffer (1) is reached,
The output voltage V _OUT of the CMOS buffer (1) rises,
As a result, the CMOS buffer (1) outputs a reset release signal. This reset release signal automatically releases the reset of the system connected to the subsequent stage.

[0007]

By the way, in the above-mentioned conventional reset circuit, the time constants of the resistor (3) and the capacitor (4) connected to the power supply terminal (2) and the threshold of the CMOS buffer (1). A reset release signal is output from the CMOS buffer (1) in relation to the value. Therefore, if the rising waveform of the power supply voltage V _CC varies depending on the load, the terminal voltage V _A of the capacitor (4) also follows and changes, so that the rising waveform of the power supply voltage V _CC is C
It greatly affects the output voltage V _OUT of the MOS buffer (1). As described above, the generation timing of the reset release signal depends on the time, and the generation timing of the reset release signal varies, resulting in a problem of lack of reliability.

Therefore, the present invention has been proposed in view of the above problems, and an object of the present invention is to provide a reset circuit which can regulate the generation timing of a reset release signal by a voltage.

[0009]

As a technical means for achieving the above object, the present invention provides a reset circuit that automatically releases a reset while a power supply voltage reaches a predetermined voltage. In addition to connecting a piezoresistor, connect a control element to the middle point of the voltage dividing resistance, and reset the output of the control element when a voltage above the threshold value is generated between the control electrode of the control element and the power supply terminal. It is characterized by being a signal.

In the present invention, it is desirable that a detecting element which is turned on when a voltage higher than a threshold value is applied is connected to the power supply terminal and an output of the detecting element is connected to a voltage dividing resistor.

[0011]

In the reset circuit according to the present invention, the generation timing of the reset release signal output from the control element is defined by the voltage determined by the voltage dividing ratio of the voltage dividing resistor and the threshold value of the control element. You can

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a reset circuit according to the present invention will be described with reference to FIGS.

FIG. 1 shows a basic circuit configuration of the present invention.
This reset circuit consists of a voltage dividing resistor (12) (13) connected between the power supply terminal (11) and ground, and the voltage dividing resistor (12).
It is composed of an output transistor (14) which is a control element connected to the midpoint (a) of (13). Specifically, the base of the output transistor (14) has a voltage dividing resistor (12).
It is connected to the midpoint (a) of (13) and the emitter is connected to the power supply terminal (1
In 1), the collector is connected to the output terminal (15) respectively. In the figure, (16) is a pull-down resistor at the output end.

Next, FIG. 2 shows a concrete circuit configuration of the present invention. This is obtained by adding a detection transistor (17) and resistors (18) and (19) to the basic circuit configuration of the reset circuit. Specifically, connect a series circuit of resistors (18) and (19) to the power supply terminal (11), connect the base of the detection transistor (17) between the resistors (18) and (19), and connect the collector thereof. Connect to the voltage dividing resistor (13).

Here, FIG. 3 shows the relationship between the power supply voltage V _CC and the output voltage V _OUT of the output transistor (14). Based on this, the operation of the reset circuit having the above configuration will be described below.

In the reset circuit of FIG. 1, when the power is turned on, the power supply voltage V _CC is applied to the voltage dividing resistors (12) and (13). Here, if the detection transistor (17) is added as in the reset circuit of FIG. 2, the power supply voltage V _CC rises when the power is turned on, and the midpoint potential of the resistors (18) and (19). When becomes equal to or higher than the base voltage of the detection transistor (17), the detection transistor (17) is turned on to bring its collector voltage to the ground potential. As a result, similarly to the above, the power supply voltage V _CC is applied to the voltage dividing resistors (12) and (13). If the detection transistor (17) is provided in this way,
It is possible to prevent malfunction due to noise that tends to occur when the power is turned on.

When the power source voltage V _CC is applied to the voltage dividing resistors (12) and (13) in this manner, the voltage dividing resistors (12) and (13) are applied.
The output transistor (1 with its base connected to the midpoint (a)
In 4), since the voltage across the voltage dividing resistors (12) and (13) is equal to the power supply voltage V _CC , the voltage between the power supply terminal (11) and the base that is the control electrode of the output transistor (14) is voltage, i.e., when the base-emitter voltage V _bE, when the power supply voltage _{V CC = V bE {1+ (} R 2 / R 1)} becomes, the output transistor (14) is turned ON The output voltage V _OUT rises, and the reset release signal is output from the output transistor (14).

Thus, the output transistor (14)
A voltage dividing resistor (12) (13) between the base and the power supply terminal (11)
Generation timing of the reset release signal output from the output transistor (14) by preventing the output transistor (14) from being turned on until a voltage exceeding a threshold value determined by the voltage division ratio of Can be specified by voltage.

By defining the generation timing of the reset release signal by the voltage, the generation timing of the reset release signal does not vary without being affected by the rising waveform of the power supply voltage V _CC .

[0020]

According to the reset circuit of the present invention, the generation timing of the reset release signal is regulated by the voltage, so that the generation timing of the reset signal varies without being affected by the rising waveform of the power supply voltage or the like. Since it does not occur, it is possible to prevent malfunctions that are likely to occur when the power is turned on, and reliability is greatly improved.

[Brief description of drawings]

FIG. 1 shows an embodiment of a reset circuit according to the present invention, and its basic configuration circuit diagram.

FIG. 2 is a specific configuration circuit diagram of a reset circuit of the present invention.

FIG. 3 is a diagram showing a reset circuit of the present invention, in which a power supply voltage V _CC
Diagram showing the relationship between the output voltage V _OUT of the output transistor and the output voltage

FIG. 4 is a circuit diagram showing a conventional example of a reset circuit.

FIG. 5 shows a power supply voltage V in a conventional reset circuit._CC,
Capacitor terminal voltage V_A, C Threshold of MOS buffer
Value voltage V_Q, CMOS buffer output voltage V_OUTRelationship
Characteristic diagram

[Explanation of symbols]

 11 Power supply terminal 12 Voltage dividing resistor 13 Voltage dividing resistor 14 Output transistor 17 Detection transistor a Middle point

Claims (3)

[Claims] 1. In a reset circuit that automatically releases reset while the power supply voltage reaches a predetermined voltage, a voltage dividing resistor is connected to a power supply terminal, and a control element is connected to the middle point of the voltage dividing resistor. A reset circuit characterized in that the output of the control element at the time when a voltage above a threshold value is generated between the control electrode of the control element and the power supply terminal is used as a reset release signal. 2. A detection element which is turned on when a voltage equal to or higher than a threshold value is applied to the power supply terminal according to claim 1,
A reset circuit in which the output of the detection element is connected to a voltage dividing resistor. 3. A detection transistor, which conducts when a voltage higher than a threshold value is applied, is connected to a power supply terminal, a voltage dividing resistor is connected between the power supply terminal and the output of the detection transistor, and the middle point of the voltage dividing resistor is connected. Connect the output transistor,
A reset circuit that causes a reset release signal to be output from the output transistor when a voltage above a threshold value is generated between the base of the output transistor and the power supply terminal and automatically operates while the power supply voltage reaches a predetermined voltage.