JPS5921552Y2 - reset circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a reset circuit that resets an electronic circuit such as a logic circuit or a counting circuit when the power is turned off, and detects the difference between the terminal voltage of a capacitor and the power supply voltage when the power is turned off,
To provide a circuit which can apply a reset voltage to an electronic circuit immediately after power-off by forcibly and rapidly changing the terminal voltage of a capacitor that obtains a reset output, and can surely reset the electronic circuit without malfunction. With the goal.

In electronic circuits such as logic circuits and counting circuits, it is necessary to set or reset each function to an initial state when the power is turned on or off.

This means that if the circuit is not reset when electrolytic corrosion is turned on, it will no longer work properly, and if the circuit is not reset when the power is turned off, uncertain or incorrect information will continue to be generated when the power is turned off. It is a necessary function for logic circuits and counting circuits because it is transmitted to other devices.

On the other hand, even in circuits that do not need to be reset when the power is turned off,
As the power is turned on and off alternately, the power supply voltage and reset voltage may not be completely discharged, and the device may not be reset when the power is turned on.

The electronic circuit targeted by the present invention is, among the above-mentioned types of circuits, particularly a circuit that needs to be put into a reset state when the power is turned off.

FIG. 1 shows a circuit diagram of an example of a conventional reset circuit.

In the figure, when a voltage is applied to power supply terminal 1 at time to, the voltage at terminal 1 rises as shown in Fig. 2A, and the voltage at reset terminal 2 rises as shown in Fig. 2B. ')
It rises with a time constant of

When the power is turned off at time t□, the voltage at terminal 1 becomes A in Figure 2.
As shown in FIG. 2B, the voltage at the noset terminal 2 decreases with a relatively large time constant, and as the capacitor C discharges through the diode D, the voltage decreases as shown in FIG.

In this case, for example, a logic circuit is connected to terminal 2, and terminal 2 is a threshold voltage (reset voltage) Vr
The logic circuit is configured to enter the reset state at the following times T and T'.

However, in this conventional reset circuit, since the voltage waveform at terminal 2 when the power is turned off is approximately the same as the power supply voltage waveform, the time τ from when the power is turned off until the logic circuit enters the reset state is relatively long. This has the disadvantage that there is a possibility that a voltage level that causes the logic circuit to malfunction may occur within this time τ'.

Furthermore, as shown in FIG. 2A, if the power supply is turned on and off alternately at a relatively fast speed, the reset voltage remains at terminal 2 even though the power supply is turned off because the above-mentioned time τ' is relatively long. There was a drawback that a voltage lower than Vr was not applied, and as a result, the logic circuit could not be reliably reset.

The present invention eliminates the above-mentioned drawbacks, and one embodiment thereof will be described with reference to FIG. 3 and the following figures.

FIG. 3 shows a circuit diagram of an embodiment of the reset circuit according to the present invention.

In the figure, a diode D1 and a resistor R1 are connected in series, and resistors R2, R3, and R5 are connected to a power supply voltage terminal 1.

A circuit (charging circuit) consisting of a diode D1 and resistors R1 and R2 is inserted between the power supply voltage terminal 1 and the capacitor C1 (second capacitor).

The other end of the resistor R3 is connected to the base of the PNP transistor Q (first transistor), and the connection point between the resistors R1 and R2 is connected to the emitter of the transistor Q1 and one end of the capacitor C1. Q1
The collector of is connected to an NPN transistor Q via a resistor R4.
2 (second transistor).

The collector of the transistor Q2 is connected to a resistor R5 (first capacitor) and the reset terminal 2, and its emitter is connected to the other end of the capacitor C1 and the other end of the capacitor C2, and is grounded.

A time constant circuit composed of a resistor R5 and a capacitor C2 is interposed between the power supply voltage terminal 1 and the emitter of the transistor Q2.

Here, time t.

When the power is turned on, the voltage at terminal 1 rises to voltage Vcc as shown in FIG.
As shown in Figure B, the terminal voltage of is determined by the time constant C1・(R2/R
1) (however, R2>R1), and the capacitor C
2, that is, the voltage at terminal 2 increases with time constants R5 and C2, as shown in the figure.

The time constant C1·(R2/R1) has a value smaller than the time constant R5°C2.

The logic circuit connected to the terminal 2 is configured to be in a reset state at a time T when the voltage of the terminal 2 is equal to or lower than the reset voltage Vr.

Note that when the power is on, the transistor Q1 is in an off state.

When the power is turned off at time t2, the voltage at terminal 1 drops with a relatively large time constant as shown in FIG. 4A, as in the conventional circuit, and at the same time, capacitor C1
The capacitor C1 is discharged with a time constant, and the terminal voltage of the capacitor C1 drops as shown in FIG.

When the power supply voltage reaches Ver and the terminal voltage of the capacitor q reaches Ver' due to the power being turned off, the base potential of the transistor Q1 becomes lower than its emitter potential, and the transistor Q1 turns on at time t3 as shown in FIG. 4C. become.

On the other hand, when the power is turned off, the terminal voltage of the capacitor C2 drops due to natural discharge as shown in the fourth diagram.

When the transistor Q1 is turned on, the transistor Q is turned on, and as a result, the capacitor C2 is forcibly discharged through the transistor Q2, and as shown in the figure, the terminal voltage becomes 02.(between the collector and emitter of the transistor Q2) from time t3. When this voltage falls below Vr, the logic circuit is reset.

In other words, the discharge of capacitor C2 is greater than the discharge of capacitor C2.
1 discharge is performed first.

In this case, since only the internal resistance of the transistor Q2 is connected to the discharge path of the capacitor C2, the discharge of the capacitor C2 is extremely steep.

Therefore, by setting the voltage Ver that is slightly lower than the voltage Ver at which the transistor Q1 can be turned on, the time τ from the time t2 when the power is turned off until the voltage at the terminal 2 becomes equal to or lower than Vr can be obtained using the conventional circuit. can be shorter than the time τ' (FIG. 2B).

In this way, since the time from when the power is turned off until the voltage at the terminal 2 becomes equal to or lower than Vr is short, there is no possibility that a voltage level that causes the logic circuit to malfunction will occur.

Furthermore, as shown in FIG. 4A, if the power is turned on again at time ts immediately after turning off the power at time t4 (however, the time from time t4 to t5 is longer than time τ), the above-mentioned Due to this operation, as shown in the fourth diagram, the time τ from time t4 until the voltage at terminal 2 becomes lower than Vr is extremely short, so the logic circuit can be reliably reset. The logic circuit can be reliably reset even if it is alternately turned on and off.

Note that although the above embodiment is a negative logic reset, the present invention is not limited to a negative logic reset, and can be similarly applied to a positive logic reset.

In this case, in FIG. 3, the collector of transistor Q1 is connected to ground via resistor R4, the other end of capacitor C1 is connected to ground, and capacitor C2 and resistor R5 are connected to the connection point of resistor R2 and diode D1. are connected in series and connected to ground, and terminal 2 is connected to the connection point between capacitor C2 and resistor R5 (however, transistor Q2 may not be provided).

In this way, when the power is turned on, a differential pulse is taken out from terminal 2, and the electronic circuit is reset (positive logic reset) at a voltage higher than the reset voltage Vr, and when the power is turned off, the difference between the terminal voltage of the capacitor C1 and the power supply voltage is The dynamic pressure is detected by the transistor Q1, the voltage between the terminals of the resistor R2 is applied to the capacitor C2, a differential pulse is taken out from the capacitor C2, and the electronic circuit is reset to positive logic.

At this time, as in the case of negative logic reset, since the time until the electronic circuit is reset is shorter than when the power is turned off, the logic circuit can be reliably reset without malfunction.

Moreover, the transistor Q1. An operational amplifier may be used instead of Q2, and in this case, the power source of the operational amplifier may be the charging voltage from the capacitor C2.

As described above, the reset circuit according to the present invention is a reset circuit that resets the electronic circuit connected to the downstream stage of the first capacitor using the terminal voltage of the first capacitor that is charged and discharged when the power is turned on and off. , a time constant circuit including the first capacitor and connected to the power source, a second capacitor that is charged and discharged by turning on and off the power source, and between the second capacitor and the power source. The charging current is supplied from the power supply so that the second capacitor is rapidly charged when the power is turned on, and the second capacitor is rapidly discharged toward the power supply when the power is turned off. a charging circuit for blocking the discharging current of the second capacitor to prevent the second capacitor from discharging, an emitter connected to the connection point between the second capacitor and the charging circuit, a base connected to the power supply, and a base of the second transistor A collector is connected to the power supply, and when the voltage difference between the voltage at the connection point of the second capacitor and the charging circuit and the power supply voltage becomes equal to or higher than a predetermined level when the power supply is turned off, the collector is turned on and the collector is connected to the second capacitor. a first transistor that rapidly discharges the charged charge through the emitter and collector, and a collector between both terminals of the first capacitor;
a second transistor whose emitter is connected, the first transistor is turned on, and the charged charge of the second capacitor is supplied, thereby turning on and forcibly discharging the charged charge of the first capacitor; It consists of
When the power is turned off, the reset circuit is characterized in that the charge in the second capacitor is discharged before the charge in the first capacitor is discharged. Even if the reset circuit of the present invention is connected to a power supply that has a large time constant due to another circuit other than the above, the reset circuit of the present invention will not be reset to the electronic circuit even when the power is turned off, without depending on the time constant of the power supply. Since it has a circuit that can independently set the time until the pulse is applied, the time from when the power is turned off until the reset voltage is applied to the electronic circuit does not depend on the time constant of the external power supply. This eliminates the risk of voltage levels that could cause the electronic circuitry to malfunction between the time the power is turned off and the time the electronic circuits are reset, and it also allows the power supply to be operated at high speeds. Even if the circuit is turned on and off alternately, the time from when the power is turned off to when the reset voltage is applied is short, so the electronic circuit can be reliably reset.

[Brief explanation of the drawing]

1 and 2 A and B are respectively circuit diagrams of examples of conventional reset circuits and voltage waveform diagrams for explaining its operation, and FIGS. 3 and 4 A-D are respectively circuit diagrams of reset circuits according to the present invention. FIG. 2 is a circuit diagram of one embodiment of the circuit and voltage and current waveform diagrams for explaining its operation. 1...Power supply voltage terminal, 2...Output terminal, R1-R6...Resistor, C1, C2...
・Capacitor, Ql, Q2 transistor, Dl...
··diode.

Claims (1)

[Scope of utility model registration request] In a reset circuit that resets an electronic circuit connected downstream of the first capacitor using the terminal voltage of the first capacitor that is charged and discharged when the power is turned on and off, the power supply, including the first capacitor, A second capacitor is connected between the second capacitor and the power supply, and is charged and discharged when the power supply is turned on and off, respectively. A charging current is supplied from the power source so that the second capacitor is rapidly charged,
a charging circuit that blocks the discharging current of the second capacitor so that the capacitor does not discharge abruptly to the power supply;
An emitter is connected to a connection point between the second capacitor and the charging circuit, a base is connected to the power source, and a collector is connected to the base of the second transistor, so that when the power source is turned off, the second capacitor is connected to the charging circuit. When the voltage difference between the voltage at the connection point with the charging circuit and the power supply voltage exceeds a predetermined level, it turns on and rapidly discharges the charge stored in the second capacitor through the emitter and collector. A collector and an emitter are connected between a first transistor and both terminals of the first capacitor, and the first transistor is turned on and is turned on by being supplied with the charge of the second capacitor. and a second transistor for forcibly discharging the charge in the first capacitor, and when the power is turned off, the charge in the second capacitor is discharged more than the charge in the first capacitor. A reset circuit characterized by the following: