JP3687477B2 - Power-on reset circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power-on reset circuit for automatically performing a reset operation when an electronic device is powered on.
[0002]
[Prior art]
Conventionally, an example of this type of power-on reset circuit is shown in FIG.
[0003]
As shown in FIG. 5, this power-on reset circuit is connected to a time constant circuit 1 in which a resistor R1 and a capacitor C1 are connected in series between a power source and a ground, and a common connection portion of the resistor R1 and the capacitor C1. The power supply voltage VDD is applied to one end of the resistor R1.
[0004]
In the power-on reset circuit having such a configuration, when power is turned on, the power supply voltage VDD rises relatively quickly as shown in FIG. Further, the capacitor C1 is charged with a time constant of C1 · R1 through the resistor R1, and the charging voltage Vn of the node N1 rises later than the rising of the power supply voltage VDD as shown in FIG. When the charging voltage Vn reaches a predetermined level, the reset signal R output from the buffer 2 changes from the “L” level to the “H” level in a relatively short time, as shown in FIG.
[0005]
Based on the reset signal R, an electronic device (not shown) such as a CPU connected to the same power source as described above is automatically reset when the power is turned on, and the electronic device can enter a normal operation state. .
[0006]
[Problems to be solved by the invention]
By the way, the resistor R1 constituting the time constant circuit 1 is generally a high resistance (for example, several MΩ) in order to increase the time constant, and there is a possibility of malfunction when noise (noise) is applied to the node N1.
[0007]
In addition, when the power supply voltage varies, the reset signal output from the buffer 2 may become unstable.
[0008]
Further, when the power supply voltage rises very slowly, there is a possibility that the reset signal is not output from the buffer 2 within a predetermined time.
[0009]
SUMMARY OF THE INVENTION An object of the present invention is to provide a power-on reset circuit that stabilizes the operation when generating a reset signal and reduces current consumption after the generation.
[0010]
[Means for Solving the Problems]
In order to solve the above-described problems and achieve the object of the present invention, each invention described in claims 1 to 6 is configured as follows.
[0011]
Specifically, the invention according to claim 1 is a time constant circuit, a detection circuit for detecting an output voltage of the time constant circuit, a flip-flop circuit having two inverters whose inputs and outputs are interconnected, and the detection circuit Feedback circuit to the input side of the detection circuit, the flip-flop circuit is initialized when the power is turned on, and when the voltage detected by the detection circuit reaches a predetermined value, The stable state is reversed.
[0012]
According to a second aspect of the present invention, in the power-on reset circuit according to the first aspect, the detection circuit comprises a series circuit in which a first MOS transistor and a diode-connected second MOS transistor are connected in series, and an output thereof The side is connected to the input side of the flip-flop circuit, and a power supply voltage is applied to the first MOS transistor.
[0013]
According to a third aspect of the present invention, in the power-on reset circuit according to the first or second aspect, the initialization of the flip-flop circuit upon power-on is performed by capacitively coupling the flip-flop circuit and the power source. This is characterized in that it is performed by the following.
[0014]
According to a fourth aspect of the present invention, in the power-on reset circuit according to the first, second, or third aspect, the two inverters are CMOS inverters.
[0015]
According to a fifth aspect of the present invention, in the power-on reset circuit according to any one of the first to fourth aspects, the detection operation of the detection circuit is stopped after the output of the flip-flop circuit is inverted. It is characterized by that.
[0016]
According to a sixth aspect of the present invention, there is provided a time constant circuit having a first capacitor and a resistor connected in series between a first power source and a second power source, and the first capacitor of the time constant circuit. A detection circuit that inputs a voltage corresponding to a voltage of a connection node between the resistor and the resistor, switches the output to the first power supply side when the voltage input reaches a predetermined level, and an output of the detection circuit is an input node Two inverters whose inputs and outputs are connected to each other between the input node and the output node, and a second one end connected to the input node and the other end connected to the second power source. A flip-flop circuit having a capacitor, and a third capacitor having one end connected to the output node and the other end connected to the first power source, and the first capacitor is connected to the detection circuit according to the output voltage of the detection circuit. 2 power supply and time constant It is characterized in further comprising a feedback circuit connecting control between a connection node of the road.
[0017]
As described above, in the inventions described in claims 1 to 6, in addition to the detection circuit, a time constant circuit that uses the power supply voltage and generates a voltage that rises later than the rise of the power supply voltage is provided. The flip-flop circuit is operated by the voltage generated by the constant circuit. For this reason, a stable reset operation can be ensured even when the rising speed of the power supply is fast.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0021]
A first embodiment of a power-on reset circuit according to the present invention will be described with reference to FIGS.
[0022]
As shown in FIG. 1, the power-on reset circuit according to the first embodiment includes a detection circuit 3 that detects that the rising level of the power supply voltage VDD has reached a predetermined value when the power is turned on, two inverters 41, And a flip-flop circuit 4 having two stable states, which is composed of 42 and capacitors C2, C3 and the like.
[0023]
As shown in FIGS. 1 and 2, the detection circuit 3 has an NMOS transistor Q1 and a diode-connected NMOS transistor Q2 connected in series, and the drain of the NMOS transistor Q1 is connected to the input side of the flip-flop circuit 4, The source of the transistor Q2 is grounded. The power supply voltage VDD is applied to the gate of the NMOS transistor Q1.
[0024]
The detection circuit 3 can adjust the detection level by adjusting the number of stages of diode-connected NMOS transistors Q2 connected in series.
[0025]
As shown in FIG. 1, in the flip-flop circuit 4, the input and output of two inverters 41 and 42 are connected to each other, and a capacitor C2 is connected between a common connection part on the input side and a power source. A capacitor C3 is connected between the common connection on the output side and the ground, and a power-on reset signal is output from the output terminal 5.
[0026]
As shown in FIG. 2, the inverter 41 includes a CMOS inverter including a PMOS transistor Q3 and a PMOS transistor Q4. Similarly, as shown in FIG. 2, the inverter 42 includes a CMOS inverter including a PMOS transistor Q5 and a PMOS transistor Q6.
[0027]
Next, the operation of the power-on reset circuit according to the first embodiment having such a configuration will be described with reference to FIGS.
[0028]
Now, when the power is turned on, the power supply voltage VDD rises as shown in 3 (A) and reaches the maximum value (saturation value). Since the input side of the flip-flop circuit 4 is pulled to the power supply voltage VDD by the capacitor C2, the input voltage Q rises as shown in FIG. 3B and becomes a predetermined value.
[0029]
On the other hand, since the output side of the flip-flop circuit 4 is pulled to the ground side by the capacitor C3, the output voltage (power-on reset signal) R is maintained at the “L” level as shown in FIG. Yes.
[0030]
When the power supply voltage VDD reaches the maximum value, the MOS transistor Q1 is turned on, and the charge of the capacitor C2 is discharged through the MOS transistors Q1 and Q2. For this reason, the input voltage Q of the flip-flop circuit 4 decreases as shown in FIG. As a result, the output voltage R of the flip-flop circuit 4 is inverted from the “L” level to the “H” level as shown in FIG. Thereafter, the voltage of each part is fixed.
[0031]
As described above, according to the power-on reset circuit of the first embodiment, the flip-flop circuit 4 is initialized when the power is turned on, and stable when the detection level of the detection circuit 3 reaches a predetermined value. The state is reversed. For this reason, even when the rise of the power supply changes very slowly, the flip-flop circuit 4 is reliably reset and a reset signal can be reliably obtained.
[0032]
In addition, since the flip-flop circuit 4 is used to maintain the state before and after the reset, it has excellent noise resistance and no risk of malfunction. Further, since the flip-flop circuit 4 does not change its state after resetting, the steady-state current consumption is small.
[0033]
Next, a second embodiment of the power-on reset circuit of the present invention will be described with reference to FIG.
[0034]
As shown in FIG. 4, the power-on reset circuit according to the second embodiment is further provided with a time constant circuit and the like in the first embodiment shown in FIG. 1, and stable power-on even when the power supply voltage rises quickly. A reset signal can be obtained.
[0035]
That is, the power-on reset circuit according to the second embodiment includes at least a time constant circuit 11, a buffer 12, a feedback circuit 13, a detection circuit 3, and a flip-flop circuit 4, as shown in FIG. What is different from the first embodiment is that a time constant circuit 11, a buffer 12, and a feedback circuit 13 are newly provided. Therefore, the same components as those of the power-on reset circuit of FIG. 1 are denoted by the same reference numerals and description thereof is omitted as appropriate.
[0036]
The time constant circuit 11 is a circuit in which a resistor R1 and a capacitor C1 are connected in series between a power source and ground. The output of the time constant circuit 11 is configured to be applied to the gate of the MOS transistor Q1, which is the input of the detection circuit 3, via the buffer 12. Note that the buffer 12 is used for waveform shaping and can be omitted.
[0037]
The output of the detection circuit 3 is fed back to the input side of the detection circuit 3 via a feedback circuit 13 composed of a PMOS transistor Q7. That is, the PMOS transistor Q7 has its source connected to the power supply, its gate connected to the drain of the MOS transistor Q1, and its drain connected to the input side of the buffer 12.
[0038]
Next, the operation of the power-on reset circuit according to the second embodiment having such a configuration will be described.
[0039]
Now, when the power is turned on, the output voltage (charge voltage) Vn of the time constant circuit 11 rises with a delay from the rise of the power supply voltage VDD. At this time, the input voltage Q of the flip-flop circuit 4 rises as in FIG. 3B, and the output voltage R of the flip-flop circuit 4 is maintained at the “L” level as in FIG. 3C. It is in the state that was done.
[0040]
When the output voltage Vn of the time constant circuit 11 reaches a predetermined value after the power supply voltage VDD reaches the maximum value, the MOS transistor Q1 of the detection circuit 3 is turned on, and the charge of the capacitor C2 is discharged through the MOS transistors Q1 and Q2. . For this reason, the input voltage Q of the flip-flop circuit 4 decreases as in FIG. As a result, the output voltage R of the flip-flop circuit 4 is inverted from the “L” level to the “H” level as in FIG.
[0041]
At this time, the MOS transistor Q7 is turned on and the capacitor C1 is discharged. As a result, the detection circuit 3 is in a non-detection state, and the potential of each part is fixed.
[0042]
As described above, according to the power-on reset circuit of the second embodiment, in addition to the detection circuit 3, the time constant circuit 11 that generates a voltage that rises later than the rise of the power supply voltage is provided. The flip-flop circuit 4 is operated by the output voltage of 11. For this reason, the flip-flop circuit 4 can ensure a stable reset operation even when the rising speed of the power supply is fast.
[0043]
Further, after the flip-flop circuit 4 is reset, each node is fixed to a predetermined state by the MOS transistor Q7, so that it is excellent in noise resistance and there is no risk of malfunction.
[0044]
【The invention's effect】
As described above, in each of the inventions according to claims 1 to 4, the flip-flop circuit is initialized when the power is turned on, and the stable state is inverted when the detection level of the detection circuit reaches a predetermined value. It is supposed to be. For this reason, even when the rise of the power supply changes very slowly, the flip-flop circuit is reliably reset and a reset signal can be reliably obtained.
[0045]
In each of the inventions according to claims 1 to 4, since the flip-flop circuit is used for maintaining the state before and after the reset, the noise resistance is excellent and there is no risk of malfunction. Further, since the flip-flop circuit does not change its state after resetting, the steady-state current consumption is small.
[0046]
Further, in the inventions according to claims 5 and 6, in addition to the detection circuit, a time constant circuit for generating a voltage that rises later than the rising of the power supply voltage is provided, and the flip-flop circuit is provided by the generated voltage of the time constant circuit. It was made to work. For this reason, a stable reset operation can be ensured even when the rising speed of the power supply is fast.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.
FIG. 2 is a circuit diagram of the first embodiment, in which a portion of a flip-flop circuit is shown in detail.
FIG. 3 is a waveform diagram of a main part of the first embodiment.
FIG. 4 is a circuit diagram showing a configuration of a second embodiment of the present invention.
FIG. 5 is a circuit diagram of a conventional circuit.
FIG. 6 is a waveform diagram of a main part of a conventional circuit.
[Explanation of symbols]
R1 resistors C1 to C3 capacitors Q1 to Q7 MOS transistor 3 detection circuit 4 flip-flop circuit 5 output terminal 11 time constant circuit 12 buffer 13 feedback circuits 41 and 42 inverter

Claims (6)

A time constant circuit;
A detection circuit for detecting an output voltage of the time constant circuit;
A flip-flop circuit having two inverters whose inputs and outputs are interconnected;
A feedback circuit that feeds back the output of the detection circuit to the input side of the detection circuit;
With
The flip-flop circuit is initialized when the power is turned on, and a stable state is inverted when a voltage detected by the detection circuit reaches a predetermined value. .   2. The detection circuit includes a series circuit in which a first MOS transistor and a diode-connected second MOS transistor are connected in series, and an output side of the detection circuit is connected to an input side of the flip-flop circuit. The power-on reset circuit described in 1.   3. The power-on reset according to claim 1, wherein the flip-flop circuit is initialized when power is turned on by capacitively coupling the flip-flop circuit and a power source. circuit.   4. The power-on reset circuit according to claim 1, wherein the two inverters are CMOS inverters. 5.   5. The power-on reset circuit according to claim 1, wherein the detection operation of the detection circuit is stopped after the output of the flip-flop circuit is inverted. A time constant circuit having a first capacitor and a resistor connected in series between a first power supply and a second power supply;
A detection circuit that inputs a voltage corresponding to a voltage of a connection node between the first capacitor and the resistor of the time constant circuit, and switches the output to the first power supply side when the voltage input reaches a predetermined level. When,
The output of the detection circuit is connected to an input node, two inverters whose inputs and outputs are connected to each other between the input node and the output node, one end to the input node, and the other end to the second power source A flip-flop circuit having a second capacitor respectively connected to the output node, and a third capacitor having one end connected to the output node and the other end connected to the first power source,
With
A power-on reset circuit, further comprising a feedback circuit that controls connection between the second power supply and a connection node of the time constant circuit in accordance with an output voltage of the detection circuit.

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