JP2854701B2 - Reference voltage generation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a reference voltage generating circuit manufactured by using a CMOS process technology or the like, wherein a reference voltage is determined by a band gap voltage of a transistor.

(Prior Art) Conventionally, as a technique in this kind of field, Japanese Unexamined Patent Publication No.
There was one described in No. 13 publication. Hereinafter, the configuration will be described with reference to the drawings.

FIG. 2 is a circuit diagram showing a configuration example of a conventional reference voltage generation circuit.

This reference voltage generation circuit is composed of power supply voltage VDD and ground GND.
And an NPN transistor 1 and a resistor 2 connected in series via a node N1. The collector and base of the transistor 1 are connected to the collector and base of an NPN transistor 3, respectively. Further, resistors 4 and 5 are connected in series between the emitter of the transistor 3 and the ground GND via the node N2. The transistors 1, 3 and the resistors 2, 4, 5 constitute a reference voltage generator.

The node N2 is connected to the positive-phase input side of an operational amplifier (hereinafter referred to as an operational amplifier) 6 serving as a reference output voltage generator, and the node N1 is connected to the negative-phase input side. Operational amplifier 6
Has a function of outputting a reference output voltage Vf and an output state of the reference output voltage Vf being controlled by a power-down signal PS.

The output side of the operational amplifier 6 is connected to the bases of the transistors 1 and 3 and to the positive-phase input side of the operational amplifier 7. The opposite-phase input side of the operational amplifier 7 is connected to the ground GND via the resistor 8, and is commonly connected to the output side of the operational amplifier 7 and the output terminal 10 for outputting the output voltage Vout via the variable resistor 9.

 Next, the operation will be described.

On the node N1, a first reference voltage V1 divided by the transistor 1 and the resistor 2 is generated. On the node N2, a second reference voltage V2 obtained by dividing the emitter output of the transistor 3 by the resistors 4 and 5 Occurs. When these reference voltages V1 and V2 are input to the negative-phase input side and the positive-phase input side of the operational amplifier 6, respectively, the reference output voltage is output from the output side of the operational amplifier 6.
Vf is output. This reference output voltage Vf is
The constant currents 11 and 12 flow to the emitters of the transistors 1 and 3 as a result.

The reference output voltage Vf is input to the operational amplifier 7 on the positive-phase input side. Further, by dividing the output of the op-ape 7 by the variable resistor 9 and the resistor 8 and inputting them to the opposite-phase input side, an output voltage Vout obtained by multiplying the reference output voltage Vf by a constant is obtained. This output voltage Vout can be expressed by the following equation.

Vout = (1+ (R9 / R8) · Vf where R8; resistance value of resistor 8 R9; resistance value of variable resistor 9 By setting the resistance value R9 of variable resistor 9 arbitrarily,
The output voltage Vout can also be set arbitrarily.

(Problems to be Solved by the Invention) However, the reference voltage generating circuit having the above configuration has the following problems.

When the power supply voltage is turned on, in the process in which the power supply voltage VDD rises from the ground GND potential, for example, the voltage dividing resistors 2, 4,
Due to manufacturing variations such as 5 and pattern layout variations, the reference voltage V1 on the node N1
If you try to rise faster than the output voltage of the operational amplifier 6
Vf does not rise, and the base currents of the transistors 1 and 3 are not supplied. As a result, since the constant currents I1 and I2 do not flow through the emitters of the transistors 1 and 3, the reference voltages V1 and V2 do not rise. As a result, the malfunction that the output voltage Vf of the opape 6 does not rise occurs. I do. As a result, there is a problem that a desired output voltage Vout cannot be obtained.

Further, the above problem also occurs when the operational amplifier 6 is released from the power down mode in which the operational amplifier 6 shifts from the power down state to the power on state.

An object of the present invention is to provide a reference voltage generation circuit that solves the problem of the prior art that a desired output voltage cannot be obtained due to a malfunction when a power supply voltage is turned on or a power down mode is canceled. .

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a reference voltage generation circuit comprising a first voltage supply circuit connected in series between a power supply voltage and a ground via first and second nodes. A reference voltage generator that outputs first and second reference voltages based on the bandgap voltages of the first and second transistors; and a reference voltage generator that is connected to the reference voltage generator. A reference output voltage generator for receiving the first and second reference voltages from the negative-phase input side and the positive-phase input side, differentially amplifying and outputting a reference output voltage, and an output side of the reference output voltage generator A reference output voltage detector for detecting an output state of the reference output voltage generator, and a start-up signal for outputting a start-up signal in response to an output of the reference output voltage detector and a power-down signal. A signal output unit, a current supply connected between the positive-phase input side of the reference output voltage generation unit and the power supply voltage, and supplying a drive current to the positive-phase input side of the reference output voltage generation unit in response to the start-up signal; Unit.

(Operation) According to the present invention, since the reference voltage generation circuit is configured as described above, the reference output voltage detection unit outputs the reference output voltage from the reference output voltage generation unit when the power supply voltage is turned on or when the power down mode is released. Not detected. The start-up signal output unit outputs a start-up signal when the power-down mode is canceled and the reference output voltage generator is in a power-on state. The current supply unit receives the start-up signal and supplies a drive current to the positive-phase input side of the reference output voltage generation unit to forcibly raise the reference output voltage. Therefore, the above problem can be solved.

Embodiment FIG. 1 is a circuit diagram of a reference voltage generation circuit showing an embodiment of the present invention.

This reference voltage generation circuit includes a reference voltage generation section 50 and a start-up section 60.

The reference voltage generator 50 outputs the first and second reference voltages V11 and V12 based on the reference output voltage Vf.
And an operational amplifier 52 that is a reference output voltage generator that differentially amplifies the first and second reference voltages V11 and V12 and outputs a reference output voltage Vf, and multiplies the reference output voltage Vf by a constant to obtain an output voltage Vo.
and an output voltage setting unit 53 that arbitrarily sets ut.

The reference voltage generation unit 51 includes an NPN transistor 51-which is a first transistor having a collector connected to the power supply voltage VDD.
1 and the emitter of the transistor 51-1 is connected to the first node N11. The node N11 has a resistor 51−
2 is connected to the ground GND. The collector and the base of the transistor 51-1 are connected to the collector and the base of an NPN transistor 51-3 as a second transistor, respectively. The resistors 51-4 and 51-5 are connected in series between the emitter of the transistor 51-3 and the ground GND via a second node N12.

The node N12 is connected to the positive-phase input side (+) of the operational amplifier 52, and the node N11 is connected to the negative-phase input side (-). The output side of the operational amplifier 52 is connected to transistors 51-1, 51-
3 and to the output voltage setting unit 53.

The output voltage setting unit 53 has a transistor 51-
It has an operational amplifier 53-1 connected to the base of 1,51-3. The negative-phase input side of the operational amplifier 53-1 is connected to the resistor 53-2
Connected to ground GND via
-3, the output side of the operational amplifier 53-1 and the output voltage Vo
The output terminal 54 for ut output and the start-up unit 60 are commonly connected.

The start-up unit 60 has an inverter 61 that is a reference output voltage detection unit connected to the output side of the operational amplifier 53-1. The output side of the inverter 61 is connected to one input side of a two-input NAND gate 62 which is a start-up signal output section. The other input side of the NAND gate 62 is connected to an input terminal 63 for inputting a power down signal PS.
The output side of the NAND gate 62 is connected to the gate of a P-channel MOS transistor (hereinafter referred to as PMOS) 64 as a current supply unit. The source of the PMOS 64 is connected to the power supply voltage VDD, and the drain is connected to the positive-phase input side of the operational amplifier 52. The input terminal 63 for inputting the power-down signal PS is connected to the op-ape 52.

FIG. 3 is an internal circuit diagram of the operational amplifier 52 in FIG.

The operational amplifier 52 includes a positive-phase input terminal 52-1 and a negative-phase input terminal 52-2, and an N-channel MO used for differential amplification.
S transistor (hereinafter referred to as NMOS) 52-3, 52-4 and P
MOS52-5 and 52-6. Further, NMOSs 57-L, 52-8, 52-9 for constant current means, PMOSs 52-10, 52-11, capacitors 52-12, resistors 52-12a for phase compensation, and PMOSs 52 for the output stage are used.
-13, PMOS 52-14 for power down mode, NMOS 52-1
5, an inverter 52-16 and an output terminal 52-17 are provided.

The operation of the reference voltage generation circuit configured as described above will be described.

When the first reference voltage V11 on the node N11 tries to rise faster than the second reference voltage V12 on the node N12 due to a manufacturing variation or the like when the power supply voltage VDD is turned on or when the power down mode is released, the operational amplifier The output of 52,53-1 is
Do not stand together. Inverter 61 detects that the output of operational amplifier 53-1 has not risen (that is, logical level "0"), and outputs the inverted output "1". NAND gate 62
Receives the output of the inverter 61 and the power-down signal PS “1” in the power-on state, and generates the start-up signal “0”.
Output to PMOS64.

As a result, the PMOS 64 is turned on, and the operational amplifier 52
Supply the drive current to the positive-phase input side. Then, the reference voltage V12 on the positive-phase input side of the operational amplifier 52 rises, and (V12> V1
At the time of 1), the reference output voltage Vf output from the operational amplifier 52 also rises. The rising reference output voltage Vf activates the transistors 51-1 and 51-3, and a current flows through each emitter. Therefore, the operational amplifier 52 rises, and the operational amplifier 53-1 receiving the output of the operational amplifier 52 also rises.

When the operational amplifier 53-1 rises, the output voltage Vout as its output rises. When the output voltage Vout exceeds the threshold value of the inverter 61, the output of the inverter 61 becomes "0" and the output of the NAND gate 62 becomes "1". As a result, the PMOS 64 is turned off, the supply of the drive current to the positive-phase input side of the operational amplifier 52 is stopped, and the reference voltage generator 50 performs the following steady operation.

For example, when the reference output voltage Vf rises due to a change in temperature or the like, the current between the collector and the emitter of the transistors 51-1 and 51-3 changes according to the rise. as a result,
Second reference voltage V12 applied to positive-phase input terminal 52-1
Is determined by the voltage division ratio of the resistors 51-4 and 51-5.
The voltage drops from the first reference voltage V11 applied to the negative-phase input terminal 52-2. As a result, the gate voltage of the NMOS 52-4 becomes NM
It is higher than the gate voltage of OS52-3. Therefore, PM
The gate voltage of OS52-13 rises and the output terminal
The reference output voltage Vf of 52-17 drops. In this way,
It operates so as to output a stable and constant reference output voltage Vf. As a result, a constant output voltage Vout obtained by multiplying the reference output voltage Vf by a constant is output to the output terminal 54 via the output voltage setting unit 53.
Output from

In the power down mode, the NMOSs 52-7, 52-8 and 52-9 as constant current means shown in FIG. 3 are turned off, and the PMOS 52-13 in the output stage is completely turned off. 17 is in a high impedance state.

 This embodiment has the following advantages.

The start-up unit 60 detects that the desired output voltage Vout is not generated when the power supply voltage VDD is turned on or when the power-down mode is released, and performs a start-up operation for forcibly starting the reference voltage generation unit 50. During the normal operation of the voltage generator 50, the startup operation is not performed. Therefore, when the reference voltage generator 50 attempts to malfunction when the power supply voltage VDD is applied or when the power down mode is canceled,
The malfunction can be prevented.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following modifications.

(I) In the above embodiment, the output voltage setting unit 53 is provided,
The output voltage Vout obtained by multiplying the reference output voltage Vf by a constant is output, and the output state of the output voltage Vout is detected by the inverter 61.However, the output voltage setting unit 53 is omitted, and the reference output voltage Vf is directly output. The detection may be performed by the inverter 61.

(II) Although the inverter 61 is used as the reference output voltage detection unit, for example, a NAND gate or a NOR gate may be used.

(III) NAND gate 6 as start-up signal output
Although 2 is used, it is also possible to use, for example, a NOR gate.

(IV) Although the current supply unit is configured by the PMOS 64, it may be configured by an NMOS.

(Effects of the Invention) As described above in detail, according to the present invention, when the power supply voltage is turned on or the power down mode is canceled, it is detected that the reference output voltage is not generated, and the correctness of the reference output voltage generation unit is detected. The drive current is supplied to the phase input side to forcibly raise the reference output voltage.Therefore, when turning on the power supply voltage or canceling the power-down mode, due to manufacturing variations in the LSI or other manufacturing process or variations in the pattern layout, etc. When a circuit attempts to malfunction, the malfunction can be prevented.

Furthermore, the effect of preventing malfunctions can be expected not only when turning on the power supply voltage and when releasing the power down mode, but also against external malfunction factors such as a momentary interruption of the power supply voltage during operation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a reference voltage generating circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional reference voltage generating circuit, and FIG. 3 is an internal circuit diagram of the operational amplifier 52 in FIG. . 51: Reference voltage generator, 52: Reference output voltage generator (operational amplifier), 61: Reference output voltage detector (inverter), 62: Start-up signal output unit (NAND gate), 64: Current supply unit (PMOS), VDD: Power supply voltage, V
11, V12: First and second reference voltages, Vf: Reference output voltage.

Claims (1)

(57) [Claims] A first transistor connected in series between a power supply voltage and a ground via a first node and a second node; and a bandgap voltage of the first and second transistors. A reference voltage generator that outputs first and second reference voltages, and is connected to the reference voltage generator, and takes in the first and second reference voltages from a negative phase input side and a positive phase input side, respectively. A reference output voltage generator that differentially amplifies and outputs a reference output voltage, and a reference output voltage detector that is connected to an output side of the reference output voltage generator and detects an output state of the reference output voltage generator. A start-up signal output unit that outputs a start-up signal in response to an output of the reference output voltage detection unit and a power-down signal, connected between a positive-phase input side of the reference output voltage generation unit and the power supply voltage, A current supply unit for supplying a drive current to a positive-phase input side of the reference output voltage generation unit in response to the start-up signal.