JP2900521B2 - Reference voltage generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generation circuit, and more particularly, to a bandgap reference type reference voltage generation circuit.

[Prior Art] FIG. 5 is a circuit diagram showing a conventional reference voltage generating circuit.

As shown in FIG. 5, a pair of p-type MOS transistors MP ₁ and MP ₂ of the same size have their gates connected to each other.
Its source is connected to the power supply V _DD . On the other hand, pnp transistors QP _1, QP ₂ the emitter area are different from each other (the emitter area; QP _1> QP ₂₎ has a base connected in common to a bias power supply V _B, the collector connected to ground GND. The emitters of the pnp transistors QP ₁ and QP ₂ are connected to the p-type MOS transistor MP via resistors R ₁ , R ₂ and R ₃ , respectively.
It is connected to the drain of the _1, MP _2. Operational amplifier A ₁ is provided between the power supply V _DD and the ground GND, its negative input is connected between the drain of the resistor R ₃ and a transistor MP _2, the positive input resistors R ₁ and R ₂ And its output is fed back to the common gate of the transistors MP ₁ and MP ₂ . The output terminal OUT is connected between the drain of the resistor R ₂ and the transistor MP _1.

In the reference voltage generation circuit configured as described above,
By feeding the output of the operational amplifier A ₁ to the gate of the transistor MP _1, MP _2, the bias power source V _B at stable state
It shows a characteristic that the reference voltage V _REF between the output terminal OUT and the reference voltage V OUT is kept substantially constant with changes in temperature and power supply voltage.
Such characteristics, when a current of equal current to the transistor QP _1, QP _2, the relationship between the emitter-base voltage V _BE2 of the transistor QP ₁ emitter-base voltage V _BE1 and the transistor QP ₂ is V _BE1 > V _BE2 stabilizes. However, in this case, it is difficult for a current equal to the transistors QP ₁ and QP ₂ to flow when the power is turned on. This allows
Current of the transistor QP ₂ is reduced, the positive feedback is applied the negative input of the operational amplifier A ₁ becomes a lower voltage with respect to the positive input, the transistor QP ₂ is hardly current increasingly flows.
Then, the output voltage at the output terminal OUT is fixed at a specific voltage, and the function as the reference voltage generation circuit is not fulfilled. Therefore, a reference voltage generation circuit that has improved such a defect has been proposed.

FIG. 6 shows a conventional reference voltage generator (reference voltage generator 11 shown by a broken line) to which a start-up circuit 2 is added.

The start-up circuit 2 is configured as follows. The sources of the p-type MOS transistors MP ₃ and MP ₄ are commonly connected to the sources of the transistors MP ₁ and MP ₂ , and the drains are connected to the emitters of the transistors QP ₁ and QP ₂ , respectively. The gates of the transistors MP ₃ and MP ₄ are commonly connected to a bias power supply _VST , and a constant bias voltage is applied.

The reference voltage generator 11, the arrangement of the resistors R ₁ to R ₃ is different from FIG. 5.

In the reference voltage generation circuit configured as described above,
Before the feedback of the operational amplifier A ₁ is applied when a voltage is turned on, by supplying substantially equal constant current from the start-up circuit 2 to the transistor QP _1, QP _2, are set to be V _BE1> V _BE2. By reducing the constant current supplied from the start-up circuit 2 to a certain extent, the stability of the reference voltage V _REF at the time of turning on the power is good, and the stability of the reference voltage V _REF with respect to changes in temperature and power supply voltage is excellent. A reference voltage generation circuit is configured.

[Problems to be Solved by the Invention] However, in the above-described conventional reference voltage generating circuit, the startup circuit 2 added to enhance the stability at the time of turning on the power supply always keeps the current flowing even after the stable state. , There is a problem that power consumption increases. Startup circuit 2
However, there is a problem that the variation of the elements of the transistors MP ₃ and MP ₄ constituting the device directly affects the variation of the voltage value of the reference voltage V _{REF at} the output terminal OUT.

The present invention has been made in view of such a problem, and can improve the stability of a reference voltage at the time of power-on, and can reduce power consumption.
It is an object of the present invention to provide a reference voltage generation circuit that can reduce variations in reference voltage.

[Means for Solving the Problems] A reference voltage generating circuit according to the present invention comprises a pair of bipolar transistors having different emitter areas, a resistor for converting the emitter current of each bipolar transistor into a voltage, and a resistor for converting the voltage. A pulse signal is output at power-on in a reference voltage generating circuit having an operational amplifier for comparison with each other and a pair of MOS transistors for feeding back the output of the operational amplifier to its gate and supplying a constant current to each of the bipolar transistors. A power-on reset circuit,
A start-up circuit for supplying a constant current to an emitter of each of the bipolar transistors in response to the pulse signal of the power-on reset circuit.

[Operation] In the present invention, a current equal to a pair of bipolar transistors having mutually different emitter areas flows, and a pair of MOs supplying a constant current to these bipolar transistors is provided.
By feeding back the output of the operational amplifier to the gate of the S transistor, the reference voltage generated between the bias power supply of the bipolar transistor and the drain of the MOS transistor is substantially unaffected by changes in temperature and power supply voltage. Is kept. In this case, since the output of the operational amplifier is not fed back when the power is turned on, the same current hardly flows through the pair of bipolar transistors. The start-up circuit responds to the pulse signal output from the power-on reset circuit when the power is turned on.
A constant current is supplied to a pair of bipolar transistors. As a result, the stability of the reference voltage when the power is turned on can be improved.

According to the present invention, the start-up circuit operates by the pulse signal supplied from the power-on reset circuit only when the power is turned on.
The power-on reset circuit and the start-up circuit can be turned off. Therefore, power consumption can be significantly reduced. Further, even if there are variations in the elements of the transistors constituting the power-on reset circuit and the startup circuit, the variations do not directly affect the reference voltage in a stable state.

Example Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a reference voltage generating circuit according to a first embodiment of the present invention.

The reference voltage generator 10 is configured as follows.
Npn transistors QN ₁ and QN with different emitter areas
₂ (emitter area; QN _1> QN ₂₎ has a base connected in common to a bias power supply V _B, its collector connected to the power supply V _DD. On the other hand, a pair of n-type MOS transistors MN ₁ and MN ₂
Has its gate connected to each other and its source grounded GN
Connected to D. Then, the n-type MOS transistors MN ₁ ,
The drain of MN ₂ is connected to np via resistors R ₁ , R ₂ and resistor R _{3 respectively.}
It is connected to the emitters of n transistors QN ₁ and QN ₂ . Operational amplifier A ₁ is provided between the power supply V _DD and the ground GND, its negative input is connected between the resistors R ₁ and R _2, the emitter its positive input of the resistor R ₃ and the transistor QN ₂ And its output is fed back to the common gate of the transistors MN ₁ and MN ₂ . The output terminal OUT is connected between the drain of the resistor R ₁ and the transistor MN _1. In this way, by applying a negative feedback to the common gate of the transistors MN _1, MN _2, a voltage value taken out from an output terminal OUT connected to the drain of the transistor MN ₁ (or MN ₂₎ is, the transistor QN _1, QN It is configured to be constant with respect to the base applied voltage of ₂ .

The start-up circuit 2 is a power-on reset circuit 1
And its two output terminals are respectively connected to the emitters of the transistors QN ₁ and QN ₂ . The power-on reset circuit 1 generates one pulse signal only after the power is turned on, and holds the standby state when the power is turned on. The start-up circuit 2 operates according to a pulse signal input from the power-on reset circuit 1 when the power is turned on, and supplies a current substantially equal to the transistors QN ₁ and QN ₂ . Therefore, the reference voltage generator 10 starts operating with the constant current supplied from the start-up circuit 2, and reaches a stable state.

According to this embodiment, the start-up circuit 2 operates by the pulse signal supplied from the power-on reset circuit 1 only when the power is turned on. Therefore, in a stable state after the power is turned on, the power-on reset circuit 1 and the start-up circuit 2 are operated. Can be in standby state. Therefore,
Power consumption can be remarkably reduced, and in particular, when a CMOS circuit is used, the current consumption can be reduced to about the same level as the leak current. In addition, even if there are variations in the elements of the transistors constituting the power-on reset circuit 1 and the startup circuit 2, in a stable state, the variations do not affect the reference voltage V at the output terminal OUT.
It does not directly affect _REF .

FIG. 2 is a circuit diagram showing a reference voltage generating circuit according to a second embodiment of the present invention. In the present embodiment, a power-on reset circuit is added to the conventional circuit shown in FIG. 6, and the start-up circuit is controlled by the power-on reset circuit. Detailed description is omitted.

This embodiment is different from the first embodiment in that the npn transistor Q
Instead of N ₁ , QN ₂ and n-type MOS transistors MN ₁ , MN ₂
pnp transistors QP ₁ and QP ₂ and p-type MOS transistors MP ₁ and M
Using the P _2, it constitutes a reference voltage generating unit 11 by replacing the relationship between the power supply V _DD and the ground GND. For this reason,
The polarity of the output terminal OUT can be reversed from that of the first embodiment. In this case, the same effects as in the first embodiment can be obtained by reversing the polarities of the power-on reset circuit 1 and the start-up circuit 2 in the first embodiment.

FIG. 3 is a circuit diagram showing a reference voltage generating circuit according to a third embodiment of the present invention. This embodiment is a further embodiment of the second embodiment shown in FIG.

The reference voltage generator 12 is a reference voltage generator in FIG.
In addition to 11, p-type MOS transistors MP ₅ and MP ₆ and diode
QP ₃ and QP ₄ are used. The transistors MP ₅ and MP ₆ have their gates connected to each other, their sources connected to the power supply V _DD , and their drains connected to the ground GND via the diodes QP ₃ and QP ₄ , respectively. Also, the transistors MP ₁ and M
In the same manner as P _2, the output of the operational amplifier A ₁ to the common gate of the transistor MP _5, MP ₆ is is fed back. The bases of the transistors QP ₁ and QP ₂ are separated from each other, and are connected to the anodes of the diodes QP ₃ and QP ₄ respectively.
As described above, since the bias voltages of the transistors QP ₁ and QP ₂ are supplied from the power supply V _DD according to the feedback output of the operational amplifier A ₁ , the reference voltage V _{REF at the} output terminal OUT has a predetermined voltage value with respect to the ground GND. it is possible to occur, it is possible to maintain a stable operation of the operational amplifier a ₁ by increasing the voltage value of the positive and negative inputs of the operational amplifier a _1.

On the other hand, the startup circuit 2 is configured as follows. The gates of the p-type MOS transistors MP ₃ and MP ₄ are connected to each other, and the sources are connected to the power supply V _DD .
The drains are connected to the emitters of the transistors QP ₁ and QP ₂ respectively. The p-type MOS transistors MP ₇ and MP ₈ have their gates connected to each other, their sources connected to the power supply _VDD , and their drains connected to the anodes of the diodes QP ₃ and QP ₄ , respectively. Also, transistors MP ₃ , MP ₄ , MP ₇ ,
The output signal of the power-on reset circuit 1 is supplied to the gate of each of the MPs ₈ , and the MP ₈ is controlled by turning on or off this signal.

The power-on reset circuit 1 is configured as follows. Two types of n-type M pulled up by power supply V _DD
The OS transistors MN ₅ and MN ₄ are sequentially cascaded to the ground GND. Capacitance C ₂ is connected between the transistor MN _4, MN ₅ of drain and the ground GND. Also transistors
Capacitance C ₁ is connected between the source and the power supply V _DD of MN _4. n-type MOS transistor MN ₃ and p-type MOS transistor M
P ₉ is a complementary pair connection between the power supply V _DD and the ground GND,
Construct an inverter circuit. This transistor MN ₃ , MP ₉
, Its gate is commonly connected to the source of the transistor MN _4, and supplies an output signal to the start-up circuit 2 from between both drain.

According to this embodiment, in the power-on reset circuit 1, the electric charge charged in the instant capacity C ₁ when the power is turned on is gradually discharged by the transistor MN _4, MN ₅ and the capacitor C _2.
First, at the time of charging, the inverter circuit composed of the transistors MN ₃ and MP ₉ lowers its output signal to a low level because its gate input exceeds the threshold voltage. Therefore, the drain current of the transistors MP ₃ , MP ₄ , MP ₇ , and MP ₈ starts to flow, and supplies a constant current to the reference voltage generator 12. Next, at the time of discharging, the inverter circuit composed of the transistors MN ₃ and MP ₉ raises its output signal to a high level because its gate input crosses the threshold voltage again. For this reason, the transistors MP ₃ , MP ₄ , MP ₇ , and MP ₈
The state becomes the FF state, and the supply of the constant current to the reference voltage generator 12 is stopped. In this way, when the power is turned on, a constant current is supplied from the startup circuit 2 controlled by the power-on reset circuit 1 to the reference voltage generator 12. In a stable state thereafter, the power-on reset circuit 1 and the start-up circuit 2 enter a standby state.

FIG. 4 is a signal waveform diagram of the reference voltage generating circuit shown in FIG. Note that points a and b indicate arbitrary points at the input terminal and output terminal of the inverter circuit (transistors MN ₃ and MP ₉ ), respectively.

As shown in Figure 4, when turning on the power (V _DD), a point after reaching a high level by the charge of the capacitor C _1, gradually decreases to the low level is discharged. At this time, the point b (the output point of the power-on reset circuit 1) becomes a low level according to the threshold voltage of the inverter circuit. Therefore, during this period, the transistors MP ₃ ,
MP ₄ , MP ₇ , MP ₈ drain current flows, and the reference voltage generator 12
Since the feedback operational amplifier A ₁ in is negative feedback,
The output waveform of the output terminal OUT is easily stabilized at the reference voltage _VREF .

[Effects of the Invention] As described above, according to the present invention, a pulse signal is output from a power-on reset circuit at the time of power-on, and a start-up circuit is operated in accordance with the pulse signal while the reference voltage at the time of power-on is changed. Stability can be improved. In a stable state after power is turned on, the power-on reset circuit and the start-up circuit are turned off, so that power consumption can be significantly reduced and variations in elements of the power-on reset circuit and the start-up circuit are reduced. The variation in the reference voltage can be reduced without affecting the reference voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a reference voltage generating circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a reference voltage generating circuit according to a second embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram showing a reference voltage generating circuit according to a third embodiment of the present invention, FIG. 4 is a signal waveform diagram thereof, FIG. 5 is a circuit diagram showing a conventional reference voltage generating circuit, and FIG. FIG. 3 is a circuit diagram showing a reference voltage generation circuit of FIG. A ₁ : operational amplifier, MN _{1 to} MN ₅ ; n-type MOS transistor, MP _{1 to} M
P ₉ ; p-type MOS transistor, QN ₁ , QN ₂ ; npn transistor, Q
P _1, QP _2; pnp _{transistors, R 1, R 2, R} 3; resistance, C _1, C _2; capacity, QP _3, QP _4; diode, V _DD; supply, V _B, V _ST; bias power supply, GND; ground, OUT; output terminal, 1; power-on reset circuit, 2: start-up circuit, 10, 11, 12; reference voltage generator

Claims (1)

(57) [Claims] 1. A pair of bipolar transistors having mutually different emitter areas, a resistor for converting the emitter current of each bipolar transistor into a voltage, an operational amplifier for comparing the voltages with each other, and an output of the operational amplifier at its gate. A power-on reset circuit for outputting a pulse signal when power is turned on, and a power-on reset circuit for outputting a pulse signal when power is turned on. A start-up circuit for supplying a constant current to the emitter of each of the bipolar transistors in response to a signal.