CN115454200B - Voltage generating circuit, leakage current compensation method and chip - Google Patents

Voltage generating circuit, leakage current compensation method and chip Download PDF

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Publication number
CN115454200B
CN115454200B CN202211185442.9A CN202211185442A CN115454200B CN 115454200 B CN115454200 B CN 115454200B CN 202211185442 A CN202211185442 A CN 202211185442A CN 115454200 B CN115454200 B CN 115454200B
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unit
triodes
triode
collector
mos transistor
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CN115454200A (en
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张三锋
张睿
潘翔鑫
杨雪
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3Peak Inc
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3Peak Inc
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Priority to PCT/CN2023/119997 priority patent/WO2024067286A1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

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  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a voltage generating circuit, a leakage current compensation method and a chip, wherein the voltage generating circuit comprises: a bandgap collector cell and a compensation cell. The band-gap collector unit comprises a first triode and N second triodes. The compensation unit includes: a first copying unit, a sampling unit and a second copying unit. The voltage generating circuit, the leakage current compensating method and the chip of the invention output proportional replica voltage by replicating the voltage of the collector electrode terminal of the corresponding triode through the first replication unit, acquire sampling current proportional to the leakage current of the parasitic diode of the corresponding triode based on the replica voltage through the sampling unit, and copy the sampling current into compensating current proportionally through the second replication unit and convey the compensating current to the collector electrode of the corresponding triode to compensate the leakage current of the parasitic diode of the corresponding triode.

Description

Voltage generating circuit, leakage current compensation method and chip
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a voltage generating circuit, a leakage current compensation method and a chip.
Background
Reference voltage generation circuits are basic blocks within modern integrated circuits that provide reference voltages for other circuits. The temperature insensitivity characteristic is usually realized by adopting the BJT device, however, the leakage current of the parasitic PN junction of the BJT device in a high-temperature environment can be increased, so that the reference voltage is changed along with the temperature, and the phenomenon is particularly obvious in a low-power consumption reference voltage generating circuit.
The simplest existing solution is to increase the current of the BJT, but the current is required to be far greater than the leakage current, so that the overall power consumption is larger. Another solution is to use a PNP transistor, but the current amplifying capability of the PNP transistor is weak, and the effect of the base current on the output voltage cannot be ignored.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a voltage generation circuit, a leakage current compensation method and a chip, which can compensate leakage current generated by parasitic PN junction of an NPN transistor in a high-temperature environment, and prevent reference voltage deviation caused by reverse saturation current leakage of a collector parasitic diode of the NPN transistor in the high-temperature environment, so that abnormal function and failure of the chip in the high-temperature environment can be caused.
To achieve the above object, an embodiment of the present invention provides a voltage generating circuit including: a bandgap collector cell and a compensation cell.
The band gap collector unit comprises a first triode and N second triodes, wherein the base electrode of the first triode is connected with the collector electrode, the base electrode and the collector electrode of the N second triodes are connected, the emitter electrode of the first triode is connected with the emitter electrodes of the N second triodes and is simultaneously connected with the ground, and N is more than or equal to 1;
The compensation unit includes: a first copying unit, a sampling unit and a second copying unit.
The first copying unit is connected with the collector electrodes of the first triode or the N second triodes to output copying voltage proportional to the voltage of the collector terminals of the first triode or the N second triodes; the sampling unit is connected with the first copying unit and obtains sampling current proportional to leakage current of parasitic diodes of the first triode or the N second triodes based on the copying voltage; the second copying unit is connected with the first copying unit, the collectors of the first triodes and the collectors of the N second triodes, the sampling current is transmitted to the second copying unit through the first copying unit, and the second copying unit is used for copying the sampling current into compensation current in proportion and transmitting the compensation current to the collectors of the first triodes and the N second triodes.
In one or more embodiments of the present invention, the second replica unit includes a current mirror circuit connected to the first replica unit, the current mirror circuit being simultaneously connected to collectors of the first transistor and the N second transistors to proportionally replicate the sampling current into corresponding compensation currents and to feed the corresponding compensation currents to the collectors of the first transistor and the N second transistors to compensate for leakage currents of parasitic diodes of the first transistor and the N second transistors.
The invention also discloses a voltage generating circuit, which comprises:
the band gap collector unit comprises a first triode and N second triodes, wherein the base electrode of the first triode is connected with the collector electrode, the base electrode and the collector electrode of the N second triodes are connected, the emitter electrode of the first triode is connected with the emitter electrodes of the N second triodes and is simultaneously connected with the ground, and N is more than or equal to 1; and
the compensation unit is connected with the collector electrodes of the first triode and the N second triodes respectively, and is used for compensating leakage currents of parasitic diodes of the first triode and the N second triodes respectively, and comprises:
the first copying unit is respectively connected with the collectors of the first triode and the N second triodes to respectively output copying voltages which are proportional to the voltages of the collector terminals of the corresponding triodes;
sampling units respectively connected with the first copying units, wherein each sampling unit obtains sampling current proportional to leakage current of a parasitic diode of a corresponding triode based on corresponding copying voltage;
and the second copying units are respectively connected with the first copying units and the collector electrodes of the triodes, the sampling current is transmitted to the corresponding second copying units through the first copying units, and the second copying units are used for copying the sampling current into compensation current in proportion and transmitting the compensation current to the collector electrodes of the corresponding triodes.
In one or more embodiments of the present invention, the first replication unit includes a second amplifier and a second MOS transistor, a first input terminal of the second amplifier is connected to a collector of a corresponding triode, a second input terminal of the second amplifier is connected to the sampling unit, a gate of the second MOS transistor is connected to an output terminal of the second amplifier, a source of the second MOS transistor is connected to the sampling unit, and a drain of the second MOS transistor is connected to the second replication unit.
In one or more embodiments of the present invention, the first replication unit includes a second MOS transistor, where the second MOS transistor is a active-MOS transistor, a gate of the second MOS transistor is connected to a collector of a corresponding triode, a source of the second MOS transistor is connected to the sampling unit, and a drain of the second MOS transistor is connected to the second replication unit.
In one or more embodiments of the present invention, the sampling unit includes a third triode having a base, an emitter, and a collector connected to the first replica unit.
In one or more embodiments of the present invention, the second replication unit includes current mirror circuits, each of which replicates each sampling current to each compensation current in proportion and transmits the compensation current to the collector of the corresponding transistor to compensate for leakage current of the parasitic diode of the corresponding transistor.
In one or more embodiments of the invention, the current mirror circuit is a cascades current mirror circuit.
In one or more embodiments of the present invention, the first replication unit includes a second amplifier and a second MOS transistor, where a first input end of the second amplifier is connected to a collector of a corresponding triode, a second input end of the second amplifier is connected to the sampling unit, a gate of the second MOS transistor is connected to an output end of the second amplifier, a source of the second MOS transistor is connected to the sampling unit, and a drain of the second MOS transistor is connected to the second replication unit; or alternatively
The first copying unit comprises a second MOS tube, the second MOS tube is a native-MOS tube, the grid electrode of the second MOS tube is connected with the collector electrode of the corresponding triode, the source electrode of the second MOS tube is connected with the sampling unit, and the drain electrode of the second MOS tube is connected with the second copying unit;
the first replication unit further comprises a capacitor, a first end of the capacitor is connected with the grid electrode of the second MOS tube, and a second end of the capacitor is connected with the ground.
In one or more embodiments of the invention, the capacitance is a MOS capacitance, a MOM capacitance, or a MIM capacitance.
In one or more embodiments of the present invention, the first replication unit includes a second amplifier and a second MOS transistor, where a first input end of the second amplifier is connected to a collector of a corresponding triode, a second input end of the second amplifier is connected to the sampling unit, a gate of the second MOS transistor is connected to an output end of the second amplifier, a source of the second MOS transistor is connected to the sampling unit, and a drain of the second MOS transistor is connected to the second replication unit; or alternatively
The first copying unit comprises a second MOS tube, the second MOS tube is a native-MOS tube, the grid electrode of the second MOS tube is connected with the collector electrode of the corresponding triode, the source electrode of the second MOS tube is connected with the sampling unit, and the drain electrode of the second MOS tube is connected with the second copying unit;
the first copying unit further comprises a diode, the cathode of the diode is connected with the grid electrode of the second MOS tube, and the anode of the diode is connected with the source electrode of the second MOS tube.
In one or more embodiments of the present invention, the diode is a parasitic diode of the second MOS transistor.
In one or more embodiments of the present invention, the voltage generating circuit further includes a first amplifier, a first resistor, a second resistor, a third resistor, and a current source, wherein a first input terminal of the first amplifier is connected to a collector of the first triode and a first terminal of the first resistor, a second input terminal of the first amplifier is connected to a first terminal of the third resistor and a first terminal of the second resistor, a second terminal of the third resistor is connected to collectors of the N second triodes, a second terminal of the first resistor is connected to a second terminal of the second resistor, a control terminal of the current source is connected to an output terminal of the first amplifier, a first terminal of the current source is connected to a power supply voltage, and a second terminal of the current source is connected to a second terminal of the second resistor.
In one or more embodiments of the present invention, the current source includes a first MOS transistor, a gate of the first MOS transistor is connected to an output terminal of the first amplifier, a source of the first MOS transistor is connected to a power supply voltage, and a drain of the first MOS transistor is connected to a second terminal of the second resistor.
The invention also discloses a leakage current compensation method of the voltage generation circuit, the voltage generation circuit comprises a band gap collector unit, the band gap collector unit comprises a first triode and N second triodes, the base electrode of the first triode is connected with a collector electrode, the base electrode and the collector electrode of the N second triodes are connected, the emitter electrode of the first triode is connected with the emitter electrodes of the N second triodes and is simultaneously connected with the ground, and N is more than or equal to 1;
the leakage current compensation method comprises the following steps:
the voltages of the collector electrode terminals of the first triode and/or the N second triodes are duplicated in proportion to obtain corresponding duplicated voltages;
obtaining sampling currents which are proportional to the leakage currents of the parasitic diodes of the first triode and/or the leakage currents of the parasitic diodes of the N second triodes based on the corresponding replica voltages;
and copying the corresponding sampling current in proportion to form a compensation current, and conveying the corresponding compensation current to the collector terminals of the first triode and the N second triodes.
The invention also discloses a chip comprising the voltage generating circuit.
Compared with the prior art, according to the voltage generation circuit, the leakage current compensation method and the chip, the voltage of the collector terminal of the corresponding triode is copied by the first copying unit to output the proportional copy voltage, the sampling current proportional to the leakage current of the parasitic diode of the corresponding triode is obtained by the sampling unit based on the copy voltage, and the sampling current is copied into the compensation current in proportion by the second copying unit and is transmitted to the collector of the corresponding triode to compensate the leakage current of the parasitic diode of the corresponding triode.
The voltage generating circuit, the leakage current compensation method and the chip can maintain the stability of the reference voltage in a wider temperature range, and avoid the chip function failure caused by the leakage of the parasitic diode, such as the failure of the over-temperature protection circuit caused by the failure of the reference voltage, so as to cause the chip damage. In addition, the influence of electric leakage on the reference voltage is reduced, so that the current of each branch circuit can be further reduced, and the circuit design with lower power consumption can be realized.
Drawings
Fig. 1 is a schematic circuit diagram of a voltage generation circuit according to a first embodiment of the present invention.
Fig. 2 is a flowchart of a leakage current compensation method of a voltage generation circuit according to a first embodiment of the invention.
Fig. 3 is a schematic circuit diagram of a voltage generating circuit according to a second embodiment of the present invention.
Fig. 4 is a circuit schematic of a voltage generation circuit according to a third embodiment of the present invention.
FIG. 5 is a flow chart of a leakage current compensation method of a voltage generation circuit according to a third embodiment of the invention
Detailed Description
Specific embodiments of the invention will be described in detail below with reference to the drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
It should be appreciated that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and/or elements capable of storing instructions for execution by the programmable circuits. When an element or circuit is referred to as being "connected to" or "connected to" another element, or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.
The invention will be further described with reference to the drawings and examples.
Example 1
As shown in fig. 1, a voltage generating circuit includes: the circuit comprises a first amplifier OP1, a first resistor R1, a second resistor R2, a third resistor R3, a current source, a band-gap collector unit and a compensation unit.
The band gap collector unit comprises a first triode Q1 and N second triodes Q2, and the first triode Q1 and the N second triodes Q2 are NPN triodes. The base electrode and the collector electrode of the first triode Q1 are connected, the N second triodes Q2 are connected in parallel, the base electrodes and the collector electrodes of the N second triodes Q2 are connected, the emitter electrode of the first triode Q1 is connected with the emitter electrode of the N second triodes Q2 and is connected with the ground at the same time, and N is more than or equal to 1.
The first input terminal of the first amplifier OP1 is connected to the collector of the first triode Q1 and the first terminal of the first resistor R1, and the second input terminal of the first amplifier OP1 is connected to the first terminal of the third resistor R3 and the first terminal of the second resistor R2. In this embodiment, the first input terminal of the first amplifier OP1 is a positive input terminal, the second input terminal of the first amplifier OP1 is a negative input terminal, and in other embodiments, the first input terminal of the first amplifier OP1 is a negative input terminal, and the second input terminal of the first amplifier OP1 is a positive input terminal. The second end of the third resistor R3 is connected with the collectors of the N second triodes Q2, and the second end of the first resistor R1 is connected with the second end of the second resistor R2. The control end of the current source is connected with the output end of the first amplifier OP1, the first end of the current source is connected with the power supply voltage, and the second end of the current source is connected with the second end of the second resistor R2.
In this embodiment, the current source includes a first MOS transistor MP1, in this embodiment, the first MOS transistor MP1 is a P-channel MOS transistor, and in other embodiments, the first MOS transistor MP1 may also be an N-channel MOS transistor. The grid of the first MOS tube MP1 is connected with the output end of the first amplifier OP1, the source electrode of the first MOS tube MP1 is connected with the power supply voltage, and the drain electrode of the first MOS tube MP1 is connected with the second end of the second resistor R2. In other embodiments, the current source may also adopt a cascades circuit structure or a simple current source.
In this embodiment, the compensation unit can compensate the leakage currents of the parasitic diode D1 of the first transistor Q1 and the parasitic diodes D2 of the N second transistors Q2 at the same time.
As shown in fig. 1, the compensation unit includes: a first copying unit 10, a sampling unit 20 and a second copying unit 30.
Specifically, the first replica unit 10 is connected to the collectors of the N second transistors Q2 to output a replica voltage proportional to the voltages of the collector terminals of the N second transistors Q2. In other embodiments, the first replica unit 10 may also be connected to the collector of the first transistor Q1 to output a replica voltage proportional to the voltage of the collector terminal of the first transistor Q1.
The first replica unit 10 includes a second amplifier OP2 and a second MOS transistor MN1. In this embodiment, the second MOS transistor MN1 is an N-channel MOS transistor, and in other embodiments, the second MOS transistor MN1 may also be a P-channel MOS transistor. The first input terminal of the second amplifier OP2 is connected to the collectors of the N second transistors Q2, and the second input terminal of the second amplifier OP2 is connected to the sampling unit 20. In this embodiment, the first input terminal of the second amplifier OP2 is a positive input terminal, the second input terminal of the second amplifier OP2 is a negative input terminal, and in other embodiments, the first input terminal of the second amplifier OP2 is a negative input terminal, and the second input terminal of the second amplifier OP2 is a positive input terminal. The gate of the second MOS transistor MN1 is connected to the output end of the second amplifier OP2, the source of the second MOS transistor MN1 is connected to the sampling unit 20, and the drain of the second MOS transistor MN1 is connected to the second copying unit 30.
In this embodiment, the voltage of the collector terminals of the N second transistors Q2 is copied from the first input terminal of the second amplifier OP2 to the second input terminal of the second amplifier OP2 through the second amplifier OP2, and at the same time, the conduction of the second MOS transistor MN1 is controlled through the second amplifier OP 2.
As shown in fig. 1, the first replica cell 10 further includes a capacitor C1 and a diode Dp. The first end of the capacitor C1 is connected to the output terminal of the second amplifier OP2, and the second end of the capacitor C1 is connected to ground. The capacitor C1 may be a MOS capacitor, a MOM capacitor, or a MIM capacitor. The cathode of the diode Dp is connected to the gate of the second MOS transistor MN1, and the anode of the diode Dp is connected to the source of the second MOS transistor MN1. In other embodiments, the diode Dp may be a parasitic diode of a certain MOS transistor.
In a low temperature environment, the compensation unit approximates an open circuit. In a high temperature environment, a compensation loop of the compensation unit is established. The capacitor C1 is used to maintain the stability of the compensation loop during the process from the low temperature environment to the high temperature environment. The diode Dp serves to prevent uncertainty of voltage due to high resistance generated from the parasitic diode D3 node of the sampling unit 20 in low temperature and normal temperature environments.
In other embodiments, the second amplifier OP2 may not be disposed in the first replication unit 10, but the second MOS transistor MN1 needs to be a active-MOS transistor. At this time, the gate of the second MOS transistor MN1 is connected to the collectors of the N second transistors Q2, the source of the second MOS transistor MN1 is connected to the sampling unit 20, and the drain of the second MOS transistor MN1 is connected to the second copying unit 30. Because the threshold of the active-MOS transistor is very low and normally open, the voltage on the gate of the second MOS transistor MN1 can be copied to the source of the second MOS transistor MN 1.
In the present embodiment, the sampling unit 20 is connected to the first replica unit 10, and the sampling unit 20 obtains a sampling current proportional to the leakage currents of the parasitic diodes of the N second transistors Q2 based on the replica voltage.
As shown in fig. 1, the sampling unit 20 includes a third transistor Q3 that is arranged in a floating (i.e., not grounded) state, and the third transistor Q3 is an NPN transistor. The base and emitter of the third triode Q3 are connected to the collector and to the second input terminal of the second amplifier OP2 and to the source of the second MOS transistor MN 1. The parasitic diode D3 of the third transistor Q3 generates a leakage current (i.e., the above-mentioned sampling current) through the replica voltage, and the leakage current of the parasitic diode D3 of the third transistor Q3 is transmitted to the second replica unit 30 through the second MOS transistor MN 1. In this embodiment, the area ratio of the third transistor Q3 to the N second transistors Q2 is 1: n.
In this embodiment, the second replication unit 30 is connected to the first replication unit 10, the collector of the first transistor Q1 and the collectors of the N second transistors Q2, and the sampling current is delivered to the second replication unit 30 through the first replication unit 10, and the second replication unit 30 is configured to replicate the sampling current into the compensation current in proportion and deliver the compensation current to the collectors of the first transistor Q1 and the N second transistors Q2.
As shown in fig. 1, the second replica unit 30 includes a current mirror circuit. The current mirror circuit is connected with the first replication unit 10, and is simultaneously connected with the collectors of the first triode Q1 and the N second triodes Q2 to output corresponding compensation currents in proportion and convey the compensation currents to the collectors of the first triode Q1 and the N second triodes Q2.
Specifically, the current mirror circuit includes a third MOS transistor MP2, a fourth MOS transistor MP3, and a fifth MOS transistor MP4. In the present embodiment, since the leakage currents of the parasitic diodes of the first transistor Q1 and the N second transistors Q2 need to be compensated, two MOS transistors are required. In other embodiments, the number of MOS transistors in the current mirror circuit may be increased or decreased as desired.
The third MOS tube MP2, the fourth MOS tube MP3 and the fifth MOS tube MP4 are connected in a common gate way, the sources of the third MOS tube MP2, the fourth MOS tube MP3 and the fifth MOS tube MP4 are connected with a power supply voltage, and the drain electrode and the grid electrode of the third MOS tube MP2 are connected and connected with the second MOS tube MN 1. The drain electrode of the fourth MOS tube MP3 is connected with the collector electrodes of the N second triodes Q2, and the drain electrode of the fifth MOS tube MP4 is connected with the collector electrodes of the first triodes Q1. In this embodiment, the third MOS transistor MP2, the fourth MOS transistor MP3, and the fifth MOS transistor MP4 are P-channel MOS transistors, and in other embodiments, the third MOS transistor MP2, the fourth MOS transistor MP3, and the fifth MOS transistor MP4 may be N-channel MOS transistors.
In the present embodiment, the ratio of the area of the third transistor Q3 to the area of the N second transistors Q2 is 1: n, the ratio of the area of the third MOS tube MP2 to the area of the fourth MOS tube MP3 is 1: the areas of the N second triodes Q2 are equal to the area of the fourth MOS transistor MP3, so that the leakage current of the parasitic diode D3 of the third triode Q3 can be amplified N times by the fourth MOS transistor MP3 and then delivered to the collector electrodes of the N second triodes Q2, so as to compensate the leakage current of the parasitic diode D2 of the N second triodes Q2, and the current flowing through the third resistor R3 can all flow into the second triodes Q2.
Similarly, the ratio of the area of the fifth MOS transistor MP4 to the area of the third MOS transistor MP2 is 1:1, so that the drain current of the parasitic diode D3 of the third transistor Q3 is equally proportionally transferred to the collector of the first transistor Q1 through the fifth MOS transistor MP4 to compensate the drain current of the parasitic diode D1 of the first transistor Q1.
In other embodiments, the number of parallel third transistors Q3 or the area of the third transistors Q3 may be changed, so that the leakage current of the parasitic diode D3 of the third transistor Q3 is equal to the leakage current of the parasitic diode D2 of the N second transistors Q2, and the ratio of the area of the corresponding third MOS transistor MP2 to the area of the fourth MOS transistor MP3 may be set as N: n, the ratio of the area of the third MOS transistor MP2 to the area of the fifth MOS transistor MP4 is set to n:1. if the first copying unit 10 is connected to the collector of the first triode Q1, the compensation principle is similar, and only the area of the third MOS transistor MP2, the area of the fourth MOS transistor MP3 and the area of the fifth MOS transistor MP4 need to be adjusted.
As shown in fig. 2, the present embodiment further discloses a leakage current compensation method of the voltage generating circuit, including:
s1, proportionally duplicating the voltages of the collector electrode terminals of a first triode Q1 or N second triodes Q2 to obtain corresponding duplicated voltages; in this embodiment, the voltages at the collector terminals of the N second transistors Q2 are preferably duplicated to improve the compensation accuracy.
S2, obtaining sampling currents which are proportional to the leakage currents of the parasitic diodes D1 of the first triodes Q1 or the leakage currents of the parasitic diodes D2 of the N second triodes Q2 based on the corresponding replica voltages; in this embodiment, a sampling current corresponding to the leakage current of the parasitic diode D2 of the N second transistors Q2 is obtained, the magnitude of the sampling current is one-nth times the leakage current of the parasitic diode D2 of the N second transistors Q2, and the magnitude of the sampling current is equal to the leakage current of the parasitic diode D1 of the first transistor Q1.
S3, copying corresponding sampling currents in proportion to form compensation currents, and conveying the corresponding compensation currents to the collector electrode ends of the first triode Q1 and the N second triodes Q2; in the present embodiment, the sampling current is equally proportional to the leakage current of the parasitic diode D1 of the first transistor Q1 by amplifying the sampling current N times to compensate the leakage current of the parasitic diode D2 of the N second transistors Q2.
The embodiment also discloses a chip comprising the voltage generating circuit.
Example 2
As shown in fig. 3, the present embodiment differs from embodiment 1 in that the second replica unit 30 in the present embodiment includes a current mirror circuit, which is a cascades current mirror circuit. The cascades current mirror circuit is connected with the first replication unit 10, and the cascades current mirror circuit is simultaneously connected with the collectors of the first triode Q1 and the N second triodes Q2 to output corresponding compensation currents to the collectors of the first triode Q1 and the N second triodes Q2 in proportion.
Specifically, the cascades current mirror circuit comprises a third MOS tube MP2, a sixth MOS tube MPC2, a biasing unit, a fourth MOS tube MP3, a seventh MOS tube MPC3, a fifth MOS tube MP4 and an eighth MOS tube MPC4.
The third MOS tube MP2, the fourth MOS tube MP3 and the fifth MOS tube MP4 are connected in a common gate mode, and the sixth MOS tube MPC2, the seventh MOS tube MPC3 and the eighth MOS tube MPC4 are connected in a common gate mode. The drain electrode of the third MOS tube MP2 is connected with the source electrode of the sixth MOS tube MPC2, the drain electrode of the fourth MOS tube MP3 is connected with the source electrode of the seventh MOS tube MPC3, and the drain electrode of the fifth MOS tube MP4 is connected with the source electrode of the eighth MOS tube MPC4. The sources of the third MOS tube MP2, the fourth MOS tube MP3 and the fifth MOS tube MP4 are connected with a power supply voltage, the drain electrode of the eighth MOS tube MPC4 is connected with the collector electrode of the first triode Q1, the drain electrode of the seventh MOS tube MPC3 is connected with the first input end of the second amplifier OP2, the drain electrode of the sixth MOS tube MPC2 is connected with the grid electrode of the third MOS tube MP2 and the first end of the biasing unit, and the second end of the biasing unit is connected with the grid electrode of the sixth MOS tube MPC2 and the drain electrode of the second MOS tube MN 1.
In this embodiment, the bias unit includes a ninth MOS transistor MPB1, where a gate of the ninth MOS transistor MPB1 is connected to a drain and connected to a gate of the sixth MOS transistor MPC2 and a drain of the second MOS transistor MN1, and a source of the ninth MOS transistor MPB1 is connected to a drain of the sixth MOS transistor MPC 2. In other embodiments, the bias unit includes a resistor, a first end of the resistor is connected to the gate of the sixth MOS transistor MPC2 and the drain of the second MOS transistor MN1, and a second end of the resistor is connected to the drain of the sixth MOS transistor MPC 2.
In this embodiment, the third MOS transistor MP2, the fourth MOS transistor MP3, the fifth MOS transistor MP4, the sixth MOS transistor MPC2, the seventh MOS transistor MPC3, the eighth MOS transistor MPC4, and the ninth MOS transistor MPB1 are P-channel MOS transistors, and in other embodiments, N-channel MOS transistors may be selected.
In this embodiment, the influence of the channel modulation effect on the circuit can be reduced by the cascode current mirror circuit, so that the accuracy of the compensation current is higher.
Example 3
As shown in fig. 4, a plurality of compensation units are provided, and in this embodiment, two compensation units are provided for the first transistor Q1 and the N second transistors Q2, respectively, the compensation unit a for compensating the leakage current of the parasitic diode D2 of the N second transistors Q2, and the compensation unit B for compensating the leakage current of the parasitic diode D1 of the first transistor Q1.
The first replica unit A1 of the compensation unit a is connected to the collectors of the N second transistors Q2 to output replica voltages proportional to the voltages of the collector terminals of the N second transistors Q2, respectively. The sampling unit A2 of the compensation unit a is connected to the first replica unit A1, and the compensation unit a obtains a sampling current proportional to the leakage currents of the parasitic diodes D2 of the N second transistors Q2 based on the corresponding replica voltages. The second replication unit A3 of the compensation unit a is connected to the first replication unit A1 and the collectors of the N second triodes Q2, and the sampling current is transmitted to the second replication unit A3 through the first replication unit A1, and the second replication unit A3 is configured to replicate the corresponding sampling current into the compensation current in proportion and transmit the compensation current to the collectors of the N second triodes Q2.
As shown in fig. 4, the first replication unit A1 includes a second amplifier OP2 and a second MOS transistor MN1. The first input end of the second amplifier OP2 is connected with the collectors of N second triodes Q2, the second input end of the second amplifier OP2 is connected with the sampling unit A2, the grid electrode of the second MOS tube MN1 is connected with the output end of the second amplifier OP2, the drain electrode of the second MOS tube MN1 is connected with the second copying unit A3, and the source electrode of the second MOS tube MN1 is connected with the sampling unit A2. In this embodiment, the first input terminal of the second amplifier OP2 is a positive input terminal, the second input terminal of the second amplifier OP2 is a negative input terminal, and in other embodiments, the first input terminal of the second amplifier OP2 is a negative input terminal, and the second input terminal of the second amplifier OP2 is a positive input terminal.
In this embodiment, the voltage of the collector terminals of the N second transistors Q2 is copied from the first input terminal of the second amplifier OP2 to the second input terminal of the second amplifier OP2 through the second amplifier OP2, and at the same time, the conduction of the second MOS transistor MN1 is controlled through the second amplifier OP 2.
The first replica cell 10 further comprises a first capacitor C1 and a first diode Dp1. The first end of the first capacitor C1 is connected to the output terminal of the second amplifier OP2, and the second end of the first capacitor C1 is connected to ground. The first capacitor C1 may be a MOS capacitor, a MOM capacitor, or a MIM capacitor. The cathode of the first diode Dp1 is connected with the grid electrode of the second MOS tube MN1, and the anode of the first diode Dp1 is connected with the source electrode of the second MOS tube MN 1. In other embodiments, the first diode Dp1 is a parasitic diode of a certain MOS transistor.
In a low temperature environment, the compensation unit a is approximately open. In a high temperature environment, a compensation loop of the compensation unit a is established. The first capacitor C1 is used to maintain stability of the compensation loop in the process from the low temperature environment to the high temperature environment. The first diode Dp1 is used to prevent uncertainty of voltage due to high resistance generated at the node of the parasitic diode D3 of the sampling unit A2 in low temperature and normal temperature environments.
In other embodiments, the second amplifier OP2 may not be disposed in the first replication unit A1, but the second MOS transistor MN1 is a native-MOS transistor. At this time, the gate of the second MOS transistor MN1 is connected to the collectors of the N second transistors Q2, the source of the second MOS transistor MN1 is connected to the sampling unit A2, and the drain of the second MOS transistor MN1 is connected to the second replica unit A3. Because the threshold of the active-MOS transistor is very low and normally open, the voltage on the gate of the second MOS transistor MN1 can be copied to the source of the second MOS transistor MN 1.
As shown in fig. 4, the sampling unit A2 includes a third transistor Q3 that is set floating (i.e., not grounded). The base and emitter of the third triode Q3 are connected to the collector and to the second input terminal of the second amplifier OP2 and the source of the second MOS transistor MN 1. The parasitic diode D3 of the third transistor Q3 generates a leakage current (i.e., the above sampling current) through the replica voltage, and the leakage current of the parasitic diode D3 of the third transistor Q3 is transmitted to the second replica unit A3 through the second MOS transistor MN 1. In this embodiment, the area ratio of the third transistor Q3 to the N second transistors Q2 is 1: n.
The second replica unit A3 includes a first current mirror circuit, which is a first cascades current mirror circuit in this embodiment, and in other embodiments, the first current mirror circuit may be a current mirror circuit with other structures. The first cascades current mirror circuit is connected with the first replication unit A1 and the collectors of the N second triodes Q2 to output compensation current to the collectors of the N second triodes Q2 in proportion.
As shown in fig. 4, the first cascades current mirror circuit includes a third MOS transistor MP2, a sixth MOS transistor MPC2, a first bias unit, a fourth MOS transistor MP3, and a seventh MOS transistor MPC3.
The third MOS tube MP2 and the fourth MOS tube MP3 are connected in a common gate mode, and the sixth MOS tube MPC2 and the seventh MOS tube MPC3 are connected in a common gate mode. The drain electrode of the third MOS tube MP2 is connected with the source electrode of the sixth MOS tube MPC2, and the drain electrode of the fourth MOS tube MP3 is connected with the source electrode of the seventh MOS tube MPC3. The sources of the third MOS tube MP2 and the fourth MOS tube MP3 are connected with a power supply voltage, the drain electrode of the seventh MOS tube MPC3 is connected with the collectors of the N second triodes Q2, the drain electrode of the sixth MOS tube MPC2 is connected with the grid electrode of the third MOS tube MP2 and the first end of the first bias unit, and the second end of the first bias unit is connected with the grid electrode of the sixth MOS tube MPC2 and the drain electrode of the second MOS tube MN 1.
In this embodiment, the influence of the channel modulation effect on the circuit can be reduced by the first cascode current mirror circuit, so that the accuracy of the compensation current is higher.
The first bias unit comprises a ninth MOS tube MPB1, wherein a grid electrode of the ninth MOS tube MPB1 is connected with a drain electrode and is connected with a grid electrode of a sixth MOS tube MPC2 and a drain electrode of a second MOS tube MN1, and a source electrode of the ninth MOS tube MPB1 is connected with the drain electrode of the sixth MOS tube MPC 2. In other embodiments, the first bias unit includes a first resistor, a first end of the first resistor is connected to the gate of the sixth MOS transistor MPC2 and the drain of the second MOS transistor MN1, and a second end of the first resistor is connected to the drain of the sixth MOS transistor MPC 2.
In this embodiment, the third MOS transistor MP2, the fourth MOS transistor MP3, the sixth MOS transistor MPC2, the seventh MOS transistor MPC3, and the ninth MOS transistor MPB1 are P-channel MOS transistors, and in other embodiments, N-channel MOS transistors may be selected.
In the present embodiment, the ratio of the area of the third transistor Q3 to the area of the N second transistors Q2 is 1: n, the ratio of the area of the third MOS tube MP2 to the area of the fourth MOS tube MP3 is 1: the areas of the N second triodes Q2 are equal to the area of the fourth MOS transistor MP3, so that the leakage current of the parasitic diode D3 of the third triode Q3 can be amplified N times by the fourth MOS transistor MP3 and then delivered to the collector electrodes of the N second triodes Q2, so as to compensate the leakage current of the parasitic diode D2 of the N second triodes Q2, and the current flowing through the third resistor R3 can all flow into the second triodes Q2.
In other embodiments, the number of parallel third transistors Q3 or the area of the third transistors Q3 may be changed, so that the leakage current of the parasitic diode D3 of the third transistor Q3 is equal to the leakage current of the N parasitic diodes of the second transistors Q2, and the ratio of the area of the corresponding third MOS transistor MP2 to the area of the fourth MOS transistor MP3 may be set as N: n.
The first replica unit B1 of the compensation unit B is connected to the collector of the first transistor Q1 to output a replica voltage proportional to the voltage of the collector terminal of the first transistor Q1. The sampling unit B2 of the compensation unit B is connected to the first replica unit B1, and the sampling unit B2 obtains a sampling current proportional to the leakage current of the parasitic diode D1 of the first transistor Q1 based on the corresponding replica voltage. The second replica unit B3 of the compensation unit B is connected to the first replica unit B1 and the collector of the first triode Q1, the sampling current is transmitted to the second replica unit B3 through the first replica unit B1, and the second replica unit B3 is configured to proportionally replicate the corresponding sampling current into the compensation current and transmit the compensation current to the collector of the first triode Q1.
As shown in fig. 4, the first replication unit B1 includes a third amplifier OP3 and a thirteenth MOS transistor MN2; the first input end of the third amplifier OP3 is connected with the collector electrode of the first triode Q1, the second input end of the third amplifier OP3 is connected with the sampling unit B2, the grid electrode of the thirteenth MOS tube MN2 is connected with the output end of the third amplifier OP3, the drain electrode of the thirteenth MOS tube MN2 is connected with the second copying unit B3, and the source electrode of the thirteenth MOS tube MN2 is connected with the sampling unit B2. In this embodiment, the first input terminal of the third amplifier OP3 is a positive input terminal, the second input terminal of the third amplifier OP3 is a negative input terminal, and in other embodiments, the first input terminal of the third amplifier OP3 is a negative input terminal, and the second input terminal of the third amplifier OP3 is a positive input terminal.
In this embodiment, the voltage of the collector terminal of the first triode Q1 is copied from the first input terminal of the third amplifier OP3 to the second input terminal of the third amplifier OP3 through the third amplifier OP3, and at the same time, the conduction of the thirteenth MOS transistor MN2 is controlled through the third amplifier OP 3.
The first replica unit B1 further comprises a second capacitor C2 and a second diode Dp2, a first end of the second capacitor C2 is connected to the output terminal of the third amplifier OP3, and a second end of the second capacitor C2 is connected to ground. The second capacitor C2 is a MOS capacitor, a MOM capacitor, or a MIM capacitor. The cathode of the second diode Dp2 is connected to the gate of the thirteenth MOS transistor MN2, and the anode of the second diode Dp2 is connected to the source of the thirteenth MOS transistor MN 2. In other embodiments, the second diode Dp2 may be a parasitic diode of a certain MOS transistor.
In a low temperature environment, the compensation unit B is approximately open. In a high temperature environment, a compensation loop of the compensation unit B is established. The second capacitor C2 is used to maintain the stability of the compensation loop during the process from the low temperature environment to the high temperature environment. The second diode Dp2 is used to prevent uncertainty of voltage due to high resistance generated at the node of the parasitic diode D4 of the sampling unit B2 in low temperature and normal temperature environments.
In other embodiments, the third amplifier OP3 may not be disposed in the first replication unit B1, but the thirteenth MOS transistor MN2 needs to be a active-MOS transistor; the gate of the thirteenth MOS transistor MN2 is connected with the collector of the first triode Q1, the source of the thirteenth MOS transistor MN2 is connected with the collector, and the drain of the thirteenth MOS transistor MN2 is connected with the second copying unit B3. Because the threshold of the active-MOS transistor is very low and normally open, the voltage on the gate of the second MOS transistor MN1 can be copied to the source of the second MOS transistor MN 1.
As shown in fig. 4, the sampling unit B2 includes a fourth transistor Q4 that is set floating (i.e., not grounded). The base and emitter of the fourth transistor Q4 are connected to the collector and to the source of the thirteenth MOS transistor MN2 and to the second input of the third amplifier OP 3. The parasitic diode D4 of the fourth transistor Q4 generates a leakage current (i.e., the above-mentioned sampling current) through the replica voltage, and the leakage current of the parasitic diode D4 of the fourth transistor Q4 is transferred to the second replica unit B3 through the thirteenth MOS transistor MN 2. In this embodiment, the area ratio of the fourth transistor Q4 to the first transistor Q1 is 1:1.
the second replica unit B3 includes a second current mirror circuit, which is a second cascades current mirror circuit in this embodiment, and is a current mirror circuit with other structures in other embodiments. The second cascades current mirror circuit is connected to the first replica unit B1 and the collector of the first transistor Q1 to output the compensation current to the collector of the first transistor Q1 in proportion.
As shown in fig. 4, the second cascades current mirror circuit includes a fifth MOS transistor MP4, a tenth MOS transistor MP5, an eighth MOS transistor MPC4, an eleventh MOS transistor MPC5, and a second bias unit.
The fifth MOS tube MP4 is connected with the tenth MOS tube MP5 in a common gate mode, and the eighth MOS tube MPC4 is connected with the eleventh MOS tube MPC5 in a common gate mode. The drain electrode of the fifth MOS tube MP4 is connected with the source electrode of the eighth MOS tube MPC4, and the drain electrode of the tenth MOS tube MP5 is connected with the source electrode of the eleventh MOS tube MPC 5. The sources of the fifth MOS tube MP4 and the tenth MOS tube MP5 are connected with a power supply voltage, the drain electrode of the eleventh MOS tube MPC5 is connected with the collector electrode of the first triode Q1 and the first input end of the second amplifier OP2, the drain electrode of the eighth MOS tube MPC4 is connected with the grid electrode of the fifth MOS tube MP4 and the first end of the second biasing unit, and the second end of the second biasing unit is connected with the grid electrode of the eighth MOS tube MPC4 and the drain electrode of the thirteenth MOS tube MN 2.
In this embodiment, the second bias unit includes a twelfth MOS transistor MPB2. The grid electrode of the twelfth MOS tube MPB2 is connected with the drain electrode, the grid electrode of the eighth MOS tube MPC4 is connected with the drain electrode of the thirteenth MOS tube MN2, and the source electrode of the twelfth MOS tube MPB2 is connected with the drain electrode of the eighth MOS tube MPC 4. In other embodiments, the second bias unit includes a second resistor, a first end of the second resistor is connected to the gate of the eighth MOS transistor MPC4 and the drain of the thirteenth MOS transistor MN2, and a second end of the second resistor is connected to the drain of the eighth MOS transistor MPC 4.
In this embodiment, the fifth MOS transistor MP4, the tenth MOS transistor MP5, the eighth MOS transistor MPC4, the eleventh MOS transistor MPC5, and the twelfth MOS transistor MPB2 are P-channel MOS transistors, and in other embodiments, N-channel MOS transistors may be selected.
In this embodiment, the influence of the channel modulation effect on the circuit can be reduced by the second cascode current mirror circuit, so that the accuracy of the compensation current is higher.
In the present embodiment, the ratio of the area of the fourth transistor Q4 to the area of the first transistor Q1 is 1:1, the ratio of the area of the fifth MOS transistor MP4 to the area of the tenth MOS transistor MP5 is 1:1, the area of the first triode Q1 is equal to the area of the fifth MOS transistor MP4, so that the leakage current of the parasitic diode D1 of the first triode Q1 is transferred to the collector of the first triode Q1 through the fifth MOS transistor MP4 in equal proportion, so as to compensate the leakage current of the parasitic diode D1 of the first triode Q1, and the current flowing through the first resistor R1 can all flow into the first triode Q1.
The embodiment also discloses a leakage current compensation method of the voltage generation circuit, the voltage generation circuit comprises a band gap collector unit, the band gap collector unit comprises a first triode Q1 and N second triodes Q2, a base electrode of the first triode Q1 is connected with a collector electrode, a base electrode and a collector electrode of the N second triodes Q2 are connected, an emitter electrode of the first triode Q1 is connected with an emitter electrode of the N second triodes Q2 and is simultaneously connected with the ground, and N is more than or equal to 1.
As shown in fig. 5, the leakage current compensation method includes:
s1, the voltages of the collector terminals of the first triode Q1 and the N second triodes Q2 are copied in proportion to obtain corresponding copy voltages.
S2, obtaining sampling currents which are proportional to the leakage currents of the parasitic diodes D1 of the first triode Q1 and the leakage currents of the parasitic diodes D2 of the N second triodes Q2 based on the corresponding replica voltages; in the present embodiment, a ratio of sampling current to leakage current proportional to leakage current of the parasitic diode D1 of the first transistor Q1 is obtained as 1:1, a ratio of sampling current proportional to leakage current of parasitic diode D2 of N second transistors Q2 to the leakage current is obtained as 1: n.
S3, copying corresponding sampling currents in proportion to form corresponding compensation currents, and conveying the corresponding compensation currents to the collector electrode ends of the first triode Q1 and the N second triodes Q2; in the present embodiment, the obtained sampling current proportional to the leakage current of the parasitic diode D1 of the first transistor Q1 is equal-proportioned to compensate for the leakage current of the parasitic diode D1 of the first transistor Q1, and the obtained sampling current proportional to the leakage current of the parasitic diode D2 of the N second transistors Q2 is amplified by N times to compensate for the leakage current of the parasitic diode D2 of the N second transistors Q2.
The embodiment also discloses a chip comprising the voltage generating circuit.
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims (16)

1. A voltage generation circuit, comprising:
the band gap collector unit comprises a first triode and N second triodes, wherein the base electrode of the first triode is connected with the collector electrode, the base electrode and the collector electrode of the N second triodes are connected, the emitter electrode of the first triode is connected with the emitter electrodes of the N second triodes and is simultaneously connected with the ground, and N is more than or equal to 1; and
a compensation unit, the compensation unit comprising:
The first copying unit is connected with the collector electrodes of the first triode or the N second triodes to output copying voltage proportional to the voltage of the collector terminals of the first triode or the N second triodes;
the sampling unit is connected with the first copying unit and obtains sampling current proportional to leakage current of parasitic diodes of the first triode or the N second triodes based on the copying voltage;
the second copying unit is connected with the first copying unit, the collector electrodes of the first triodes and the collector electrodes of the N second triodes, the sampling current is transmitted to the second copying unit through the first copying unit, and the second copying unit is used for copying the sampling current into compensation current according to the number of the first triodes and the second triodes in proportion and transmitting the compensation current to the collector electrodes of the first triodes and the N second triodes.
2. The voltage generation circuit of claim 1 wherein the second replica unit comprises a current mirror circuit coupled to the first replica unit, the current mirror circuit coupled to the collectors of the first transistor and the N second transistors simultaneously to scale the sampled current to corresponding compensation currents and to the collectors of the first transistor and the N second transistors to compensate for leakage currents of parasitic diodes of the first transistor and the N second transistors.
3. A voltage generation circuit, comprising:
the band gap collector unit comprises a first triode and N second triodes, wherein the base electrode of the first triode is connected with the collector electrode, the base electrode and the collector electrode of the N second triodes are connected, the emitter electrode of the first triode is connected with the emitter electrodes of the N second triodes and is simultaneously connected with the ground, and N is more than or equal to 1; and
the compensation unit is connected with the collector electrodes of the first triode and the N second triodes respectively, and is used for compensating leakage currents of parasitic diodes of the first triode and the N second triodes respectively, and comprises:
the first copying unit is respectively connected with the collectors of the first triode and the N second triodes to respectively output copying voltages which are proportional to the voltages of the collector terminals of the corresponding triodes;
sampling units respectively connected with the first copying units, wherein each sampling unit obtains sampling current proportional to leakage current of a parasitic diode of a corresponding triode based on corresponding copying voltage;
the second copying units are respectively connected with the first copying units and the collector electrodes of the triodes, the sampling current is transmitted to the corresponding second copying units through the first copying units, and the second copying units are used for copying the sampling current into compensation current according to the number of the first triodes and the number of the second triodes in proportion and transmitting the compensation current to the collector electrodes of the corresponding triodes.
4. A voltage generating circuit according to claim 1 or 3, wherein the first replica unit comprises a second amplifier and a second MOS transistor, a first input terminal of the second amplifier is connected to a collector of the corresponding transistor, a second input terminal of the second amplifier is connected to the sampling unit, a gate of the second MOS transistor is connected to an output terminal of the second amplifier, a source of the second MOS transistor is connected to the sampling unit, and a drain of the second MOS transistor is connected to the second replica unit.
5. The voltage generating circuit according to claim 1 or 3, wherein the first replica unit comprises a second MOS transistor, the second MOS transistor is a active-MOS transistor, a gate of the second MOS transistor is connected to a collector of a corresponding triode, a source of the second MOS transistor is connected to the sampling unit, and a drain of the second MOS transistor is connected to the second replica unit.
6. A voltage generation circuit according to claim 1 or 3, wherein the sampling unit comprises a third transistor having a base, an emitter and a collector connected to the first replica unit.
7. The voltage generation circuit of claim 3 wherein the second replica unit comprises current mirror circuits, each of which copies each of the sampled currents to each of the compensation currents in proportion and supplies the compensation currents to the collectors of the corresponding transistors to compensate for leakage currents of the parasitic diodes of the corresponding transistors.
8. The voltage generation circuit of claim 2 or 7, wherein the current mirror circuit is a cascades current mirror circuit.
9. A voltage generating circuit according to claim 1 or 3, wherein the first replica unit comprises a second amplifier and a second MOS transistor, a first input terminal of the second amplifier is connected to a collector of the corresponding triode, a second input terminal of the second amplifier is connected to the sampling unit, a gate of the second MOS transistor is connected to an output terminal of the second amplifier, a source of the second MOS transistor is connected to the sampling unit, and a drain of the second MOS transistor is connected to the second replica unit; or alternatively
The first copying unit comprises a second MOS tube, the second MOS tube is a native-MOS tube, the grid electrode of the second MOS tube is connected with the collector electrode of the corresponding triode, the source electrode of the second MOS tube is connected with the sampling unit, and the drain electrode of the second MOS tube is connected with the second copying unit;
the first replication unit further comprises a capacitor, a first end of the capacitor is connected with the grid electrode of the second MOS tube, and a second end of the capacitor is connected with the ground.
10. The voltage generation circuit of claim 9, wherein the capacitance is a MOS capacitance, a MOM capacitance, or a MIM capacitance.
11. A voltage generating circuit according to claim 1 or 3, wherein the first replica unit comprises a second amplifier and a second MOS transistor, a first input terminal of the second amplifier is connected to a collector of the corresponding triode, a second input terminal of the second amplifier is connected to the sampling unit, a gate of the second MOS transistor is connected to an output terminal of the second amplifier, a source of the second MOS transistor is connected to the sampling unit, and a drain of the second MOS transistor is connected to the second replica unit; or alternatively
The first copying unit comprises a second MOS tube, the second MOS tube is a native-MOS tube, the grid electrode of the second MOS tube is connected with the collector electrode of the corresponding triode, the source electrode of the second MOS tube is connected with the sampling unit, and the drain electrode of the second MOS tube is connected with the second copying unit;
the first copying unit further comprises a diode, the cathode of the diode is connected with the grid electrode of the second MOS tube, and the anode of the diode is connected with the source electrode of the second MOS tube.
12. The voltage generation circuit of claim 11 wherein the diode is a parasitic diode of the second MOS transistor.
13. A voltage generation circuit according to claim 1 or 3, further comprising a first amplifier, a first resistor, a second resistor, a third resistor and a current source, wherein the first input terminal of the first amplifier is connected to the collector of the first transistor and to the first terminal of the first resistor, the second input terminal of the first amplifier is connected to the first terminal of the third resistor and to the first terminal of the second resistor, the second terminal of the third resistor is connected to the collectors of the N second transistors, the second terminal of the first resistor is connected to the second terminal of the second resistor, the control terminal of the current source is connected to the output terminal of the first amplifier, the first terminal of the current source is connected to the supply voltage, and the second terminal of the current source is connected to the second terminal of the second resistor.
14. The voltage generation circuit of claim 13 wherein the current source comprises a first MOS transistor, a gate of the first MOS transistor is coupled to an output of the first amplifier, a source of the first MOS transistor is coupled to a supply voltage, and a drain of the first MOS transistor is coupled to a second end of the second resistor.
15. The leakage current compensation method of the voltage generation circuit is characterized in that the voltage generation circuit comprises a band-gap collector unit, the band-gap collector unit comprises a first triode and N second triodes, the base electrode of the first triode is connected with a collector electrode, the base electrode and the collector electrode of the N second triodes are connected, the emitter electrode of the first triode is connected with the emitter electrodes of the N second triodes and is simultaneously connected with the ground, and N is more than or equal to 1;
the leakage current compensation method comprises the following steps:
the voltages of the collector electrode terminals of the first triode and/or the N second triodes are duplicated in proportion to obtain corresponding duplicated voltages;
obtaining sampling currents which are proportional to the leakage currents of the parasitic diodes of the first triode and/or the leakage currents of the parasitic diodes of the N second triodes based on the corresponding replica voltages;
based on the number of the first triode and the second triode, corresponding sampling currents are copied in proportion to form compensation currents, and the corresponding compensation currents are transmitted to collector ends of the first triode and the N second triodes.
16. A chip comprising a voltage generating circuit according to any one of claims 1 to 14.
CN202211185442.9A 2022-09-27 2022-09-27 Voltage generating circuit, leakage current compensation method and chip Active CN115454200B (en)

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CN107870648A (en) * 2017-11-16 2018-04-03 中国科学院微电子研究所 Band gap reference voltage generating device
CN109888446A (en) * 2019-04-10 2019-06-14 曾运华 A kind of active resonator of loss balancing type electricity tune and its loss compensation method
CN113419591A (en) * 2021-07-23 2021-09-21 深圳英集芯科技股份有限公司 Leakage current compensation structure, method, device and equipment based on band gap collector
CN113655841A (en) * 2021-08-18 2021-11-16 西安电子科技大学重庆集成电路创新研究院 Band gap reference voltage circuit
CN217443795U (en) * 2022-05-31 2022-09-16 上海灿瑞科技股份有限公司 Band-gap reference circuit with high-temperature compensation function

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