JP3110360B2 - Power-on reset circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power-on reset circuit of a semiconductor integrated circuit, and more particularly to a power-on reset circuit of a semiconductor integrated circuit such as a semiconductor memory having a substrate potential generating circuit.

[0002]

2. Description of the Related Art A conventional power-on reset circuit used in a semiconductor integrated circuit performs a reset operation immediately after power-on by giving a time constant to the power-on voltage by means of an element resistor and a capacitor. I have. On the other hand, the substrate potential generation circuit and the substrate potential detection circuit are circuits independent of the power-on reset circuit. For example, FIG. 6 shows an example of a semiconductor memory integrated circuit, in which a power-on reset circuit including a time constant circuit 16 and CMOS inverters 3 and 4 and a substrate potential detection circuit 5 are configured independently of each other.

The power-on reset circuit has a first P-channel circuit having one end of a current path connected to VCC, a gate connected to GND, and the other end of the current path connected to an output node "A" of a time constant circuit.
A time constant circuit is constituted by the channel MOS transistor 1 and a capacitor 2 having one end connected to the output node "A" of the time constant circuit and the other end connected to GND. CMOS
The inverter has one end of the current path connected to VCC, the gate connected to the output node "A" of the time constant circuit, and the other end connected to the output node "B" of the power-on reset circuit.
The channel MOS transistor 3 and one end of the current path were connected to the output node "B" of the power-on reset circuit, the gate was connected to the output node "A" of the time constant circuit, and the other end of the current path was connected to GND. And an N-channel MOS transistor 4.

According to the configuration of the power-on reset circuit, as the potential of VCC rises when the power is turned on, a potential difference occurs between the gate of the first P-channel MOS transistor 1 and the first P-channel MOS transistor. 1 becomes conductive. At this time, the first P channel MO
A channel resistance exists in the source / drain current path of the S transistor 1, and a time constant is determined in combination with the capacitance value of the capacitor 2. As a result, the potential of the output node "A" of the time constant circuit has a time constant with respect to the potential of VCC and rises later.

The potential at the output node "A" of the time constant circuit is C
Until the potential of the output node "A" exceeds the threshold value of the CMOS inverter circuit.
The output potential of the OS inverter circuit rises while following the VCC potential at the same potential. This state is a reset operation.

Thereafter, the output node "A" of the time constant circuit 16
Is higher than the threshold value of the CMOS inverter circuit, the output potential of the CMOS inverter circuit becomes the GND potential, and the reset operation is released.

[0007] As described above, the time constant circuit 16
A time constant consisting of the channel resistance of the OS transistor 1 and the capacitance of the capacitor 2 connected in series with the OS transistor 1;
Except immediately after power-on, as long as the VCC potential holds the normal potential, the potential of the capacitor is also held.
The reset operation is performed only when the power is turned on.

In a semiconductor integrated circuit having a substrate potential generation circuit mounted thereon, the substrate potential is detected by a substrate potential detection circuit 5, and based on the output, the substrate potential is held at an appropriate level, and the threshold voltage of the MOS transistor is reduced. To keep the operation stable. For this reason, in order to perform the above reset operation reliably, the substrate potential at the time of power-on reset is also required as a condition for the reset operation. It was not a real problem because was essential.

However, in recent semiconductor integrated circuits, an operation mode has been set beforehand and used more and more, and there are many problems caused by a failure in normal initialization when power is turned on. Further, the power consumption of semiconductor integrated circuits has been reduced, and the threshold voltage of MOS transistors has been reduced. Along with these changes in the situation, there has been a need to reliably perform initialization at power-on, which has been neglected in the past.

[0010]

In the above-described conventional power-on reset circuit of a semiconductor integrated circuit, it is described that the substrate potential generation circuit and the substrate potential detection circuit exist independently of the power-on reset circuit. It is as follows. The power-on reset signal is used for initialization of many peripheral circuits because of its role. FIG. 7 shows an example of a general circuit diagram of a semiconductor memory integrated circuit. An output signal from the power-on reset circuit 26 is wired around the memory cell array 21 and supplies a reset signal “H” to peripheral circuits that need to be initialized when power is turned on.

The circuit A (18) and the circuit B shown in FIG.
(25) is a circuit initialized by a reset signal “H” from the power-on reset circuit 26. As described above, there are not a few cases where the power-on reset circuit 26 and the circuit B (25) to be initialized are physically separated from each other due to layout restrictions or the like. However, such a large separation distance is not limited to only the power-on reset signal, and similarly occurs in transmission and reception of signals between peripheral circuits. It can be said that a similar condition exists between the driver circuit 17 and the circuit B (25) and the circuit C (20) in FIG. Here, a driver circuit 17 for transmitting a signal is sent to a circuit A for receiving.
(18) is located at the near end, circuit B (25) and circuit C
(20) is located at the farthest end. Therefore, these circuits B
(25) and the circuit C (18) have a high wiring impedance and are easily affected by an adjacent wiring.

However, the circuit B (25) and the circuit C (2
0), also due to the wiring layout of the CLK signal,
There is a difference in the influence from the adjacent wiring. Circuit B (25)
In the case of (1), initialization by the power-on reset signal "H" is required, and the distance between the internal signal wiring and the CLK wiring is long and located at the far end with respect to the driver circuit 17. Significantly affected by signals. On the other hand, the circuit C (20) is located at the far end from the driver 17 similarly to the circuit B (25), but the initialization by the power-on reset signal “H” is unnecessary, and the internal signal In that the distance between the wiring and the CLK wiring is short, the influence of the adjacent CLK signal is not so large.

As described above, the above-mentioned layout-related factors cause an effect between adjacent wirings. However, in the initialization at the time of power-on, in addition to the layout-related factors, a circuit is also required. The characteristics of the constituent elements are greatly involved. In many cases, a semiconductor integrated circuit includes a MOS transistor as a component thereof.
In the OS transistor, in order to stabilize its characteristics,
It is necessary to properly maintain the substrate potential.

Since the substrate potential is generated by a substrate potential generation circuit mounted on a semiconductor integrated circuit, the substrate potential cannot be maintained at an appropriate value immediately after power-on.
Before the substrate potential reaches an appropriate potential, the operation of the MOS transistor is also unstable, and the MOS transistor is susceptible to the above-mentioned noise from the adjacent wiring. Specifically, for example, the threshold voltage of an N-channel MOS transistor is
Immediately after this power is turned on, it is extremely low, from 0.2 V to 0.3
It is known that a conduction state is caused by noise of about V.

As for the relationship between the driver circuit 17 and the circuit B (25), the inverter 22 in the input stage of the circuit B (25) immediately before the power supply is turned on and before the substrate potential reaches the appropriate potential.
May malfunction due to the influence of adjacent noise from the CLK signal. This will be described with reference to the signal timing chart of FIG. When the power is turned on at time T1, the power-on reset signal “H” and the internal signal “J”, and then the internal signal “K” start to rise following the power supply voltage from time T3. Also, T
At three times, the substrate potential starts to be supplied, and gradually drops to a potential lower than GND. Thereafter, the power-on reset is released at time T5 according to the internal time constant by the power-on reset signal. Although the supply of the external CLK signal starts at time T6, the substrate potential at this time has not yet reached an appropriate value, and thus the driver circuit 17 and the circuit B
In relation to (25), the adjacent CLK signal affects the internal signal "M" near the input of the circuit B (25), causing the N-channel MOS transistor of the inverter 22 in the input stage to malfunction.

In this example, the supply of the external CLK signal is started at time T6, which triggers a malfunction, but the improper substrate potential at this time also causes a malfunction. ing.

As described above, in the semiconductor integrated circuit, since the threshold voltage of the MOS transistor is not stable immediately after the power is turned on, reliable initialization cannot be performed, or the state changes after initialization. There was a problem.

In view of the above, an object of the present invention is to provide a semiconductor integrated circuit having a substrate potential generating circuit for applying a substrate potential and a substrate potential detecting circuit for detecting a substrate potential and outputting a signal for controlling the substrate potential generating circuit. Another object of the present invention is to provide a power-on reset circuit that outputs a power-on reset signal that enables a reliable and highly reliable reset operation in a power-on reset circuit mounted on a power-on reset circuit.

[0019]

In order to achieve the above object, a power-on reset circuit according to the present invention comprises a substrate potential generating circuit for applying a substrate potential, and controlling the substrate potential generating circuit by detecting the substrate potential. A power-on reset circuit of a semiconductor integrated circuit having a substrate potential detection circuit for outputting a signal to perform the operation of detecting a predetermined period of time after power-on. A power-on reset is performed by outputting an output signal of the potential detection circuit, and a predetermined power-on reset signal for canceling the power-on reset by disabling the output of the substrate potential detection circuit after a predetermined time has elapsed since the power-on reset. A signal generation circuit.

In the power-on reset circuit of the present invention, the output of the substrate potential detection circuit, which was independent in the conventional circuit, is output immediately after the power-on, and after a predetermined time has elapsed from the power-on, the output of the substrate detection circuit is replaced with the power-on reset. Outputs reset signal. Thus, a predetermined power-on reset signal is output after an appropriate substrate potential is obtained. A malfunction that occurs at the time of initialization when the power is turned on can be prevented.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail based on embodiments of the present invention with reference to the drawings. FIG.
1 shows a power-on reset circuit according to an embodiment of the present invention. 6 is different from the conventional circuit shown in FIG. 6 in that a reset signal generation circuit 30 for logically synthesizing the power-on reset signal and the output of the substrate potential detection circuit 5 which are independent in FIG.

More specifically, the power-on reset circuit of this embodiment has a time constant circuit 16 and a reset signal generation circuit 30, and uses the output "E" of the substrate potential detection circuit 5 as an input. The time constant circuit 16 connects one end (source) of the current path to the power supply VCC and connects the gate to GND ("
C "), and the other end (drain) of the current path is connected to an output node (output node)" A "of the time constant circuit.
It comprises a channel MOS transistor 1 and a capacitor 2 having one end connected to the output node "A" of the time constant circuit 16 and the other end connected to GND.

In the reset signal generation circuit 30, one end of the current path is connected to the internal node "F", and the gate is connected to the time constant circuit 1
6, the second P-channel MOS transistor having the other end of the current path connected to the output node "B" of the power-on reset circuit 30, and one end (drain) of the current path connected to the power node. The gate is connected to the output node "A" of the time constant circuit 16, and the other end (source) of the current path is connected to the output node "B" of the ON reset circuit 30.
N channel MOS transistor 4 connected to
And a third P-channel M whose one end of the current path is connected to VCC, the gate is connected to the output node "E" of the substrate potential detection circuit 5, and the other end of the current path is connected to the internal node "F".
The OS transistor 6 and one end of the current path are connected to the output node "B" of the power-on reset circuit 30, the gate is connected to the output node "E" of the substrate potential detection circuit 5, and the other end of the current path is connected to GND. Second N-channel MOS connected
A logic gate circuit including the transistor 7 is provided.

As described above, in the power-on reset circuit of this embodiment, the output "E" of the substrate potential detection circuit 5, which is independent in the conventional circuit, is output to the reset signal generation circuit 30.
, And is logically synthesized with the output of the time constant circuit 16 to output a power-on reset signal “B”.

According to the above configuration, when power is turned on, VCC is
As the potential rises, a potential difference occurs between the source and the gate of the first P-channel MOS transistor 1, and the first P-channel MOS transistor 1 becomes conductive. At this time, a channel resistance exists between the source and the drain of the first P-channel MOS transistor 1, and a time constant is determined by a combination of the capacitance of the capacitor 2 and the channel resistance. The potential of the output node "A" of the time constant circuit 16 rises with respect to the potential of VCC according to this time constant.

The potential of the output node "A" of the time constant circuit 16 is input to the reset signal generation circuit 30 of the next stage, and the potential of the output node "A" of the time constant circuit 16 is set to the threshold of the reset signal generation circuit 30. Board potential detection circuit 5
Is valid, and this is output as a power-on reset signal "B" for continuing the power-on reset. Thereafter, when the potential of the output node "A" of the time constant circuit 16 exceeds the threshold value of the reset signal generation circuit 30, the output "E" of the substrate potential detection circuit 5 becomes invalid, and the output of the time constant circuit is inverted. Is output as a power-on reset signal “B” for releasing the power-on reset.

The time constant circuit 16 has a PMO
It has a time constant constituted by the channel resistance of the S transistor 1 and the capacitance of the capacitor 2 connected in series, and the potential of the capacitor 2 is also held as long as the VCC potential holds a normal potential. , The power-on reset is released. Therefore, the power-on reset signal “
The active period of "B" is only when the power is turned on. The output "E" of the substrate potential detection circuit 5 is used as an input for the substrate potential generation circuit as in the conventional circuit, and is effective even after the power is turned on. Function.

The above operation will be described with reference to the timing chart of FIG. First, when the power of the semiconductor integrated circuit is turned on at the time T1, the power-on reset signal “H”, the internal signal “J”, and the internal signal “K” start rising following the power supply voltage. At the time T3, the substrate potential starts to be supplied, and the substrate potential “L” falls to a potential lower than GND. At this point, the power-on reset, which is irrelevant to the substrate potential performed in the conventional circuit, is not released, and the initialization operation is continued.

At time T6, the supply of the external CLK signal starts. However, at this time, since the substrate potential “L” has not yet reached the appropriate value, the initialization is continued. Here, in the conventional circuit, due to the relationship between the driver circuit 17 and the circuit B (25) in the semiconductor integrated circuit shown in FIG. 7, the circuit extends adjacent to the internal signal "M" which is an input to the circuit B (25). The influence of the CLK wiring which is applied causes the N-channel MOS transistor of the input stage inverter 22 to malfunction. However, in the present embodiment, the data is not destroyed in the flip-flop 24 in the circuit B (25) by the continuation of the initialization operation.

After the time T7 and before the time T8, the substrate potential "L" becomes sufficiently lower than GND, so that the N-channel MOS transistor of the input-stage inverter 22 shown in FIG. At the time, the substrate potential reaches an appropriate value, and the power-on reset is released. By performing the reset release at this point, no malfunction occurs, and the data of the flip-flop 24 in the circuit B (25) is correctly held.

FIG. 2 is a circuit diagram showing a configuration of a power-on reset circuit according to a second embodiment of the present invention. In the present embodiment, a reset signal generation circuit including a transfer gate is used instead of the configuration of the logic gate circuit of FIG. 1 that combines the output “E” of the substrate potential detection circuit 5 and the output “A” of the time constant circuit 16. Adopt 30A.

More specifically, in the power-on reset circuit of this embodiment, the reset signal generation circuit 30A includes a first transfer gate including a pair of a P-channel transistor 10 and an N-channel transistor 11;
A second transfer gate comprising a pair of P-channel transistor 12 and N-channel transistor 13;
The output “A” of the time constant circuit 16 is input to each gate.
A CMOS inverter comprising a pair of P-channel transistor 14 and N-channel transistor 15,
The wired OR output of the first and second transfer gates is the output of the power-on reset circuit of this embodiment.
B ".

The input of the first transfer gate is GND
And the input of the second transfer gate is the output “E” of the substrate potential detection circuit 5. The output of the time constant circuit 16 is input to both the gates of the N-channel transistor 11 of the first transfer gate and the P-channel transistor 12 of the second transfer gate. Also, the P-channel transistor 10 of the first transfer gate and the N-channel transistor 10 of the second transfer gate
Both gates of the channel transistor 13 are CMO
It is connected to the output "G" of the S inverter.

With the above configuration, first, when the output potential of the time constant circuit 16 is low immediately after the power is turned on, the P-channel transistor 12 of the second transfer gate is turned on, and the output "G" of the CMOS inverter is turned on. N-channel transistor 1 of the second transfer gate
3 also conducts, the second transfer gate conducts, and the output "E" of the substrate potential detection circuit 5 is output from the reset signal generation circuit 30A.

When a predetermined time has elapsed since the power was turned on and the output potential of the time constant circuit 16 exceeds the threshold voltage of the reset signal generation circuit 30A, the second transfer gate is turned off, and conversely, the first transfer gate is turned off. Is conducted, the output "E" of the substrate potential generating circuit 5 is invalidated in the reset signal generating circuit 30A, and the GND potential is output from the power-on reset circuit.

FIG. 3 shows the configuration of a power-on reset circuit according to a third embodiment of the present invention. The power-on reset circuit according to the present embodiment is the same as the power-on reset circuit according to the first embodiment.
The channel transistor 1 is replaced by a resistor 8 to form a time constant circuit 16A. Other configurations are the same as those of the first embodiment, and the same reference numerals are given and the description will be omitted. The power-on reset circuit of the present embodiment operates in the same manner as the first embodiment.

FIG. 4 shows a configuration of a power-on reset circuit according to a fourth embodiment of the present invention. In the power-on reset circuit of this embodiment, the time constant circuit 16B is configured by replacing the capacitor 2 of the time constant circuit 16 in the first embodiment with a MOS capacitor using a MOS transistor. Is the same as in the first embodiment. The power-on reset circuit of the present embodiment operates in the same manner as the first embodiment.

As described above, the present invention has been described based on the preferred embodiment. However, the power-on reset circuit of the present invention is not limited to the configuration of the above-described embodiment. Various modifications and changes from the configuration are also included in the scope of the present invention.

[0039]

As described above, according to the power-on reset circuit of the present invention, a predetermined power-on reset signal is output after the substrate potential is in an appropriate state, so that power-on reset Of the semiconductor integrated circuit, in particular, MOS transistors, and the like.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a power-on reset circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a power-on reset circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a power-on reset circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram of a power-on reset circuit according to a fourth embodiment of the present invention.

FIG. 5 is a timing chart of signals according to the embodiment of FIG. 1;

FIG. 6 is a circuit diagram of a conventional power-on reset circuit.

FIG. 7 is a schematic circuit diagram showing an example of an arrangement of a general semiconductor integrated circuit.

FIG. 8 is a timing chart of a conventional power-on reset circuit.

[Explanation of symbols]

Reference Signs List 1 P-channel MOS transistor for pull-up 2 Capacitor for generating time constant 3 P-channel MOS transistor for driver 4 N-channel MOS transistor for driver 5 Substrate potential detection circuit 6 P-channel MOS transistor for driver 7 N-channel MOS transistor for driver 8 Pull-up Element resistance 9 N-channel transistor for generating time constant 10 P-channel MOS transistor for transfer gate 11 N-channel MOS transistor for transfer gate 12 P-channel MOS transistor for transfer gate 13 N-channel MOS transistor for transfer gate 14 P-channel for transfer gate control MOS transistor 15 N-channel MOS transistor for transfer gate control 6, 16A, 16B Time constant circuit 17 Driver circuit (peripheral circuit) 18 Circuit A (peripheral circuit) 19 CLK signal-like external terminal 20 Circuit C 21 Memory cell array 22 CMOS inverter 23 CMOS 2-input NOR circuit 24 Flip-flop circuit 25 Circuit B 26 Power-on reset circuit 30, 30A Reset signal generation circuit A Time constant circuit output node B Power-on reset signal output node C GND node D VCC node E Output node of substrate potential detection circuit F Internal node FG Internal signal H Power-on reset Signal I CLK signal J Internal signal K Internal signal L Substrate potential

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-335914 (JP, A) JP-A-4-72912 (JP, A) JP-A-2-153621 (JP, A) JP-A-9-99 270686 (JP, A) Japanese Utility Model 4-86924 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 17/00-17/70

Claims (5)

(57) [Claims] A substrate potential generating circuit for applying a substrate potential;
A power-on reset circuit for a semiconductor integrated circuit having a substrate potential detection circuit for detecting the substrate potential and outputting a signal for controlling the substrate potential generation circuit; A time detecting means for outputting an output signal of the substrate potential detecting circuit within a predetermined time after power-on, and outputting a predetermined power-on reset signal after disabling the output of the substrate potential detecting circuit for a predetermined time after power-on And a reset signal generation circuit. 2. The power-on reset circuit according to claim 1, wherein said elapsed time detecting means has a time constant circuit in which an output potential rises with a time constant from power-on. 3. The power-on reset circuit according to claim 2, wherein the reset signal generation circuit is a logic circuit that performs a logical operation on an output of the time constant circuit and an output of the substrate potential detection circuit. 4. A reset signal generating circuit comprising: a first transfer gate for transmitting an output of the substrate potential detecting circuit before the substrate potential reaches a predetermined potential; and a ground after the substrate potential reaches the predetermined potential. 3. The power-on reset circuit according to claim 1, further comprising: a second transfer gate that outputs a potential as the power-on reset signal. 4. 5. The power-on reset circuit according to claim 1, wherein said elapsed time detecting means includes a MOS capacitor.