JP2703890B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a program for adjusting a circuit operation or switching a circuit function depending on whether or not a fuse is blown. Circuit. 2. Description of the Related Art Conventionally, in a semiconductor integrated circuit, this type of program circuit is configured as shown in FIG. That is, the present circuit, the fuse F ₁ to a load, N-channel MOSFET Q
Inverter driven by ₁ and N-channel MOSFE
A flip-flop circuit composed of a CMOS inverter consisting of TQ ₂ and P-channel MOSFET Q _3. If F ₁ is not disconnected, when the power is turned on while the potential of the node 1 rises following the power supply via the F _1, the potential of the node 2, the potential difference between the power supply potential and the node 1 is Q ₃ Works beyond the threshold voltage V _t to Q ₃ is turned on, hardly changed. Therefore, the potential of the node 1 rises faster than the potential of the node 2. When a result, the circuit F ₁ is connected, the node 1
High level, node 2 becomes Low level and becomes stable. On the other hand, if the F ₁ is disconnected, the node 1 at the time of power-on is in a floating state also be disconnected from the ground potential from the power supply potential. However, as we all know,
Node 1 is grounded when the power is turned on. Power source potential supply is turned exceeds the threshold voltage of Q ₃ when Q ₃
Is turned on, and the potential of the node 2 rises. As a result, node 1 Q ₁ is turned on will be connected to the ground potential, the node 2 is held at the power supply potential. Thus, in the program circuit as described above, the Low level is output signal phi _R when not cutting the fuse F _1, when the cut is fixed to the High level. That is, the output signal phi _R in accordance with the state of the fuse is controlled. [INVENTION AND SUMMARY Problems] However, in such a program circuit, as described above, when cutting the fuse F _1, since the node 1 is in a floating state at power up, following problems May occur. That is, when the power supply potential rises sharply, the potential at the node 1 also rises due to capacitive coupling due to parasitic capacitance in a single chip as a semiconductor integrated circuit. Rise at this time of potential is faster than node 2, those of Q ₂ is turned on earlier than this for Q _1. That is, this flip-flop latches data that is the reverse of the above, and node 1
The gh level and the node 2 become the Low level. Q ₁ is there but its leakage current inevitably flows in the off state, and the node 1 is disconnected from the power supply potential. Therefore, the charge stored in the node 1 is reduced by the leakage current of Q _1, finally, inverts the state of the flip-flop allowed to Q ₃ on the output signal phi _R is the fuse F ₁ is disconnected It corresponds to the state. Thus, in this circuit, the output corresponding to the cutting and non-cutting of the fuse F ₁ is eventually obtained, inversion of the output corresponding to the cutting of the fuse F _1, it is based on the leakage current for Q ₁ Since the discharge is at the node 1, a considerable time is required and a malfunction is likely to occur. An object of the present invention is to provide a circuit that outputs a signal corresponding to the disconnection / non-disconnection of a fuse immediately after power-on. [Means for Solving the Problems] A semiconductor integrated circuit according to the present invention
A power-on detection circuit that detects power-on and generates a one-shot pulse has a MOSFET that resets the circuit by the one-shot pulse. Example Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of the present invention. Differs from the conventional example shown in FIG. 4, the drain and the output node 1 of the inverter to load the fuse F ₁ is, ground source connected respectively to the output signal phi _V of power-on detection circuit to gate it is that it has a N-channel Q ₄ input. The power-on detection circuit outputs a one-shot pulse in response to power-on, as shown in the output waveform. When not cutting the fuse F _1, when the power is turned on, Q ₄ is turned on in response to the output signal phi _V of power-on detection circuit, the potential of the node 1 is Ichi担reset to the ground potential. However, since the signal φ _V disappears, Q ₄ turns off and the node 1
Rises following the power supply via the F _1. On the other hand, when the power supply rises and the potential difference between the power supply potential and the node 1 is Q ₃
Since the charge is not supplied until the voltage V _T exceeds Q V and Q ₃ is turned on, it does not easily rise. Therefore, the flip-flop is connected to node 1
Is high level and node 2 is low level and stabilized. Then, if the fuse F ₁ is cut, in the case where the potential of the node 1 is such as to increase following the power coupling due to the parasitic capacitance, for Q ₄ is turned on by receiving phi _V, node The potential of 1 is reset to the ground potential. After that, no charge is supplied to node 1 from anywhere,
The potential does not rise. On the other hand, the potential of the node 2, the potential difference between the power supply potential and the node 1 is past the V _T of Q ₃ by an increase in the power supply potential
Since Q ₃ is turned on, it rises following the power supply. As a result, the node 1 is at a low level and the node 2 is at a high level, and the node 1 is stabilized. Thus, in the program circuit of the present embodiment,
An output corresponding to the cutting / non-cutting of the fuse is generated, and the output state when the fuse is not cut-off is inverted for a while, but is immediately changed to the corresponding state and fixed. Therefore, unlike the conventional example, the output inversion state does not continue for a long time, and no malfunction occurs. The third figure is shows an example of a power-on detection circuit which generates a one shot pulse at power-on, it is easy to see that the detection signal phi _V of Figure 1 shown is obtained. FIG. 2 is a circuit diagram of another embodiment of the present invention. The difference from the above-described embodiment is that the flip-flop 2
N-channel MO for resetting both inverters
It has SFETs Q ₄ and Q ₅ . For normal use, there is no problem if only the output of the inverter reset to load the fuse as the embodiment described above, by adding the Q _5, it is possible to further stabilize the program circuit of this type. That is, when the power supply potential decreases and rises due to the occurrence of noise after the power supply potential is already stabilized, the output signal φ of the power-on detection circuit
_When the level of _V rises and Q ₄ turns on, the potential at node 1 becomes
Becomes ground potential. In such a case, there is no problem when the fuse is cut in the circuit of FIG. 1, but when the fuse is connected, the data of the flip-flop may be inverted. On the other hand, in the circuit of FIG. 2, since Q ₅ is connected to the output node 2 of the CMOS inverters, nodes 1 and 2 becomes the ground potential simultaneously. When φ _V returns to the ground potential and Q ₄ and Q ₅ are turned off again, the potential of the node 1 rises faster than that of the node 2.
It becomes w and stabilizes with the original correct data latched. As described above, in this embodiment, a stable program circuit that can sufficiently cope with noise can be obtained. [Effects of the Invention] As described above, the present invention has a power-on detection circuit in a semiconductor integrated circuit having a program circuit using a fuse, receives an output signal from the circuit, and resets the program circuit. As a result, there is an effect that a malfunction of the program circuit, which easily occurs when the power is turned on, can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a program circuit of the present invention, FIG. 2 is a circuit diagram of a conventional program circuit, FIG. 3 is a circuit diagram showing an example of a power-on detection circuit, FIG. Is a circuit diagram showing a conventional example. F ₁ … Fuse, Q ₁ , Q ₂ , Q ₄ , Q ₅ , Q ₇ , Q ₈ , Q ₁₀ , Q ₁₂ … N-channel MOSFET, Q ₃ , Q ₆ , Q ₉ , Q ₁₁ … P-channel MOSFE
T, φ _{R ......} program circuit output signal, φ _{V ......} output signal of the power-on detection circuit.

Claims (1)

(57) [Claims] A fuse connected between the node and the first power supply terminal, a second power supply terminal to which a potential different from the first power supply terminal is supplied, and a first MOS transistor provided between the node. A first inverter and a second inverter composed of second and third MOS transistors connected in series between the first power supply terminal and the second power supply terminal in a flip-flop form; A control signal which is provided between the power supply terminal and the second power supply terminal and becomes an active level for a predetermined time when it detects that power is applied between the first power supply terminal and the second power supply terminal And a gate unit connected between the second power supply terminal and the node, the control signal being supplied to a control terminal, wherein the control signal is at the active level, Electrically connecting the second power supply terminal and the node The semiconductor integrated circuit of the program circuit; and a gate means for connecting.