JP3123058B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable circuit having a fuse for a semiconductor memory, and more particularly to a semiconductor memory having means for preventing a malfunction when the fuse is not completely cut.

[Conventional technology]

First, a conventional semiconductor memory will be described with reference to the drawings. FIG. 4 shows a programmable circuit having a fuse of a conventional semiconductor memory.

In FIG. 4, F is a fuse, 8, 9 are inverters, Q
_3, Q ₄ a connection point between the N-channel type MOS transistors, N ₁ is F and Q _3, phi is a clock signal to be described later, OUT is the output signal, the programmable circuit 3 is configured by the above.

Next, the operation of FIG. 4 will be described. Here, when the fuse F is not cut, it is assumed that the resistance value of the fuse F takes a value extremely smaller than the on-resistance values of the N-channel MOS transistors Q ₃ and Q ₄ . For example, Q _3, to the on-resistance value of the number KΩ of Q _4, the resistance value of the number 10Ω fuse F. First, if the fuse F is uncut, regardless of the level of the clock signal phi, the resistance ratio of F and Q ₂ and Q _3, the connection point N ₁ becomes high level.

Next, a case where the fuse F is cut will be described. First, in the case of an unstable state such as immediately after turning on the power, Q ₄
There until turned on, the connection point N ₁ becomes uncertain level. In particular, it is intended that the fuse F, if F is connected with a high resistance (a few ΜΩ~ number about G [Omega]), the connection point N ₁ with the rise of the power supply voltage is charged to the high level. In this case, N-channel MOS transistor Q ₄ is to be turned on, N ₁ is malfunctioning and confirm the high level is generated. Therefore, such is connected to N-channel MOS transistor Q ₃ in order to prevent a malfunction by temporarily high level clock signal phi, the Q ₂ is turned on, the connection point N ₁ low To If once N ₁ is the low level, the output of the inverter 8 becomes high level, because Q ₄ are turned on, a low level of N ₁ is determined. Here, if the Q ₃ is turned on, why N ₁ becomes low level, due to the resistance ratio of F and Q _3. As described above, the output OUT of the programmable circuit 3 goes high or low depending on whether the fuse F is cut or not. The clock signal φ is generated by a chip select internal signal 信号 (not shown), a write enable internal signal WE ′ (not shown), and the like. Therefore, N-channel type MOS
Despite may once after power to temporarily high gate input of the transistor Q _3, ▲
▼ and WE 'temporarily go high several times after power-on.

[Problem to be Solved by the Invention] The above-described conventional semiconductor memory has an N-type memory provided for correctly operating a programmable circuit having a fuse.
Since the channel-type MOS transistor is operated many times after the power is turned on, there is a disadvantage that current consumption is increased.

[Differences from the Prior Art of the Invention] In contrast to the conventional semiconductor memory described above, the present invention operates an N-channel MOS transistor provided for correctly operating a programmable circuit having a fuse only once after power-on. With the difference that

[Means for solving the problem]

A semiconductor memory according to the present invention has a first reset circuit that stores a predetermined level after power-on and is reset according to an external clock signal, and stores a predetermined level after power-on and responds to an inverted signal of the external clock signal. A reset circuit resetting the fuse, and a programmable circuit having a fuse, and outputting a fuse cut presence / absence signal of a first level when the fuse is cut, and a second level when the fuse is not cut. An N-channel type that is inserted between the fuse and GND and the output signal of either the first or second reset circuit is applied to the gate
A MOS transistor, and after the power is turned on, the first or the second
One of the reset circuits outputs a reset signal, thereby irrespective of the level of the external clock signal at the time of power-on, the N-channel type MOS transistor is turned on during the period from power-on to the first logic level change. It is characterized by conducting.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is an operation waveform diagram of the embodiment shown in FIG.

In FIG. 1, a programmable circuit 3 is a fourth conventional example.
Since it is the same as the figure, the description is omitted. The reset circuit 1 includes inverters 5 and 6, an N-channel MOS transistor Q ₁ having a write control signal WE ′ as a gate input, a capacitor C
Is composed of ₁ and C _2, the transistor size of the inverter 5, 6 WE 'reset signal RS1 Always when power is turned on in a low level state constitute a flip-flop circuit as a high level adjustment The coupling capacitors C ₁ and C ₂ for level stabilization are inserted. In exactly the same way, the reset circuit 2 includes the inverters 10, 1
1. N with write control signal ▲ ▼ as gate input
It consists of a channel type MOS transistor Q ₂ , capacitors C ₃ and C ₄ , and configures a flip-flop circuit so that the reset signal RS2 always goes to high level when power is turned on while ▲ ▼ is at low level Inverter 10,1
The transistor size of 1 is adjusted, and coupling capacitors C ₃ and C ₄ for level stabilization are inserted. 7 is O
In the R circuit, the above-mentioned reset signals RS1 and RS2 are input and the output is RS.
Input. ▲ ▼ Buffer circuit 4 is an inverter
The input is a write control external signal ▲ ▼, and the output is a write control internal signal ▲, W
E '.

Next, the operation of FIG. 1 will be described with reference to the waveform diagram of FIG. First, as shown in FIG.
When the power supply Vcc is turned on while ▼ is at the high level, the write control internal signal WE ′ remains at the low level.
The reset signal RS1 rises as shown in FIG. On the other hand, the write control internal signal ▲
▼ is high level as shown in the figure, N-channel type MOS
Transistor Q ₂ is turned on, RS2 is maintained at a low level. Accordingly, since the reset signal RS is an output of the OR circuit 7 having the inputs RS1 and RS2, the reset signal RS has a high level similarly to RS1. N-channel type MO with reset signal RS as input
S transistor Q ₃ are turned on, the connection point N ₁ of the fuse F and N-channel type MOS transistors Q _3, Q ₄ is at the high or low level in response to the presence or absence of cleavage of the fuses F as shown in FIG.

Next, when the write control external signal ▲ ▼ starts the first write operation changes to low level from high, WE 'becomes high level, the N-channel type MOS transistor Q ₁ is turned on, an inverter 5, 6 Flip
The flop is inverted, and the reset signals RS1 and RS go low. Therefore, the N-channel MOS transistor Q ₃
Turns off. Thereafter, regardless of the level of the write control external signal ▲ ▼, the reset signal RS1, RS2 and RS continues to maintain a low level, Q ₃ is turned on only when the power is turned on, keeps off thereafter.

Subsequently, when the power supply Vcc is turned on while ▲ is kept at the low level as shown in FIG. 2B, the operation of the reset circuit 2 enables completely the same operation as that of FIG. 2A. The description is omitted.

Embodiment 2 Next, another embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In FIG. 3, the reset circuits 1, 2 and the programmable circuit 3 are the same as those in FIG. 1 of the first embodiment of the present invention.
The description is omitted. The difference from FIG. 1 is that a ▲ ▼ buffer circuit 14 is provided instead of the ▲ ▼ buffer circuit.
This is constituted by inverters 15 and 16. Also,
The difference is that the gate inputs of the N-channel MOS transistors Q ₁ and Q ₂ are CS ′ and ▲ ▼, respectively.

Next, the operation of FIG. 3 is exactly the same as that of the first embodiment shown in FIGS. 1 and 2 except that WE ′ is replaced with CS ′ and ▲ ▼ is replaced with ▲ ▼. Omitted. This embodiment has an advantage that it can be applied to a semiconductor memory such as a ROM (read only memory) having no ▲ ▼ terminal.

〔The invention's effect〕

As described above, the present invention resets the programmable circuit including the fuse only during the period from when the power is turned on until the logic level of the external clock signal changes. There is an effect that can be done.

[Brief description of the drawings]

1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, FIG. 3 is a circuit diagram showing a second embodiment of the present invention, and FIG. FIG. 9 is a circuit diagram showing a conventional example. 1,2 ... reset circuit, 3 ... programmable circuit, 4
… ▲ ▼ buffer circuit, 5,6,8 to 13,15,16 …… inverter, 7… OR circuit, 14 …… ▲ ▼ buffer circuit,
Q _{1 to} Q ₄ … N-channel MOS transistors, C _{1 to} C ₄ …
… Capacitance, F… Fuse, N ₁ …… Node, ▲ ▼… Write control external signal, WE ', ▲ …… Write control internal signal, ▲ ▼… Chip select external signal, C
S ', ▲ ▼: Chip select internal signal, RS, RS1,
RS2: Reset signal, φ: Clock signal, OUT: Output signal.

Claims (2)

(57) [Claims] A first reset circuit for storing a predetermined level after power-on and resetting in response to an external clock signal; and a first reset circuit for storing a predetermined level after power-on and resetting in response to an inverted signal of the external clock signal A second reset circuit, and a fuse, wherein the first level is provided when the fuse is blown, and the second level is provided when the fuse is not blown.
And a N-channel type wherein a programmable circuit which outputs a signal indicating whether a fuse has been blown at a level of at least one of the first and second reset circuits inserted between the fuse and GND is applied to a gate. A MOS transistor, and either one of the first or second reset circuit outputs a reset signal in response to a first logical level change of the external clock signal after power-on, so that the external circuit at power-on is output. A semiconductor memory in which the N-channel MOS transistor is turned on during a period from power-on to the first change in logic level, regardless of the level of a clock signal. 2. A first reset circuit which is reset in response to power-on and is set in response to one logic level of a control signal, and the other logic level of said control signal which is reset in response to power-on and reset A second reset circuit that is set in response to a fuse, one end of which is connected to the first power supply potential, and the other end of which is connected to the second power supply potential and the fuse is disconnected. Means for setting an output signal to the second power supply potential and setting the output signal to the first power supply potential when the fuse is not blown; and connecting the other end of the fuse to the second power supply potential. A transistor provided between the transistors, the transistor being turned on in response to at least one of the first and second reset circuits being reset.