JPH1131956A - Reset signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To securely prevent a power-on reset circuit from being initialized undesirably. SOLUTION: For example, two voltage level detecting circuits 11 and 12 having different voltage detection levels are prepared; and the detection signal OUT 11 of the voltage level detecting circuit 11 having a higher voltage detection level is connected to the reset input of a latch circuit 21 and the detection signal OUT 12 of the voltage level detecting circuit 12 having a lower voltage detection level is inputted to the set input. The output OUT 21 of the latch circuit 21 is used as a power-on reset signal PONRST. Consequently, the circuit can be reset continuously until the high voltage is reached when the power source is turned on, and is not reset until a voltage which is low to a no- operation-hindrance extent is reached when the source voltage drops.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset signal generating circuit, and more particularly to a reset signal generating circuit for use in a power-on reset circuit of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Generally, when operating a semiconductor integrated circuit device (hereinafter simply referred to as an LSI (Large Scale Integrated circuit)), first, the output of an internal circuit such as a latch or a register in the LSI is set to a logical level. "1" for
Alternatively, an initialization (reset) operation of setting to either “0” is performed.

Usually, a dedicated terminal for an initialization operation is prepared, and an initialization signal (for example, a reset signal) is supplied to the terminal from an external device or device of the LSI to thereby initialize the internal circuit. Alternatively, it is detected that the power supply voltage is supplied to the LSI, and an initialization signal is generated inside the LSI in synchronization with the power-on, thereby performing the initialization operation of the internal circuit. (So-called power-on-reset).

Conventionally, a power-on reset circuit using a voltage level detection circuit has been mainly used as a circuit for realizing an initialization operation by the latter power-on reset.

[0005] This is an environment in which the rise time of the power supply voltage at power-on uses an LSI, that is, the capacity of a power supply line such as a board or a set, a power supply for supplying the power supply voltage or a power supply IC (Integrated Circuit). / LS
Due to the characteristics of I (current supply capability, etc.), the power supply voltage extends over a wide time range from the order of μsec to several hundred msec, so that the power supply voltage does not reach the set voltage detection level regardless of the rise time of the power supply voltage. This is because it is necessary to reliably output a power-on reset signal during the period.

In addition, in the case of this power-on reset circuit, in order to ensure that the initializing operation is performed even at a low voltage in the course of a voltage rise at the time of turning on the power, a voltage until the voltage is increased to a higher voltage is required. For a while, it was necessary to output the power-on reset signal.

FIG. 11 shows a case where a power-on reset circuit is constructed using the above-described voltage level detection circuit.
It shows a relationship between a power supply voltage and a power-on reset signal.

In the power-on reset circuit in this case, as shown in FIGS. 1A and 1B, the power-on reset signal is output for a longer time as the rise of the power supply voltage VDD is slower. Will be done.

However, the above-described conventional power-on reset circuit has a voltage detection level fixed at a certain value (one point), and is intended to ensure that the initialization operation is performed when the power is turned on. When the voltage detection level is set higher, for example, as shown in FIG. 12, the power supply voltage VDD temporarily lowering during operation of the data signal output circuit or the like, and the power supply voltage VDD lower than the above voltage detection level
'Causes a power-on-reset signal to be erroneously output, causing an unintended initialization operation.

On the other hand, if the voltage detection level is set lower to avoid erroneous output of the power-on reset signal of the power-on reset circuit as described above,
For example, in the case where the power-on voltage VDD rises quickly and the output of the power-on reset signal is cut off before the initialization operation of all the internal circuits is insufficient, the initialization at power-on is performed. There is a problem that the operation is not executed reliably.

[0011]

As described above, in the prior art, if the voltage detection level is set to a high level, an undesired initialization operation may be performed, and conversely, the voltage detection level is set to a low level. Then, there is a problem that the initialization operation at the time of turning on the power is not performed reliably.

Therefore, the present invention provides a reset signal generating circuit which can reliably prevent an unintended initialization operation from being performed and can surely execute the initialization operation when power is turned on. It is intended to provide.

[0013]

In order to achieve the above object, in a reset signal generating circuit according to the present invention, the reset signal generating circuit is provided until a power supply voltage in a semiconductor integrated circuit device reaches a first detection level. First output of reset signal for initializing internal circuit of semiconductor integrated circuit device
And second output means for outputting the reset signal after the power supply voltage reaches a second detection level different from the first detection level.

Further, in the reset signal generating circuit of the present invention, when the rise of the power supply voltage in the semiconductor integrated circuit device is equal to or lower than the first detection level, the reset is detected and the first signal is detected.
A first voltage level detection circuit that outputs a detection signal of the first detection level and a second detection level when the fall of the power supply voltage is equal to or lower than a second detection level different from the first detection level. A second voltage level detection circuit for outputting a signal, a reset input signal using the first detection signal as a set input signal, and an initialization operation of an internal circuit of the semiconductor integrated circuit device using the second detection signal as a set input signal. And a latch circuit composed of a flip-flop that outputs a reset signal.

Further, in the reset signal generating circuit according to the present invention, when the rise of the power supply voltage in the semiconductor integrated circuit device is equal to or lower than the first detection level, it is detected and the first detection signal is output. A voltage level detection circuit for detecting when the power supply voltage falls below a second detection level different from the first detection level and outputting a second detection signal; A latch circuit composed of a flip-flop for outputting a reset signal for initializing an internal circuit of the semiconductor integrated circuit device using the detection signal as a reset input signal and the second detection signal as a set input signal. ing.

According to the reset signal generation circuit of the present invention, it is possible to provide a difference (so-called hysteresis characteristic) to the voltage at which the power-on reset signal is generated when the power supply voltage rises and falls. . This makes it possible to continue resetting when the power is turned on until a higher voltage is reached, and to prevent the reset from being applied when the power supply voltage falls to a low voltage that does not hinder operation. It is possible.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a power-on reset circuit according to a first embodiment of the present invention.

The reset circuit includes, for example, a first voltage level detection circuit 11 and a second voltage level detection circuit 1
2, and a latch circuit 21 composed of a flip-flop
It consists of.

The first voltage level detection circuit 11 has a first voltage detection level V _H , for example, as shown in FIG. 2, and has a power supply voltage V _H in a semiconductor integrated circuit device (LSI).
DD is so when: the first voltage detection level V _H, and outputs a first detection signal OUT 11 detects it.

The second voltage level detecting circuit 12, for example, as shown in FIG. 3, a second voltage detection level V _L lower than the first voltage detection level V _H, the LSI
When the power supply voltage VDD is equal to or lower than the second voltage detection level _VL , it is detected and a second detection signal OUT12 is output.

As shown in FIG. 4, for example, the latch circuit 21 receives the first detection signal OUT11, which is the output of the first voltage level detection circuit 11, as a reset input signal, and outputs the second voltage level detection circuit 12 Output signal of the second detection signal OU
T12 is a set input signal, and a signal (power-on reset signal PONRST) for initializing the internal circuit of the LSI is generated as an output (OUT21).

That is, the first and second voltage level detection circuits 11 and 12 both supply the power supply voltage VDD of the first and second voltage levels.
Below the voltage detection levels V _H and V _L , a signal of the power supply voltage VDD level and the first and second voltage detection levels V
_{When the} voltage becomes higher than _H and _VL , signals of GND level due to ground are output as first and second detection signals OUT11 and OUT12, respectively.

On the other hand, the latch circuit 21 is set by the second detection signal OUT12, which is the output of the second voltage level detection circuit 12, when the power supply voltage VDD is turned on. Is output as the power-on reset signal PONRST.

When the power supply voltage VDD exceeds the second voltage detection level V _L , the second detection signal OUT12 output from the second voltage level detection circuit 12 changes from the level of the power supply voltage VDD to the ground potential GND. It switches to the level signal,
The latch circuit 21 receives the power-on reset signal PONRST
Is maintained at the power supply voltage VDD level.

Furthermore, the power supply voltage VDD rises over time, exceeds a first voltage detection level V _H, the first detection signal OUT 11 is the power supply voltage is the output of the first voltage level detecting circuit 11 From the level of VDD to the ground potential GND
By switching to the level signal, the latch circuit 21
Is reset, and outputs a signal at the ground potential GND level as the power-on reset signal PONRST.

When the power supply voltage VDD is higher than the first voltage detection level V _H , the latch circuit 21 retains the previous state, so that the power-on reset signal PONRST
At the ground potential GND level.

On the other hand, when the power supply voltage VDD falls after exceeding the first voltage detection level V _H , the power supply voltage V
When the DD decreases and becomes lower than the first voltage detection level V _H , the first voltage level output from the first voltage level detection circuit 11
Is switched from the signal at the ground potential GND level to the signal at the power supply voltage VDD level.

However, in this case, the first detection signal
Even if OUT 11 is switched to a signal at the level of the power supply voltage VDD, the latch circuit 21 is not affected at all. However, when the power supply voltage VDD further decreases and becomes lower than the second voltage detection level _VL , the second detection signal OUT12 output from the second voltage level detection circuit 12 becomes the ground potential GN.
The signal switches from the D level signal to the power supply voltage VDD level signal.

As a result, the latch circuit 21 is set, and the power-on reset signal PONRST is supplied to the ground potential GN.
Switching from the D level to the signal of the power supply voltage VDD level enables the initialization operation of the internal circuit of the LSI.

As described above, the power-on reset signal PONRST having a so-called hysteresis characteristic is different in the voltage at which the reset signal is output when the power supply voltage VDD increases and when the power supply voltage VDD decreases. -The reset circuit can be realized with a simple circuit configuration.

As a result, the power-on reset signal PO
By giving the NRST a hysteresis characteristic, for example, the power supply voltage VDD may be instantaneously reduced during the operation of the LSI (the power supply voltage _VH may be lower than the first voltage detection level VH).
Even when DD ′) occurs, it is possible to prevent the power-on reset signal PONRST from being output erroneously and performing an undesired initialization operation.

That is, once the power supply voltage VDD rises to the specified power supply voltage once after the power is turned on, the power-on reset is performed as long as the power supply voltage VDD does not drop below the second voltage detection level _VL. The signal PONRST is not output. For this reason, the second voltage detection level V _L is set at the very lower limit of the power supply voltage VDD at which the LSI can operate, and the first voltage detection level V _H is the lower limit of the voltage range that guarantees the operation. It is desirable to set the voltage slightly lower than that.

This makes it possible to continue resetting to a higher voltage when the power is turned on.
Can be reliably executed. Conversely, when the voltage drops, erroneous output of the power-on-reset signal PONRST due to fluctuations in the power supply voltage VDD can be prevented, and the output of the power-on-reset signal PONRST is sufficient to hinder the operation of the LSI. Power supply voltage VDD
Is reduced, that is, only when it is really necessary to reset, it is possible to realize an LSI with high circuit operation reliability.

FIG. 5 shows a specific example of the configuration of the above-mentioned power-on reset circuit. The first voltage level detection circuit 11 includes a power supply voltage VDD and a ground potential GND.
Between the two N-channel type M via a resistor 11a.
OS (Metal Oxide Semiconductor) transistor 11
b and 11c are connected in series. The gates of the transistors 11b and 11c are connected to the respective drains.

The connection point (node) 11d between the transistor 11b and the resistor 11a is connected to the gate of a P-channel MOS transistor 11e, and the source of the transistor 11e is connected to the power supply voltage VDD.

The drain of the transistor 11e is connected to the ground potential GND via the resistor 11f. Further, the transistor 11e and the resistor 1
The waveform shaping circuit 1 is connected to a connection point (node) 11g with 1f.
The reset input terminal of the latch circuit 21 is connected via 1h.

The second voltage level detection circuit 12 has an N-channel MOS transistor 12b connected between the power supply voltage VDD and the ground potential GND via a resistor 12a. The gate of the transistor 12b is connected to the drain.

The connection point (node) 12c between the transistor 12b and the resistor 12a is connected to the gate of a P-channel MOS transistor 12d, and the source of the transistor 12d is connected to the power supply voltage VDD.

The drain of the transistor 12d is connected to the ground potential GND via the resistor 12e. Further, the transistor 12d and the resistor 1
The waveform shaping circuit 1 is connected to a connection point (node) 12f with 2e.
The set input terminal of the latch circuit 21 is connected via 2g.

The waveform shaping circuit 11h of the first voltage level detecting circuit 11 and the waveform shaping circuit 12g of the second voltage level detecting circuit 12 both have a rapid rise of the power supply voltage VDD when the power is turned on. In such a case, signals of appropriate lengths are obtained as the first and second detection signals OUT11 and OUT12.
For example, the configuration is such that delay circuits composed of the inverter INV and the capacitor C are prepared for the number of stages corresponding to the polarities of the first and second detection signals OUT11 and OUT12.

The latch circuit 21 outputs, for example, a first detection signal OU output from the first voltage level detection circuit 11.
Inverter 21 as reset input to which T11 is supplied
a, an OR circuit 21b to which the output of the inverter 21a is supplied to one input, the second voltage level detecting circuit 1
The second detection signal OUT12 which is the output of the OR circuit 21c is supplied to one input (set input), and an inverter 21d to which the output of the OR circuit 21c is supplied is a flip-flop type. It has become.

The output of the OR circuit 21c is input to the other input of the OR circuit 21b.
The output of the OR circuit 21b is supplied to the other input of 1c.

The output characteristics and operation timing of each circuit in the above configuration will be described with reference to FIG. In the first voltage level detection circuit 11, the transistors 11b and 11c are connected to the potential V 1 of the connection point 11d.
1d, the potential V 11j of the connection point 11j is the transistor 11b,
When the threshold values Vth 11b and Vth 11c are equal to or larger than Vth 11b (V11d ≧ Vth11b, V11j ≧ Vth11c)
And turn them on.

The transistor 11e has a potential V 11d at a connection point 11d which is a gate input of the transistor 11e.
Is smaller than or equal to the threshold Vth 11e of the transistor 11e (| Vth 11e | ≧ V 11d).

The transistors 11b and 11c and the power supply voltage V
Since there is a resistor 11a between the DD, although a slight deviation due to the resistance value occurs, as a result, the transistor 11e is the power supply voltage VDD becomes equal to or higher than the first voltage detection level _{V H (Vth 11b + Vth 11c} + Vth 11e ≧ V
_H ) to turn on, and change the potential V 11g of the connection point 11g from the power supply voltage VDD to a level close to the ground potential GND.

As a result, the first voltage level detection circuit 1
1, the power supply voltage VDD is when the following first voltage detection level V _H supply voltage VDD as a first detection signal OUT 11
When the signal reaches the first voltage detection level _VH or higher, a signal at the ground potential GND level is output.

On the other hand, in the second voltage level detection circuit 12, the transistor 12b is connected to the potential V 12c of the connection point 12c.
Is higher than or equal to the threshold value Vth 12b of the transistor 12b (V 12c ≧ Vth 12b).

The transistor 12d has a potential V 12c at a connection point 12c which is a gate input of the transistor 12d.
Is equal to or smaller than the threshold value Vth 12d of the transistor 12d (| Vth 12d | ≧ V 12c).

Since the resistor 12a exists between the transistor 12b and the power supply voltage VDD, a slight shift occurs due to the resistance value.
2d turns on when the power supply voltage VDD becomes equal to or higher than the second voltage detection level _VL (Vth12b + Vth12d ≧ _VL ), and changes the potential V12f of the connection point 12f from the power supply voltage VDD to the ground potential G.
Change to a level close to ND.

Thus, the second voltage level detection circuit 1
2 is the power supply voltage VDD as the second detection signal OUT12 when the power supply voltage VDD is equal to or lower than the second voltage detection level _VL.
When the level signal becomes equal to or higher than the second voltage detection level _VL , a signal at the ground potential GND level is output.

The latch circuit 21 is set by the rising of the second detection signal OUT12, which is the output of the second voltage level detection circuit 12, when the voltage rises, such as when the power is turned on, and the first voltage level detection circuit The signal is reset by a signal triggered by the fall of the first detection signal OUT11, which is the output of the first detection signal OUT11.

Also, when the voltage drops, the second detection signal OUT12 from the second voltage level detection circuit 12 does not depend on the rising of the first detection signal OUT11 from the first voltage level detection circuit 11. Reset by rising.

As a result, the latch circuit 21 outputs, as its output (OUT 21), a power circuit having a hysteresis characteristic.
An on-reset signal PONRST can be generated.

In this power-on reset circuit, the first and second voltage level detection circuits 11 and 12 have basically the same configuration, and the first voltage level detection circuit 11
Only by adding the transistors 11c, by setting the voltage detection level V _H of the higher, so as produce a difference voltage detection level of the lower voltage detecting level V _L of the.

As a result, the hysteresis width can be made more stable as compared with the case where the difference in voltage detection level is obtained by making the circuit configuration different, and the design change due to the fluctuation of the manufacturing process can be prevented. It is possible to realize a power-on reset circuit that can easily and reliably operate.

According to the above configuration, the detection signals of the two voltage level detection circuits 11 and 12 having different voltage detection levels are provided.
Of the output signals OUT11 and OUT12, the detection signal OUT12 having the lower voltage detection level is set as the set signal, and the detection signal OUT11 having the higher voltage detection level
Is used as a power-on reset signal PONRST.

For this reason, the voltage at which the reset signal is output differs between when the power supply voltage VDD rises and when the power supply voltage VDD falls, that is, when the power-on reset signal PONRST having a so-called hysteresis characteristic can be output. The reset circuit can be realized with a simple circuit configuration.

As a result, when the power is turned on, it is possible to continue resetting to a higher voltage, so that a more reliable initialization operation can be realized. Further, as a result that the voltage detection level V _L for generating the reset signal at the time of power supply falling can be reduced to near the lower limit of the power supply voltage VDD so as not to hinder the operation of the LSI, for example, FIG. As shown, the instantaneous decrease in the power supply voltage VDD (the first voltage detection level V _H) caused by the influence of switching of the data output during the operation of the LSI, etc.
Erroneous output of the power-on reset signal PONRST due to the power supply voltage VDD ′) lower than the power supply voltage VDD ′) can be prevented.

[0059] Similarly, at the time of power-on, rises while waving with a power supply voltage VDD, a even when the back and forth up and down of the first voltage detection level V _H, the power
The disadvantage that the ON / reset signal PONRST is output many times can be solved.

As described above, the voltage at which the power-on reset signal is generated can be made different when the power supply voltage rises and falls. That is, two voltage level detection circuits having different voltage detection levels are prepared, and a detection signal of a voltage level detection circuit having a lower voltage detection level is set as a set signal, and a detection signal of a voltage level detection circuit having a higher voltage detection level is generated as a signal. The output of the latch circuit as a reset signal is used as a power-on reset signal.

As a result, the lower voltage detection level becomes L
The power is turned on by setting the power supply voltage close to the lower limit of the power supply voltage at which SI operation is possible, and setting the higher voltage detection level to a voltage slightly lower than the lower limit of the voltage range that guarantees operation. In some cases, resetting can be continued until the voltage becomes higher, and when the power supply voltage falls, resetting can be prevented until the voltage becomes low enough to not hinder the operation.

Therefore, when the power is turned on, the reset can be continuously performed until the initialization operation is performed. When the voltage drops, the reset can be performed only when the initialization operation is required, and the LSI can be reset. The initialization operation of the internal circuit of the
Even when a momentary drop in the power supply voltage occurs during the operation of the LSI, it is possible to prevent a power-on-reset signal from being output by mistake and performing an undesired initialization operation. It is possible.

Further, as the voltage level detection circuits having different voltage detection levels, the number of transistors of the circuit having the same configuration is changed, and the difference between the voltage detection levels is obtained by using the threshold value of the difference transistor. I have. Therefore, the difference between the voltage detection levels can always be set to a predetermined value (the number of transistors × the threshold).

Therefore, the hysteresis width can be made more stable as compared with the case where the difference in voltage detection level is obtained by making the circuit configuration different, and the design can be made irrespective of the variation of the manufacturing process. It is possible to realize a power-on-reset circuit that can easily and reliably operate.

In the above-described first embodiment of the present invention, the case where the voltage level detecting circuit is constituted by using a transistor and a resistor has been described as an example.
However, the present invention is not limited to this. For example, as shown in FIG.

That is, the power-on-reset circuit according to the second embodiment of the present invention is, for example, the power-on-reset circuit shown in FIG. Resistor 11a is a P-channel type MO
The S transistor 11a 'and the resistor 11f are replaced with an N-channel MOS transistor 11f' to form a first voltage level detection circuit 11 '. Similarly, the resistance of the second voltage level detection circuit 12 is changed. 12
a is a P-channel MOS transistor 12a ', and a resistor 12e is an N-channel MOS transistor 12a'.
e 'is replaced with the second voltage level detection circuit 12', so that the first and second voltage level detection circuits 11 'and 12' can be used without using a resistor.
It is configured to include only transistors.

The power-on reset circuit is not limited to the case where voltage level detection circuits having different voltage detection levels are individually prepared. For example, the power-on reset circuit includes one voltage level detection circuit and one latch circuit. It is also possible to configure an on-reset circuit.

FIG. 9 shows a schematic configuration of a power-on reset circuit according to a third embodiment of the present invention. That is, the reset circuit includes, for example, the second voltage level detection circuit 12 'in the power-on reset circuit shown in FIG. 8 and the output (first detection signal OUT12) of the voltage level detection circuit 12'. ') Is supplied as a reset input to one input of the OR circuit 21b,
The P-channel MOS transistor 12a 'and the N-channel MOS transistor of the voltage level detection circuit 12'
Connection point (node) between transistor 12b (node) 12c and P-channel MOS transistor 12d
And a latch circuit 21 'in which a potential of 12h (second detection signal OUT 12'') is supplied as a set input to one input of an OR circuit 21c.

In the case of this reset circuit, the transistor 12b is connected to the potential V 12h of the connection point 12h by the transistor 1
When the voltage becomes equal to or higher than the threshold value Vth 12b (second detection level) of 2b, it turns on, and the potential V 12h of the connection point 12h is set to the “L” level.

The transistor 12d is turned on when the potential V 12h at the connection point 12h becomes equal to or higher than the sum (first detection level) of the threshold values Vth 12b and Vth 12d of the transistors 12b and 12d. The potential V 12f is set to “H”
To level.

As a result, for example, as shown in FIG.
When the voltage rises, such as when the power is turned on, the latch circuit 21 '
Is set by the rising edge of the second detection signal OUT12 ″, and is reset by the signal triggered by the falling edge of the first detection signal OUT12 ′.

When the voltage drops, the first detection signal OU
Regardless of the rise of T12 ', the output (OU) is reset by being reset by the rise of the second detection signal OUT12''.
As T21 ′), a power-on reset signal PONRST having hysteresis characteristics can be generated.

In the case of the power-on reset circuit having the configuration according to the third embodiment, only one voltage level detection circuit is required, so that the operation is smaller than that of the reset circuit having the configuration according to the first or second embodiment. This method is particularly suitable when applied to an LSI that requires a small current flow and consumes low current. Of course, various modifications can be made without departing from the scope of the present invention.

[0074]

As described above, according to the present invention, it is possible to reliably prevent an unintended initialization operation from being performed, and to ensure that the initialization operation is performed when the power is turned on. And a reset signal generation circuit capable of performing the operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a power-on reset circuit according to a first embodiment of the present invention.

FIG. 2 is an output characteristic diagram for explaining the operation of the first voltage level detection circuit.

FIG. 3 is an output characteristic diagram for explaining the operation of the second voltage level detection circuit.

FIG. 4 is an output characteristic diagram for explaining the operation of the latch circuit.

FIG. 5 is a schematic diagram specifically illustrating a configuration of a power-on reset circuit.

FIG. 6 is a schematic diagram similarly illustrating the timing of such an operation.

FIG. 7 is a schematic view similarly illustrating the operation.

FIG. 8 is a schematic diagram showing another configuration example of the power-on reset circuit according to the second embodiment of the present invention.

FIG. 9 is a schematic diagram showing another configuration example of the power-on reset circuit according to the third embodiment of the present invention.

FIG. 10 is a schematic view similarly illustrating the operation.

FIG. 11 is an output characteristic diagram shown to explain the operation of the voltage level detection circuit to explain the related art and its problems.

FIG. 12 is an output characteristic diagram for explaining the operation of the conventional power-on reset circuit.

[Explanation of symbols]

11, 11 '... first voltage level detection circuit 11a, 11f ... resistors 11b, 11c, 11f' ... N-channel MOS transistors 11d, 11g, 11j ... connection points 11a ', 11e ... P-channel MOS transistors 11h ... waveform Molding circuit INV Inverter C Capacitor 12, 12 'Second voltage level detection circuit 12a, 12e Resistor 12b, 12e' N-channel MOS transistor 12c, 12f, 12h Connection point 12a ', 12d P channel Type MOS transistor 12g Waveform shaping circuit 21, 21 'Latch circuit 21a, 21d Inverter 21b, 21c OR circuit _VH ... First voltage detection level _VL ... Second voltage detection level VDD, VDD' ... Power supply Voltage GND: Ground potential OUT11: First detection signal OUT12: Second detection signal PONRST … Power-on reset signal

Claims (8)

[Claims] A first output means for outputting a reset signal for initializing an internal circuit of the semiconductor integrated circuit device until a power supply voltage of the semiconductor integrated circuit device reaches a first detection level; A second power supply voltage different from the first detection level;
And a second output means for outputting the reset signal after reaching the detection level. A first voltage level detecting circuit for detecting a rise in the power supply voltage and outputting a first detection signal when the rise in the power supply voltage is equal to or lower than a first detection level; A latch circuit for taking in the first detection signal as a reset input signal.
2. The reset signal generation circuit according to 1. A second voltage level detecting circuit for detecting when the power supply voltage falls below a second detection level, and outputting a second detection signal; 2. The reset signal generation circuit according to claim 1, further comprising: a latch circuit that receives the second detection signal as a set input signal. 4. A first detection level of the first voltage level detection circuit is set higher than a second detection level of the second voltage level detection circuit by a threshold value of at least one transistor. 4. The reset signal generation circuit according to claim 2, wherein 5. A first detection level of the first voltage level detection circuit is set to a voltage value lower than a lower limit of a power supply voltage range that guarantees an operation, and a second detection level of the second voltage level detection circuit is set to a second voltage level. 4. The reset signal generation circuit according to claim 2, wherein the detection level is set to a lower limit of a power supply voltage at which the semiconductor integrated circuit device can operate. 6. The first and second output means detects when the rise of the power supply voltage is equal to or lower than a first detection level, outputs a first detection signal, and outputs the power supply voltage. A voltage level detection circuit for detecting when the falling of the first detection signal is lower than or equal to a second detection level and outputting a second detection signal; a reset input signal for the first detection signal; 2. The reset signal generating circuit according to claim 1, further comprising: a latch circuit for taking in as a set input signal. 7. A first voltage level detection circuit for detecting a rise of a power supply voltage in a semiconductor integrated circuit device when the rise in power supply voltage is equal to or lower than a first detection level and outputting a first detection signal; Is lower than or equal to a second detection level different from the first detection level, the second detection level is detected and the second detection level is detected.
A second voltage level detection circuit that outputs a detection signal of the following: an operation of initializing an internal circuit of the semiconductor integrated circuit device by using the first detection signal as a reset input signal and the second detection signal as a set input signal And a latch circuit comprising a flip-flop for outputting a reset signal for causing the reset signal to be generated. 8. When the rise of the power supply voltage in the semiconductor integrated circuit device is equal to or lower than a first detection level, it detects the rise and outputs a first detection signal. A voltage level detection circuit for detecting a second detection signal when the detection level is equal to or lower than a second detection level different from the detection level, and outputting a second detection signal; a reset input signal for the first detection signal; A reset signal generation circuit, comprising: a latch circuit composed of a flip-flop that outputs a reset signal for performing an initialization operation of an internal circuit of the semiconductor integrated circuit device using the signal as a set input signal.