JP2019129426A - Semiconductor device and generation method for reset signal - Google Patents

Abstract

PURPOSE: To provide a semiconductor device and generation method for reset signal, capable of resetting flip-flop included in a circuit configuration part according to power activation without causing a malfunction in the circuit configuration part.CONSTITUTION: The semiconductor device includes: a power-on reset part for generating a reset signal with a first level urging resetting during a rise period of a power supply voltage according to power activation; a circuit configuration part whose circuit is comprised of a plurality of circuit elements including flip-flop reset according to a reset signal. The power-on reset part detects whether or not the circuit elements properly operate according to power activation and when a proper operation of the circuit elements is detected, transits the reset signal to a second level urging a reset release from a state of a first level.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a power-on reset unit that generates a reset signal in response to power-on, and a reset signal generation method.

  A semiconductor device including a circuit configuration part in which a digital circuit is constructed by a plurality of circuit elements is provided with a power-on reset circuit that initializes a state of a flip-flop as a circuit element when power is turned on.

  As such a power-on reset circuit, it maintains a low level state that prompts resetting immediately after the power is turned on, and transitions to a high level that prompts reset release when the voltage value reaches a predetermined voltage value due to a rise in power supply voltage A circuit for generating a reset signal is proposed (for example, see Patent Document 1). The reset signal is supplied to the reset terminal of each flip-flop included in the circuit configuration. Thus, each flip flop resets its own state while the reset signal is at the low level.

JP 2007-81533 A

  However, due to variations in the manufacture of semiconductor devices, the reset signal is generated before the voltage value reaches the voltage value at which the circuit elements (including flip-flops) can operate in the rise period of the power supply voltage immediately after the power is turned on. There was a case that the transition to the level to release the reset state. At this time, since the reset value is released and the voltage value of the power supply voltage reaches the voltage value at which the circuit element can operate, an erroneous output is made from each circuit element, so that the circuit configuration unit malfunctions. The problem that there is a possibility of doing.

  An object of the present invention is to provide a semiconductor device capable of resetting a flip flop included in a circuit component in response to power on without causing a malfunction in the circuit component, and a method of generating a reset signal. And

  A semiconductor device according to the present invention includes a power on reset unit generating a reset signal having a first level for prompting reset in a rise period of a power supply voltage according to power on, and a flip flop reset according to the reset signal. And the power-on reset unit detects whether or not the circuit element has operated normally in response to the power-on. The reset signal is transitioned from the state of the first level to a second level prompting release of reset when it is detected that the circuit element operates normally.

  A method of generating a reset signal according to the present invention is a method of generating a reset signal having a first level for prompting a reset in a rising period of a power supply voltage according to power on, the method including the reset signal In response to detecting whether or not the circuit element included in the circuit configuration unit in which the circuit is configured by a plurality of circuit elements including flip-flops to be reset operates normally, the circuit element is detected to be operating normally In some cases, the reset signal is transitioned from the state of the first level to a second level urging release of reset.

  In the present invention, the state of the reset signal generated in response to the power-on is transitioned from the state prompting the reset to the state prompting the release of the reset after it is detected that the circuit elements included in the semiconductor device operate normally. This makes it possible to reset the state of the flip-flops included in the circuit component in response to power on without causing a malfunction in the circuit component.

FIG. 2 is a circuit diagram showing a circuit configuration unit 10 and a power on reset unit 20 included in a semiconductor IC chip 100. It is a figure showing the truth table of RSFF23. 5 is a time chart illustrating the operation of the power on reset unit 20. FIG. FIG. 16 is a circuit diagram showing a modification of the circuit configuration unit 10 and the power on reset unit 20 included in the semiconductor IC chip 100. FIG. 16 is a circuit diagram showing another modification of the circuit configuration unit 10 and the power on reset unit 20 included in the semiconductor IC chip 100. 3 is a circuit diagram showing a configuration of a trimming circuit 29. FIG. It is a figure showing an example of the correspondence of trimming code TMC and the voltage value of 2nd threshold voltage Vt2.

  FIG. 1 is a circuit diagram showing a circuit configuration unit 10 and a power-on reset unit 20 included in a semiconductor IC chip 100 as a semiconductor device.

  The circuit configuration unit 10 includes various flip-flops (hereinafter referred to as FFs) such as JK, RS, T, and D types, various logic gates such as AND gates, OR gates, and inverters, and various circuit elements such as memories. The circuit of FIG.

  The power-on reset unit 20 generates a reset signal RES that has, for example, a logic level 0 that prompts resetting during the rising period of the power supply voltage VDD in response to power-on, and then transitions to a logic level 1 state that prompts reset cancellation. . The power-on reset unit 20 supplies the reset signal RES to reset terminals of a plurality of FFs with reset terminals (including FF 12) included in the circuit configuration unit 10 via the reset wiring LR.

  As shown in FIG. 1, the power on reset unit 20 includes comparators 21 and 22, an RS flip flop 23 (hereinafter, referred to as RSFF 23), an AND gate 24, and an inverter 25.

  The comparator 21 determines whether the voltage value of the power supply voltage VDD is equal to or higher than a predetermined first threshold voltage Vt1. The first threshold voltage Vt1 has a voltage value lower than the rated voltage value of the power supply voltage VDD. When the comparator 21 determines that the voltage value of the power supply voltage VDD is equal to or higher than the first threshold voltage Vt1, the comparator 21 determines that the voltage value of the power supply voltage VDD is not equal to or higher than the first threshold voltage Vt1. A first power supply voltage determination signal D1 having a logic level 0 is generated. The comparator 21 supplies the power supply voltage determination signal D1 to the AND gate 24.

  The comparator 22 determines whether the voltage value of the power supply voltage VDD is equal to or higher than a predetermined second threshold voltage Vt2. The second threshold voltage Vt2 is lower than the first threshold voltage Vt1 and has a voltage value equal to or higher than the lower limit value of the power supply voltage VDD capable of operating each circuit element.

  The comparator 22 has a logic level 0 when it is determined that the power supply voltage VDD is not equal to or higher than the second threshold voltage Vt2, and has a logic level 1 when it is determined that the power supply voltage VDD is equal to or higher than the second threshold voltage Vt2. 2 power supply voltage determination signal D2 is generated. The comparator 22 supplies the generated power supply voltage determination signal D2 to the inverted R terminal of the RSFF 23.

  The inverter 25 receives an output signal of a specific one of the plurality of circuit elements included in the circuit configuration unit 10, and generates a signal obtained by inverting the logic level of the output signal as an operation detection signal BC, This is supplied to the AND gate 24. That is, the inverter 25 detects whether or not this circuit element is operating normally after turning on the power based on the output signal of this one specific circuit element, and generates an operation detection signal BC indicating the detection result. To do.

  In the embodiment shown in FIG. 1, the inverter 25 receives the output signal of the FF 12 that is the FF with reset terminal among the plurality of circuit elements included in the circuit configuration unit 10 and inverts the logic level of the output signal. The generated signal is generated as an operation detection signal BC.

  That is, when the voltage value of the power supply voltage VDD after power on is equal to or higher than the voltage value that allows the FF 12 to operate normally, the FF 12 resets its own state in response to the reset signal RES of logic level 0. To do. Therefore, the level of the output signal of the FF 12 becomes the logic level 0 by the reset. On the other hand, when the voltage value of the power supply voltage VDD after the power-on is lower than the voltage value that allows the FF 12 to operate normally, the FF 12 does not reset even if the reset signal RES of logic level 0 is supplied. Therefore, at this time, the level of the output signal of the FF 12 is in an indeterminate state.

  Therefore, the inverter 25 detects that the FF 12 is operating normally when the level of the output signal of the FF 12 is the logic level 0 that is output when the FF 12 is reset, and has a logic level 1 representing normal operation. An operation detection signal BC is supplied to the AND gate 24.

  When the power supply voltage determination signal D1 has the logic level 1 and the operation detection signal BC is the logic level 1 indicating the normal operation of the FF 12, the AND gate 24 has the logic level 1 reset release signal indicating reset release. Generate RC. Further, when at least one of the operation detection signal BC and the power supply voltage determination signal D1 indicates the logic level 0, the AND gate 24 generates the reset release signal RC of the logic level 0 indicating maintenance of the current state.

  The AND gate 24 supplies the generated reset release signal RC to the S terminal of the RSFF 23.

  As shown in FIG. 1, the RSFF 23 includes inverters IV1 to IV5, a NAND gate ND1, and NOR gates NR1 to NR3. Here, the input terminal of the inverter IV1 becomes the inverting R terminal of the RS flip-flop 23, and the input terminal of the inverter IV2 becomes the S terminal of the RS flip-flop 23.

  The inverter IV1 supplies a signal Ra obtained by inverting the logic level of the power supply voltage determination signal D2 supplied via the inverting R terminal to the NAND gate ND1 and the NOR gate NR1. The inverter IV2 supplies a signal Sa obtained by inverting the logic level of the reset release signal RC supplied via the S terminal to the NAND gate ND1 and the NOR gate NR1.

  The NOR gate NR1 supplies a signal Rb obtained by inverting the logical sum of the signal Sa and the signal Ra to the NOR gate NR2. The NAND gate ND1 and the inverter IV3 supply a signal Sb indicating a logical product of the signal Sa and the signal Ra to the NOR gate NR3.

  The NOR gate NR2 supplies a signal obtained by inverting the logical sum result of the output signal Y1 of the NOR gate NR3 and the signal Rb to the NOR gate NR3 as an output signal Y2. The NOR gate NR3 supplies a signal obtained by inverting the logical sum result of the output signal Y2 and the signal Sb to the NOR gate NR2 and the inverter IV4 as the output signal Y1 described above.

  The inverters IV4 and IV5 use the output signal Y1 output from the NOR gate NR3 as a reset signal RES, and this is used as a reset terminal of a plurality of reset terminal FFs (including FF12) included in the circuit configuration unit 10 via the reset wiring LR. To supply.

  FIG. 2 is a truth table representing the operation of the RSFF 23 configured as described above. As shown in FIG. 2, when both the power supply voltage determination signal D2 and the reset release signal RC are at the logic level 0, the RSFF 23 generates a reset signal RES at the logic level 0 prompting reset. When both the power supply voltage determination signal D2 and the reset release signal RC are at the logic level 1, the RSFF 23 generates a reset signal RES at the logic level 1 prompting release of the reset.

  In addition, as shown in FIG. 2, when one of the power supply voltage determination signal D2 and the reset release signal RC represents the logic level 0 and the other represents the logic level 1, the RSFF 23 indicates the current state of the reset signal RES. maintain.

  The operation of the power-on reset unit 20 will be described below with reference to the time chart shown in FIG.

  First, since the voltage value of the power supply voltage VDD is lower than the second threshold voltage Vt2 when the power is turned on, the power supply voltage determination signals D1 and D2 and the reset release signal RC maintain the logic level 0 state. Further, at the time of power on, the RSFF 23 outputs a reset signal RES of logic level 0 prompting reset.

  After the power is turned on, the voltage value of the power supply voltage VDD gradually increases as shown in FIG. 3, and at time t1 when the voltage value reaches the second threshold voltage Vt2, the state of the power supply voltage determination signal D2 is logic level 0 To the logic level 1. As shown in FIG. 3, the power supply voltage determination signal D2 maintains the logic level 1 state while the voltage value of the power supply voltage VDD is equal to or higher than the second threshold voltage Vt2.

  During this time, although the power supply voltage determination signal D2 transitions to the logic level 1, since the power supply voltage determination signal D1 and the reset release signal RC are in the logic level 0, the RSFF 23 sets the reset signal RES to the logic level 0 that prompts the reset. Keep in the state of

  Thereafter, the voltage value of the power supply voltage VDD further increases, and the power supply voltage determination signal D1 transitions from the logic level 0 state to the logic level 1 at a time point t2 when the power supply voltage VDD reaches the first threshold voltage Vt1. As shown in FIG. 3, the power supply voltage determination signal D1 maintains the logic level 1 state while the voltage value of the power supply voltage VDD is equal to or higher than the first threshold voltage Vt1.

  Here, according to the voltage value of the power supply voltage VDD at the time point t2, each circuit element included in the circuit configuration unit 10 should be in a state where normal operation is possible. However, due to manufacturing variations and the like, the circuit element may not operate normally at the voltage value of the power supply voltage VDD at the stage of time point t2. For example, in the example shown in FIG. 3, the FF 12 does not operate normally at the voltage value of the power supply voltage VDD at the time point t2, and the reset state is entered even if the power-on reset RES at the logic level 0 that prompts the reset is supplied. Don't be.

  Therefore, at time t2, the signal level of the output terminal of the FF 12 is not in the state of logic level 0 at the time of reset, so the inverter 25 can not detect that the FF 12 has operated normally. BC is continuously supplied to the AND gate 24. Thus, the AND gate 24 supplies a reset release signal RC of logic level 0 to the S terminal of the RSFF 23. Therefore, the RSFF 23 maintains the signal level of the reset signal RES at a logic level 0 that prompts a power-on reset even after the time point t2.

  Thereafter, when the voltage value of the power supply voltage VDD further increases and reaches, for example, a voltage value at which the FF 12 can operate at a time point t3 shown in FIG. 3, the FF 12 is reset in response to the reset signal RES at the logic level 0. As a result, at time t3, the operation detection signal BC changes from the logic level 0 state to the logic level 1 state indicating that the FF 12 has normally operated, and the reset release signal RC is also in the logic level 0 state accordingly. To a logic level 1 state. Therefore, since the inverter 25 detects that the FF 12 actually operates normally (power-on reset) at the time point t3 shown in FIG. 3, the RSFF 23 releases the reset signal RES from the logic level 0 state. Transition to urged logic level 1.

  In this way, the power-on reset unit 20 first generates a reset signal RES having a logic level 0 that prompts resetting in response to power-on. Then, the power-on reset unit 20 releases the reset signal RES from reset after detecting that the voltage value of the power supply voltage VDD becomes equal to or higher than the first threshold voltage Vt1 and the FF 12 operates normally (power-on reset). Transition to the logic level 1 state to be urged.

  This prevents a problem that after the power is turned on, the reset signal RES transitions to a state that prompts reset release before the voltage value of the power supply voltage reaches a voltage value at which each circuit element can be operated. Therefore, according to the configuration illustrated in FIG. 1, the FF included in the circuit configuration unit 10 can be changed in response to power-on without causing malfunction in the circuit configuration unit 10 regardless of variations in manufacturing of the semiconductor device. It becomes possible to reset.

  In the above-described embodiment, it is detected whether or not the FF 12 is operating normally, with a specific one of the plurality of FFs included in the circuit configuration unit 10 as a representative of the circuit element.

  The FF 12 is preferably an FF arranged at a position where the wiring length of the reset wiring LR from the power-on reset unit 20 is longest in the semiconductor IC chip 100. That is, the power on reset unit 20 is fed back with an output signal of the FF that is supplied with the logic level 0 reset signal RES most late after power on due to the wiring delay of the reset wiring LR. As a result, since the reset state is released after all the FFs are in the reset state, a problem caused by resetting only some of the FFs first is avoided.

  In addition, not only one FF 12 among a plurality of FFs included in the circuit configuration unit 10 but also two or more FFs are used as representatives of circuit elements to detect whether or not they are operating normally. May be.

  FIG. 4 is a circuit diagram showing a modified example of the circuit configuration unit 10 and the power on reset unit 20 included in the semiconductor IC chip 100, which has been made in view of the above point. The power-on reset unit 20 shown in FIG. 4 adopts a 3-input AND gate 24A instead of the 2-input AND gate 24 as shown in FIG. 1, and an inverter 26 for detecting normal operation. Except for the newly added point is the same as that shown in FIG.

  The inverter 26 supplies a signal obtained by inverting the logic level of the output signal of the FF 13 with a reset terminal among the plurality of FFs included in the circuit configuration unit 10 as the operation detection signal BCr to the AND gate 24A.

  Therefore, when the power supply voltage determination signal D1 represents logic level 1 and the inverters 25 and 26 detect normal operation (reset) of the FFs 12 and 13, the AND gate 24A outputs RSFF 23 as the reset release signal RC of logic level 1. Supply to the S terminal of the As a result, the RSFF 32 causes the reset signal RES to transition from a logic level 0 state to a logic level 1 state that prompts reset release.

  Therefore, according to the configuration shown in FIG. 4, it is possible to prevent the malfunction of the circuit configuration section 10 at the time of power on reset more reliably than in the case where the configuration shown in FIG. 1 is adopted.

  In the example shown in FIG. 1 and FIG. 4, the FF is used as a representative of the circuit element for detecting whether the circuit element is operating normally, but other circuit elements other than the FF may be used.

  FIG. 5 is a circuit diagram showing a modified example of the circuit configuration unit 10 and the power on reset unit 20 included in the semiconductor IC chip 100, which has been made in view of the above point.

  In the configuration shown in FIG. 5, the power on reset unit 20 is the same as that shown in FIG. However, in the configuration shown in FIG. 5, the memory 14 included in the circuit configuration unit 10 is a detection target of normal operation as a representative of circuit elements.

  In addition to the memory controller 15 that controls the writing and reading of data to the memory 14, the circuit configuration unit 10 is provided with a D-type FF 16 that takes in read data DAT read from the memory 14 and a comparator 17. It has been. Incidentally, operation check data is stored in advance at a predetermined address of the memory 14.

  The memory controller 15 reads the data for operation confirmation stored at a predetermined address of the memory 14 in response to power on, and supplies the read data as the read data DAT to the FF 16. The FF 16 takes in the read data DAT and supplies it to the comparator 17.

  The comparator 17 determines whether or not the expected value data PDT indicating the same data value as the operation confirmation data described above and the read data DAT indicate the same data value. The comparator 17 determines that the expected value data PDT and the read data DAT indicate the same data value, the logic level 0, and the comparator 17 indicates that the comparison result signal CM of the logic level 1 indicates the power value. This is supplied to the inverter 25 of the on-reset unit 20.

  That is, when the voltage value of the power supply voltage VDD after power-on is equal to or higher than the voltage value that allows the memory 14 and the memory controller 15 to operate normally, the read data DAT read from the memory 14 and the expected value The data PDT matches. Therefore, at this time, the comparison result signal CM represents the logic level 0. On the other hand, if the voltage value of the power supply voltage VDD is less than the voltage value at which the memory 14 and the memory controller 15 can operate normally, the memory 14 can not read correctly. Therefore, at this time, the comparison result signal CM represents the logic level 1.

  Therefore, when the comparison result signal CM indicates the logic level 0, the inverter 25 detects that the memory 14 is operating normally, and outputs the operation detection signal BC of logic level 1 representing the normal operation to the AND gate 24. Supply. On the other hand, when the comparison result signal CM represents the logic level 1, the inverter 25 supplies the AND gate 24 with the operation detection signal BC of the logic level 0.

  Therefore, the RSFF 23 first generates a reset signal RES having a logic level 0 that prompts resetting in response to power-on. When the voltage value of the power supply voltage VDD becomes equal to or higher than the first threshold voltage Vt1 and the normal operation (data reading) of the memory 14 is detected, the RSFF 23 sets the reset signal RES to the logic level 1 that prompts the reset release. Transition to the state.

  Thus, as in the embodiment shown in FIGS. 1 and 4, after the power is turned on, the reset signal RES urges release of reset before the voltage value of the power supply voltage reaches the voltage value at which each circuit element can operate. It is possible to prevent the problem of transition.

  The second threshold voltage Vt2 described above is set to a voltage value higher than the lower limit value of the power supply voltage VDD which can normally operate the circuit elements (logic elements, FFs, memories, etc.) included in the circuit configuration unit 10. It is desirable to set. As a result, after the power is turned on, the power-on reset is unlocked when the voltage value of the power supply voltage VDD is less than the lower limit value described above, that is, the voltage value at which the circuit element cannot be normally operated. It becomes possible to avoid the malfunction that the part 10 malfunctions.

  FIG. 6 shows an example of the trimming circuit 29 provided in the semiconductor IC chip 100 in order to set the second threshold voltage Vt2 to a voltage value higher than the lower limit value of the power supply voltage VDD that allows the circuit elements to operate normally. FIG.

  The trimming circuit 29 shown in FIG. 6 includes resistors RN0 to RN6 connected in series, trimming elements TR1 to TR5, and a trimming decoder DEC.

  The voltage VD is applied to one end of the resistor RN0. The other end of the resistor RN (k−1) is connected to one end of the resistor RN (k) (k is an integer of 1 to 5). One end of a resistor RN6 is connected to the other end of the resistor RN5, and a ground potential is applied to the other end of the resistor RN6.

  Here, the voltage generated at the connection point CN between the resistors RN5 and RN6 is supplied to the comparator 22 as the second threshold voltage Vt2.

  Both ends of the trimming element TR (k) are connected to both ends of the resistor RN (k).

  The trimming element TR (k) shorts both ends of the resistor RN (k) immediately after manufacturing. However, when a trimming signal g (k) of high level is supplied from the trimming decoder DEC, the trimming element TR (k) opens both ends of the resistor RN (k), and thereafter the level of the trimming signal g (k) Regardless, the open state of both ends of the resistor RN (k) is maintained. On the other hand, when the low level trimming signal g (k) is supplied, the trimming element TR (k) maintains the state in which both ends of the resistor RN (k) are shorted.

  The trimming decoder DEC generates a trimming signal g (k) having a high level or a low level according to the trimming code TMC, and supplies the trimming signal TR (k) with the trimming signal g (k).

  According to such a configuration, the resistance value between the resistor RN0 and the connection point CN changes according to the data value represented by the trimming code TMC, and accordingly, the voltage value of the second threshold voltage Vt2 generated at the connection point CN also changes.

  For example, as shown in FIG. 7, for each data value [000] to [101] represented by the 3-bit trimming code TMC, the second threshold voltage Vt2 is set to a voltage value of a magnitude corresponding to that data value. The

  Here, when the lower limit value of the power supply voltage VDD capable of operating the circuit element is, for example, the lower limit value VLL indicated by a one-dot chain line in FIG. 7, the data value [011], [100] or [101] ] May be supplied to the trimming decoder DEC.

  In the reset signal RES in the above embodiment, the reset is prompted when the logic level is 0, and the reset release is prompted when the logic level is 1, but the reset is prompted at the logic level 1 and the logic level is reset. It may be made to urge reset cancellation at 0. Therefore, the signals shown in FIGS. 1, 4 and 5 are not limited to the above-described logic level state (0 or 1).

  In short, as the semiconductor IC chip 100, one including the following circuit components and the power on reset unit may be employed.

  That is, the circuit configuration unit (10) includes a circuit including a plurality of circuit elements including a flip-flop (FF12) that is reset in response to a reset signal (RES). The power-on reset unit (20) generates, as a reset signal (RES), a signal having a first level (for example, logic level 0) that prompts resetting during a rising period of the power supply voltage (VDD) in response to power-on. Here, the power-on reset unit detects whether or not the circuit element (12, 13, 14) operates normally in response to power-on (25), and detects that the circuit element operates normally Then, the reset signal (RES) is shifted from the first level state to the second level (for example, logic level 1) that prompts the reset release.

DESCRIPTION OF SYMBOLS 10 Circuit structure part 12, 13 Flip-flop 14 Memory 20 Power-on reset part 21, 22 Comparator 23 RS flip-flop 24 And gate 25 Inverter

Claims (10)

A power-on reset unit that generates a reset signal having a first level that prompts resetting in a period of increase in power supply voltage in response to power-on;
A circuit configuration part in which a circuit is configured by a plurality of circuit elements including a flip-flop that is reset in response to the reset signal,
The power-on reset unit is
It is detected whether or not the circuit element operates normally in response to the power-on, and when it is detected that the circuit element operates normally, the reset signal is urged to be released from the state of the first level. A semiconductor device characterized by transitioning to a second level. The circuit element is the flip flop,
2. The semiconductor device according to claim 1, wherein the power-on reset unit detects that the circuit element operates normally when the output signal of the flip-flop has a reset level. The level of the output signal of the flip flop at the time of the reset is the first level,
The power-on reset unit is
An inverter that generates a signal obtained by inverting the level of the output signal of the flip flop as an operation detection signal indicating whether the flip flop operates normally;
It has the second level when the voltage value of the power supply voltage is equal to or higher than the first threshold voltage, and the first level when the voltage value of the power supply voltage is less than the first threshold voltage. A first comparator for generating a first power supply voltage determination signal;
When both the first power supply voltage determination signal and the operation detection signal represent the second level, the second power supply voltage determination signal and the operation detection signal have the second level. An AND gate for generating a reset unlocking signal having the first level if at least one represents the first level;
When the voltage value of the power supply voltage is equal to or higher than a second threshold voltage lower than the first threshold voltage, it has the second level, and the voltage value of the power supply voltage is less than the second threshold voltage A second comparator for generating a second power supply voltage determination signal having the first level;
An RS flip-flop that receives the reset unlock signal at its own S terminal and supplies an output signal obtained by receiving the second power supply voltage determination signal at its inverted R terminal to the circuit component as the reset signal And a semiconductor device according to claim 2.   The semiconductor device according to claim 3, wherein a voltage value of the second threshold voltage is higher than a lower limit value of the power supply voltage capable of operating the circuit element.   The semiconductor device according to claim 3, further comprising a trimming circuit that sets a voltage value of the second threshold voltage. The circuit configuration unit includes a plurality of flip flops,
The said flip-flop is arrange | positioned in the position where the wiring length of the reset wiring which transmits the said reset signal becomes the longest among these flip-flops, The any one of the Claims 1-5 characterized by the above-mentioned. Semiconductor device. The circuit element is a plurality of the flip flops,
2. The semiconductor device according to claim 1, wherein the power on reset unit detects that the circuit element has operated normally when all the output signals of the plurality of flip flops have a reset level. apparatus. The circuit configuration unit includes a memory as the circuit element,
The power-on reset unit is
The second embodiment of the present invention detects whether or not the memory has operated normally in response to the power-on, and when it is detected that the memory has operated normally, the reset signal is urged to release the reset from the first level state. The semiconductor device according to claim 1, wherein the transition is made to the level of Operation confirmation data having a predetermined data value is stored at a predetermined address of the memory,
The circuit component is
A memory controller that reads the operation check data from the predetermined address of the memory in response to power-on;
A comparator that compares the expected value data representing the same data value as the predetermined data value and the operation check data, and generates a comparison result signal indicating whether or not both represent the same data value. ,
9. The power-on reset unit detects that the circuit element has normally operated when the comparison result signal indicates coincidence between the expected value data and the operation check data. The semiconductor device described. A reset signal generation method for generating a reset signal having a first level that prompts resetting in a rising period of a power supply voltage in response to power-on,
It is detected whether or not a circuit element included in a circuit configuration unit in which a circuit is configured by a plurality of circuit elements including a flip flop that is reset according to the reset signal has operated normally.
A method of generating a reset signal, wherein the reset signal is transitioned from the state of the first level to a second level prompting release of reset when it is detected that the circuit element operates normally.

Images