JPS6020221A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a voltage detection circuit which detects between the first voltage, where power voltage is greater than lower-operating voltage of the internal circuit, and the second voltage greater in absolute value than the first, and form clear signals of the internal circuit by the output signals of the said second voltage. CONSTITUTION:The voltage detection circuit-A is the first voltage comparator having the voltage-V1 greater than a lower-limit actuating point of the internal circuit as reference voltage. The circuit-A is also the second voltage comparator where the voltage comparator-B has the voltage-V2, greater in absolute value than the voltage-V1, as reference voltage. The comparators A and B both make a voltage comparison between power voltage-VDD and reference voltages V1, and V2, and form H-level signals when the voltage-VDD becomes greater than V1 and V2. The output of the detection circuit-A is inputted in a set terminal S of FF, and the detection circuit-B is inputted in a reset terminal R of FF. The clear signals of the circuit unmentioned in the figure are outputted from the output terminal Q of FF, and peripheral equipment is set into initial state, thereby facilitating the clear during power making.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, and for example, an internally synchronized CMOS static type device that detects the transition of an address signal and forms a timing signal necessary for internal operation. It relates to technology effective for RAM.

[Background technology]

The inventors of the present invention have already developed an internally synchronized static RAM (Random Access Memory) that detects the change timing of an external address signal and uses it to control the timing of internal operations.

The inventor of the present invention has discovered that in such an internally synchronized static RAM, the following drawback occurs immediately after the power supply voltage is turned on. That is, if the address signal is already at a fixed level when the internal circuit becomes operational after the power is turned on, the address signal cannot be changed and the memory operation becomes impossible.

Therefore, the inventor of the present application considered providing a function to automatically perform a clearing operation when the power is turned on. In this case, if an attempt is made to detect the rise of the power supply voltage using a time constant circuit such as a differentiating circuit, a problem arises in that a detection signal cannot be obtained if the rise is slow.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having an auto-clear function when power is turned on with a simple circuit configuration.

Another object of the present invention is to provide a semiconductor integrated circuit device that can operate immediately after power is turned on without any change in external signals.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

In other words, a voltage detection circuit is provided to detect when a change in the power supply voltage reaches between a first voltage set at or above the operating lower limit voltage of the internal circuit and a second voltage that is larger in absolute value. A circuit is provided that forms a clear signal for the internal circuit based on the output signal.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Although not particularly limited, the RAM in the figure is a well-known 0M RAM.
O3 (complementary-metal-insulator-semiconductor) integrated circuit (IC)
) technology on a semiconductor substrate such as a silicon single crystal.

The terminals Ax, Ay, Din, Dout, WE and cs are its external terminals. Note that the power supply terminal is omitted in the figure.

One specific circuit of the memory cell MC is shown as a representative, and includes a memory MO5FETQ1 . Q2 and the above MO3FETQ
High resistances R1 and R2 formed of a polysilicon layer for retaining information are provided between the drains of I and Q2 and the power supply voltage VDD. And the above MO3FE
TQ1. A transmission gate) MO5FETQ3. is connected between the common connection point of Q2 and the complementary data lines DO, DO. Q4 is provided. Other memory cells MC also have similar circuit configurations. These memory cells are arranged in a matrix. The gates of the transmission gate type MOS FETs Q3, Q4, etc. of the memory cells arranged in the same row are commonly connected to the corresponding word lines wi and W2, respectively, and the input/output terminals of the memory cells arranged in the same column are
A pair of complementary data (or bits) D
O,D.

and connected to Dl and DI.

In the above memory cell MC, in order to make it consume low power, the resistor R1 can maintain the gate voltage of the MOSFETQ2 above the threshold voltage when the MO3FETQ1 is turned off. The resistance value is set to a certain level. Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistor R1 is the MO3FETQI
The MO3FET Q2 is designed to have a current supply capability sufficient to prevent the information charges stored in the gate capacitance (not shown) from being discharged due to the drain leakage current of the MO3FETQ2.

According to this embodiment, although the RAM is manufactured by OMO3-IC technology, the memory cell MC is composed of an n-channel MO3FET and a polysilicon resistance element as described above.

p channel MOS instead of the above polysilicon resistance element
The size of the memory cell and memory array can be made smaller than when FETs are used. That is, when a polysilicon resistor is used, it can be formed integrally with the gate electrode of the driving MO3FET QI or Q2, and the size of the resistor itself can be reduced. And p channel MO3F
As when using ET, the driving MO3FETQ1. Q
Since there is no need to separate it by a relatively large distance from 2, no wasted blank space is generated.

In the figure, the word line W1 is connected to the X address decoder
- Drive circuit DVI that receives the selection signal formed by DCR
selected by The same applies to the other word line W2.

The X-address decoder X-DCR is composed of mutually similar NOR gate circuits Gl, G2, etc. These NOR gate circuits G1. An external address signal A is supplied to inputs such as G2 from an appropriate circuit device (not shown).
0 to at are applied in a predetermined combination to the internal complementary address signal processed by the X address buffer 1X-ADB which receives X. In this embodiment, the non-inverted address signals aO-at and the inverted address signals 10-at are combined and expressed as address signals aO-al.

A pair of data i! in the above memory array! IDo.

50, DI, and DI are transmission gates MO8FETQ9. and DI for data line selection, respectively. QIO and Qll, G1
It is connected to the common data lines CD, CD through a column switch circuit composed of two. This common data line C
The input terminal of the read circuit DOB and the output terminal of the write circuit DIR are connected to D and CD. The output terminal of the read circuit DOB sends a read signal to the data output terminal Dout, and the input terminal of the write circuit DIB is applied with a write data signal supplied from the data input terminal Din.

MOSFETQ9 that constitutes the above column switch circuit.
A selection signal is supplied to the gates of QIO, Qll, and G12 from the Y address decoder Y-DCR, respectively.

This Y-address decoder Y-DCR is constructed from mutually similar NOR gate circuits G3.04 and the like. These NOR gate circuits G3. The input of G4 receives an external address signal AY supplied from an appropriate circuit device (not shown).
Internal complementary address signals i0 to aj processed by the receiving Y address buffer Y-ADH are applied in a predetermined combination. In this embodiment, the non-inverted address signals aO-aj and the inverted address signals 10-aj are combined and expressed as address signals aO-aj.

The control circuit CON receives control signals from the external terminals WE and C3, and forms a control signal (read or write control signal) for setting its operation mode.

Furthermore, between each data line and the power supply voltage VDD, there is a p-channel MO5FET for precharging the data line.
Q5 to G8 are provided.

In this embodiment, changes in external address signals AX and AV (
In order to detect transition) timing, the address signal a formed by the address buffers X-ADH and Y-ADH is
A trigger circuit EGT receiving X'+87' is provided. This edge trigger circuit EGT is
Although not particularly limited, it is constituted by an exclusive OR circuit that receives the address signal ax' and its delayed signal. That is, when the address signal ax' changes, the levels of the re-input signals become inconsistent by the delay time. As a result, the exclusive OR circuit outputs a mismatch signal which becomes logic "1" during that time.

The timing signal φt generated by this edge trigger circuit EGT limits the output timing of the address buffer X-ADB, and the timing signals φ and φ limit the output timing of the
The operation timing of 3FETs Q5 to G8 is controlled.

Furthermore, an auto clear circuit ACL is provided to enable read or write operations immediately after the aSS becomes adult.

FIG. 2 shows a circuit diagram of an embodiment of the auto clear circuit ACL.

Voltage detection circuit A detects a voltage v1 higher than the lower limit operation of the internal circuit.
This is a first voltage comparator circuit that uses the reference voltage as the reference voltage. Further, the voltage comparison circuit B is a second voltage comparison circuit that uses a voltage v2, which is larger in absolute value than the voltage v1, as a reference voltage. These voltage comparison circuits A and B both have the power supply voltage VDD and the reference voltage Vl.

A voltage comparison operation is performed with V2, and the power supply voltage V
DD is the reference voltage V1. When the voltage is larger than V2, a high level detection signal is generated, although there is no particular limitation. Although not particularly limited, the detection signal formed by the first voltage detection circuit A is a flip-flop circuit F.
It is supplied to the set input terminal S of F. Furthermore, the detection signal formed by the second voltage detection circuit B is supplied to the reset input terminal R of the flip-flop circuit FF, although this is not particularly limited. A clear signal ac for resetting peripheral circuits such as the Ars decoder is generated from the output terminal Q of the flip-flop circuit FF, and is supplied to these peripheral circuits.

The operation of the auto clear circuit of this embodiment will be explained with reference to the waveform diagram in FIG.

When the power is turned on, the power supply voltage V increases as shown by the solid line in the figure.
When the DD starts up, it first bypasses the voltage 1 set higher than the operating limit voltage of the internal circuit, and the voltage detection circuit A
detects this. This detection signal causes the flip-flop
Since the knob FF is sent, a clear signal ac which changes to a high level (logic "L") is generated from its output terminal Q as shown by the dashed line in the figure. As a result, the clearing operation of peripheral circuits such as the second address decoder and the like is started. Next, when the power supply voltage VDD reaches the above voltage ■2,
Voltage detection circuit B detects this. Since the flip-flop FF is reset by this detection signal, the clear signal aC sent from the output terminal Q is at a low level (
The reset operation is completed by changing to logic "0").

Therefore, a write or read operation can be performed on a memory cell according to an already supplied address signal.

〔effect〕

(1) Since two types of reference voltages that are higher than the lower limit operating voltage of the internal circuit are used, it is possible to form a clear signal that is reliably generated without being affected by the rise of the power supply voltage VDD.

(2) A clear signal is not generated unless the power supply voltage changes from a reference voltage that is small in absolute value to a reference voltage that is large in order to reach the voltage of Class 2M, so fluctuations (bumps) occur in the power supply voltage. However, since there is no response as in the case of using the above-mentioned differentiating circuit, it is possible to achieve the effect that a reliable auto-clear operation can be realized.

(3) By providing the above auto-clear circuit in an internally synchronous semiconductor memory device, it is possible to access the device at the same time as the power is turned on without performing any special initialization.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the reference voltage and power supply voltage actually supplied to the voltage comparison circuits A and B may both be level-shifted.

Further, as the reference voltage, a threshold voltage of a circuit element such as a MOSFET (insulated gate field effect transistor) may be used.

Furthermore, instead of the flip-flop circuit described above, a logic gate circuit may be used to generate a similar rear signal ac.

[Application field]

The above explanation has mainly been about the case where the invention made by the inventor of the present application is applied to an internally synchronous static type RAM, which is the technical field behind the invention.
However, the invention is not limited to this, but for example, it is possible to use a dynamic type memory cell, construct its peripheral circuit with a static type circuit, and provide the above-mentioned edge trigger circuit to similarly control the operation timing of the internal circuit. , it can also be applied to a dynamic type RAM that can be handled in the same way as the static type RAM described above.

Furthermore, the present invention can be similarly applied to semiconductor integrated circuit devices that perform information processing operations such as microcomputers that include storage means such as flip-flop circuits and registers.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing an m-embodiment of the auto clear circuit, and Fig. 3 is an operation waveform diagram for explaining its operation. It is. X-ADB...X address buffer, Y-ADB...Y
Address buffer, X-DCR...X address decoder, Y-DCR...Y address decoder, MC...memory cell, DIB...write circuit, DOB...read circuit, CON...control circuit, EGT...edge trigger circuit ,
A CL...Auto clear circuit, A, B...Voltage detection circuit, FF...Flip-flop circuit 1st Figure 11- 2nd Figure 5th Figure 3

Claims (1)

[Claims] 1. A first voltage detection circuit that receives a first reference voltage that is equal to or higher than the operating lower limit voltage of the internal circuit and a power supply voltage; a second voltage detection circuit receiving the set second reference voltage and power supply voltage;
Above 1. After receiving the second voltage detection output, until the power supply voltage reaches the second reference voltage from the first reference voltage,
A semiconductor integrated circuit device comprising: an auto clear circuit that forms a clear signal for an internal circuit. 2. The internal circuit that receives the above clear signal constitutes an internally synchronous semiconductor memory device that forms various timing signals necessary for the operation of the internal circuit based on the timing signal that detects the transition of the address signal. A semiconductor integrated circuit device according to claim 1. 3. The above semiconductor memory device is a CMOS static type R
3. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is an AM.