JPS6013391A - Mos storage device - Google Patents

Abstract

PURPOSE:To reduce a through current, to save power consumption and to prevent a latch-up and the incorrect selection of an address decoder by forming an address signal changing steeply to accelerate the amplification of an address buffer or detecting the transition period of an output signal from an address buffer to inhibit transmission. CONSTITUTION:A latch circuit FF is obtained by connecting so as to cross between the input and output of two inverter circuits constituted of n channel MOSFET Q20 (Q22) and p channel MOSFET Q21 (Q23) and its I/O terminals are connected to the input terminal and output terminal of an inverter IV3 respectively. When the input signal and output signal of the IV3 reach a level inverting the latch circuit FF receiving the input and output signals, the latch circuit FF responds the inversion steeply by its forward feedback operation and transmits the inversion to the input and output side of the IV3, so that an address signal formed by the IV3 can be steeply changed. Since the conductance characteristic of the MOSFET is easily inverted in accordance with the output of the IV3, the value is set up to a comparatively small value.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to an MO3 storage device, for example,
The present invention relates to a technique that is effective for an internally synchronous CMOS static RAM that detects the change timing of an address signal and is used to control the timing of internal operations.

[Background technology]

An address buffer in a CMOS static RAM may be constructed by connecting a plurality of inverter circuits in series.

The CMO3 circuit only operates during the transition period when its input signal changes.
It has the feature of extremely low power consumption because it passes direct current. However, on the other hand, when the above signal is at the intermediate level of the transition period, both the n-channel MO3FET and the p-channel MOS FET are turned on with relatively large conductance characteristics, so a relatively large through current flows. It is something.

Therefore, when using the address buffer as described above, if the input address signal changes slowly, a relatively large through current will flow through all the inverter circuits at the same time. Further, when the output signal of the address buffer is at an intermediate level, a large through current flows in the address decoder circuit accordingly, and erroneous selection occurs. When the through-current flows all at once as described above, not only does the current consumption increase, but there is also the possibility that the parasitic silice element becomes operational, causing a latch-up.

[Purpose of the invention]

An object of the present invention is to provide an MO3 storage device that achieves low power consumption, prevents launch-up, and prevents incorrect address decoder selection.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, by using the positive feedback amplification operation of the latch circuit to form a rapidly changing address signal to facilitate the amplification operation of the address buffer, or by detecting the transition period of the output signal of the address buffer. By inhibiting transmission of the output signal of the address buffer, generation of through current is reduced.

〔Example〕

FIG. 1 shows the present invention as a CMOS static RAM.
A circuit diagram of an embodiment when applied to is shown. Although not particularly limited, the RAM shown in the figure may be a known CMO3 (
It is formed on a single semiconductor substrate, such as a single silicon crystal, by integrated circuit (IC) technology.

The terminals Ax, Ay, Din, Dout, WE and CS are its external terminals. Note that the power supply terminal is omitted in the figure.

One specific circuit of the memory cell MC is shown as a representative, which is a memory (drive) MO3FET QI whose gate and drain are cross-connected to each other.

High resistances R1 and R2 formed of a polysilicon layer for retaining information are provided between the MO3FET Q2 and the drain of the MO3FET QI and Q2 and the power supply voltage VDD. A transmission gate MO3F is connected between the common connection point of the MO3FETs Ql and Q2 and the complementary data lines Do and DO.
ETQ3. Q4 is provided. Other memory cells MC
Both have similar circuit configurations. These memory cells are arranged in a matrix. Transmission gate type M of memory cells arranged in the same row.

5FETQ3. Gates such as Q4 are commonly connected to the corresponding word lines W1 and W2, and the input/output terminals of the memory cells arranged in the same column are connected to the corresponding pair of complementary data lines (or pins in the memory cell MC). , in order to make it consume low power, its resistor R1 is
M when MOS F ETQl is turned off
The resistance value is set to be high enough to maintain the gate voltage of O3FETQ2 above the threshold voltage. Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistance R
1 is designed to have a current supply ability sufficient to prevent the information charge stored in the gate capacitance (not shown) of MO3FET Q2 from being discharged due to drain leakage current of MO3FET QI.

According to this embodiment, although the RAM is manufactured by CMO3-IC technology, the memory cell MC is composed of an n-channel MO3FET and a polysilicon resistance element as described above.

p channel MO3 instead of the above polysilicon resistance element
The size of the memory cell and memory array can be made smaller than when FETtl- is used. That is, when a polysilicon resistor is used, it can be formed integrally with the gate electrode of the driving M○5FET QI or Q2, and its size can be reduced. And p-channel MOS
As when using FET, drive MO3FETQI
, Q2 does not have to be separated by a relatively large distance, so no unnecessary blank space is created.

In the figure, the word line W1 is connected to the X address decoder
- Drive circuit DVI that receives the selection signal formed by DCR
selected by The same applies to the other word line W2.

The X-address decoder X-DCR is composed of NOR gate circuits Gl, '02, etc. of mutually parallel type (1u).The inputs of these NOR gate circuits Gl, '02, etc.
Internal complementary address signals processed by an X address buffer X-ADB receiving an external address signal Ax supplied from an appropriate circuit device (not shown) are applied in a predetermined combination.

A pair of data lines DO2DO and DI, Di in the memory array are connected to transmission gates MO3FETQ9. It is connected to common data lines CD and CD via a column switch circuit composed of QIO, Qll, and G12. This common data line CD, C
The input terminal of the read circuit DOB and the output terminal of the write circuit DIB are connected to D. The above readout circuit DO
The output terminal of B sends a read signal to the data output terminal Dout, and the input terminal of write time 1?3DIB sends a read signal to the data output terminal Dout.
A write data signal supplied from the data input terminal Din is applied.

MO3FETQ9 that constitutes the above column switch circuit.
A selection signal is supplied to the gates of QIO, Qll, and G12 from the Y address decoder Y-DCR, respectively.

This Y-address decoder Y-DCR is composed of circuits G3.04 to NORAD1 which are similar to each other.

These NOR gate circuits G3. The input of G4 receives an external address signal A supplied from an appropriate circuit device (not shown).
Internal complementary address signals processed by the Y address buffer Y-ADB receiving y are applied in a predetermined combination.

The control circuit CON receives control signals from the external 111 children WE and G3 and forms an internal control timing signal.

Although not particularly limited, the internal control signal cs generated by this control circuit CON is transmitted to the X address decoder X.
- It is input to the NOR gate circuits Gl, 02, etc. that constitute the DCR. As a result, all the word lines are set to a non-selected state due to the high level (logic "1") of the control signal cs when the chip is not selected, and the load MO3FETQ5 etc. and the memory cell MO3FETQ3. This prevents direct current from flowing through Ql etc.

FIG. 2 shows the address buffer X-ADB (Y-A
A circuit diagram of an embodiment of DB) is shown. In this example, CMOS inverters IVI connected in cascade configuration
The next latch circuit FF is provided in the address buffer configured by IV6. Note that the inverter IV7 forms an inverted address signal at having a phase opposite to the input address signal Ai.

The latch circuit FF is an n-channel MO3FETQ2
0 (G22) and p-channel MO3FETQ21 (
G23) and the input of two inverter circuits,
The outputs are cross-connected, and the pair of input/output terminals are respectively connected between the input terminal and the output terminal of the inverter IV3.

In this embodiment, when the signal reaches the level at which the latch circuit FF inverts, the launch circuit FF that receives the input signal and output signal of the impark IV3 responds sharply by its positive feedback operation, and Since the address signal is transmitted to the input side and the output side of the impark IV3, the address signal formed by the impark IV3 can also be changed rapidly. The conductance characteristic of the MOSFET constituting the latch circuit FF is set to a relatively small value so that it can be easily inverted according to the output of the inverter IV3.

FIG. 3 shows a circuit diagram of another embodiment of the address buffer.

In this embodiment, the following circuits are provided in the address buffer made up of the inverters IVI to IV6. That is, the same MOS FET Q20 to Q2 as above
3 constitutes a latch circuit FF, one input/output terminal of which is supplied with the input signal of the inverter TV3. The output signal of this launch circuit FF is supplied to one input terminal of the exclusive OR circuit EX via an inverter IV8. The output signal of the final stage inverter IV6 is supplied to the other input terminal of the exclusive OR circuit EX. The output signal of this exclusive OR circuit EX is used as a control signal of a NOR gate circuit NOR that controls transmission of the address signal formed by the inverter IV6.

Note that, although not particularly limited, as will be described later, the output signal of the exclusive OR circuit EX performs edge detection of logic "1" when its address signal Ai changes, so this can be used to control internal operation timing, e.g. , complementary data line pair,
It may also be used for an equalization operation that short-circuits D.

Next, the operation of this embodiment circuit will be explained with reference to the timing diagram of FIG.

Now, when the signal at the node N1 at the input terminal of the inverter V3 changes from high level to low level as shown by the broken line, the signal at the node N2 at the output terminal of the inverter TV6 formed through the inverters IV3 to IV6 also lags. changes from high level to low level. At this time, in response to the change in the signal at the node N1, the latch circuit 1i! l'
Since F is inverted, the output terminal of the inverter IV8, the node N3, abruptly changes from high level to low level. Therefore, during the period until the node N2 changes to the low level, the input voltages of the exclusive OR circuit EX do not match, so the output terminal node N4 becomes high level (logic "1") during that period. Therefore, the NOR gate circuit NO.
R is closed and the inverted address signal at is forcibly fixed at a low level. Then, when the above-mentioned mismatch period elapses, the node N4 of the output terminal of the exclusive OR circuit EX becomes low level, so that
An address signal formed by V6 is conveyed. Note that the non-inverted address signal at is formed through an inverter circuit (not shown).

As a result, in the address decoder circuit, the intermediate level address signal at is not supplied, so that N current does not flow and a double selection operation is not performed.

〔effect〕

(Using the positive feedback operation of the 11 latch circuit FF, the input signal and output signal of the inverter rV3 change sharply, so the transition period of the address signal can be shortened. Also, it is possible to significantly reduce the through current in the address decoder circuit.

(2) The transition period of the address signal is detected by inputting the output signal of the latch circuit FF and the output signal of the final stage inverter IV6 to the exclusive OR circuit, and the address signal is sent to the address decoder circuit. Therefore, it is possible to significantly reduce the through current in the address decoder circuit.

(3) According to the above (IL) (2), it is possible to achieve a significant reduction in the through current, thereby achieving the effect that the power consumption can be significantly reduced.

(4) Due to (11 and (21) above, (1) it is possible to achieve a significant reduction in the conduction current, thereby achieving the effect of preventing the occurrence of latch-up due to parasitic sil-risk elements.

(5) With (1) or (2) above, it is possible to increase the speed of change of the address signal, thereby achieving the effect of preventing double selection of word lines.

(6) Since the change timing signal of the address signal can be generated from the exclusive OR circuit EX, an effect can be obtained that an internally synchronous type semiconductor memory device can be realized using this signal.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. do not have. In the embodiment circuit of FIG. 2 or 3, an inverter IV1. IV2 is provided to keep its input impedance high, and the number of IV2 may be one. Furthermore, the number of inverter circuits arranged in series can be varied as required.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to a CMOS static type RAM, which is the field of application that formed the background of the invention, but the invention is not limited to this. For example, address buffers,
The present invention can be widely applied to various semiconductor storage devices such as ROM (read only memory), RAM, and programmable ROM in which the address decoder circuit and the like are composed of CMO3 circuits or single-channel MO3FETs.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention applied to a CMOS static RAM, FIG. 2 is a circuit diagram showing an embodiment of the address buffer circuit, and FIG. 3 is a circuit diagram showing an embodiment of the address buffer circuit. FIG. 4, a circuit diagram showing another embodiment of the buffer, is a timing diagram for explaining its operation. X-ADB...X address buffer, Y-ADB...Y
Address buffer, X-DCR...X address decoder, Y-DCR...Y address decoder, MC...memory cell, DIB...write circuit, DOB...read circuit, CON...control circuit 5 1st Figure 6 2 Figure L Figure 3 Figure 4

Claims (1)

[Scope of Claims] 1. A plurality of impark circuits in a cascade configuration that receive address signals supplied from the outside, a latch circuit that receives signals at a predetermined connection point in this inverter circuit array, and an output signal of this latch circuit. An address buffer is provided with a function to provide positive feedback to a predetermined terminal of the inverter circuit array, or a function to inhibit transmission to the address decoder by detecting a mismatch between the output signal of the latch circuit and the output signal of the final stage inverter circuit. M characterized by comprising
O3 storage. 2. The MO3 storage device according to claim 1, wherein the circuit for forming the mismatch detection output is constituted by an exclusive OR circuit. 3. The MO3 storage device according to claim 1 or 2, wherein the address buffer is an address buffer for selecting a word line. 4. MO3 according to claim 1, 2 or 3, wherein the output signal of the exclusive OR circuit is also used to control the operation timing of the internal circuit. Storage device.