JPS60234292A - Mos static ram - Google Patents

Abstract

PURPOSE:To attain the high-speed working of an MOS static RAM by providing a load FET with which a complementary data line is turned on in a non-selection mode. CONSTITUTION:When a complementary data line DO and a line DO', etc. are put under a non-selection state by a low level column selection signal YO, etc., the output YO' of an inverter IVO is changed to a high level. Then load MOSFET Q13 and Q14 connected in parallel to load MOSFETQ5 and Q6 respectively are turned on. Thus the conductances of lines DO and DO' are increased and both lines have an approximately equal potential with no remain of the preceding read information. Therefore, the time is shortened to change the line DO' to a high level according to the storage contents of a memory cell MC. Thus the working speed of an MOS static RAM can be increased.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a static RAM (Random Access Memory) composed of MOSFETs (Insulated Gate Field Effect Transistors).
The present invention relates to a technique that is effective when used in a device configured with a CMO3 (complementary MO3) circuit.

[Background technology]

The memory array in MOS static RAM is
Input/output terminals of a static flip-flop circuit constituting a memory cell are connected to a pair of complementary data lines D via a transmission gate MO3FET. This complementary data line D is provided with MO3FF, T as a load resistance. The conductance characteristic of the MOS FET serving as this load resistance is set to a small value. because,
In order to increase storage capacity, a memory array is formed with a small element size in order to configure a large number of memory cells. When the transmission gate MO3FET is turned on and the input/output terminals of the flip-flop circuit are connected, the driving MO3FET and the transmission gate MO3FET in the on state constituting the flip-flop circuit are connected.
3FET conductance characteristics and the above load MO3FE
Since the read low level of the complementary data line is determined according to the conductance characteristic ratio with the conductance characteristic of T, the conductance characteristic of the load MO3FET is inevitably set small. Therefore, in the read operation of memory cells provided for the same complementary data line, when performing inverted read, in other words, the logic
When reading the storage information of logic “1” after reading the storage information of “0”, the complementary data line has the previous logic “0”.
Since the information "" remains, a problem arises in that it takes a relatively long time to change from a low level to a high level using the load MOSFET having the poor conductance characteristics.

Regarding MOS static type RAM, please refer to Japanese Patent Application Laid-open No. 1987-
It is described in detail in the 198594 publication.

[Purpose of the invention]

An object of the present invention is to provide a MOS static type RAM that operates at high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, as load means provided on a pair of complementary data lines constituting a memory array, a pair of first load MOS FETs which are kept in a steady state of operation, and these loads M
By providing a pair of second loads MO3FETs that are arranged in parallel with the O3FETs and are controlled to be in the on state when the complementary data line thereof is in the non-selected state, the inversion from the memory cell on the same complementary data line is This achieves high-speed reading.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the present invention. Although not particularly limited, the RAM in the figure may be a known CM
O3 (Complementary-Insulator-Semiconductor) Integrated Circuit (IC
) technology on a semiconductor substrate such as a silicon single crystal.

The terminals Ax, Ay, Din, Dout, WE and CS are its external terminals. Note that the power supply terminal is omitted in the figure.

One specific circuit of the memory cell MC is shown as a representative, and includes memory MO5FETQI, Q2 whose gates and drains are cross-connected to each other, and the MO3FETQ mentioned above.
High resistances R1 and R2 formed of a polycrystalline silicon layer for information retention are provided between the drains of I and Q2 and the power supply voltage VDD. And the above MO5F
Common connection point of ETQI, Q2 and complementary data lines DO, Do
A transmission gate MO5FETQ3. Q4 is provided. Other memory cells MC also have similar circuit configurations. These memory cells are arranged in a matrix. The gates of the transmission gates MO3FETQ3゜Q4, etc. of the memory cells arranged in the same row are commonly connected to the respective corresponding word lines WO and Wl, and the input/output terminals of the memory cells arranged in the same column are respectively connected to the corresponding word lines WO and Wl. a pair of complementary data (or bit) lines Do,
Connected to Do, Di, and DI.

In the memory cell MC, in order to make it consume low power, the resistor R1 can maintain the gate voltage of MOS FETQ2 above the threshold voltage when MOS FETQl is turned off. The resistance value is set to a certain level. Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistor R1 is the MO3FETQI
The MO5FET Q2 is designed to have a current supply capability sufficient to prevent the information charges stored in the gate capacitance (not shown) from being discharged due to the drain leakage current of the MO5FETQ2.

According to this embodiment, although the RAM is manufactured by OMO3-IC technology, the memory cell MC is composed of an n-channel MO3FET and a polysilicon resistance element as described above.

p channel MO8 instead of the above polysilicon resistance element
Compared to the case of using FETs, the size of the memory cell and memory array can be made smaller. That is, when a polysilicon resistor is used, it can be formed integrally with the gate electrode of the drive MO3FET QI or G2, and its size can be reduced. And p-channel MO5FET
As when using the driving MO3FETQ1. Since it does not have to be separated from Q2 by a relatively large distance, no unnecessary blank space is created.

In the figure, the word line WO is connected to the X address decoder
- Drive circuit DVO that receives the selection signal formed by DCR
selected by The same applies to the other word lines W1.

The X-address decoder X-DCR is composed of mutually similar NOR gate circuits Gl, 02, etc. These NOR gate circuits Gl, G2, etc. have +l, for example.
Internal complementary address signals aO, aO to ak, ak processed by an X address buffer be done. Furthermore, an internal chip selection signal ce is applied to the X address buffer X-ADB in order to provide the first stage cut function.

A pair of complementary data lines DO, D in the memory array
O, DI, and DI are transmission gates MO3FETQ9.0 and DI, respectively, for data line selection. QlO and Qll, G12
It is connected to the common complementary data lines CD, CD through a column switch circuit composed of the following. The input terminal of the read circuit DOB and the output terminal of the write circuit DIB are connected to the common complementary data 1JlcD, cD. The output terminal of the readout circuit DOB is the data output terminal Do.
A read signal is sent to ut, and a write data signal supplied from the data input terminal Din is applied to the input terminal of the write circuit DIB.

Also, a pair of complementary data lines DO, DO and DI are shown as representative in the memory array.

Di has MO3FETQ5 as a load means.
~Q8 is provided. These MO3FETQ5~Q8
are kept in a steady state of operation by having their gates and drains commonly connected. In addition, in order to speed up the inversion read operation, the MO3FETs Q5 to Q
B has MO3FETQI 3 to Q in parallel form, respectively.
16 are provided. These MO3FF, TQI 3~
A complementary data line selection signal Y, which will be described later, is applied to the gate of Q16.
Inverted signals YO and Yl of O2Y1 are supplied.

MO3FETQ9 that constitutes the above column switch circuit.
The gates of QI O, Qll, and G12 each have Y
Selection signals YO and Yl formed by address decoder Y-DCR are supplied. This Y address decoder Y-
DCR is a mutually similar NOR gate circuit G3. G
Consists of 4th grade. These NOR gate circuits G3.
G4, etc., are internal complementary address signals aQ, aOxaj, a processed by a Y address buffer Y-ADH that receives an external address signal Ay (address signal output from an appropriate circuit device not shown) consisting of, for example, j+1 bits.
j are applied in a predetermined combination.

The above NOR gate circuit G3. The selection signals YO and Yl formed by G4 are applied to the inverter circuit IVO.

IVI and the above load MO3FETQI 3~Q
16 are formed.

The control circuit CON receives control signals from external terminals WE and C3 and forms the internal control timing signal 5 and the like.

In this embodiment, since all word lines are in a non-selected state when a chip is not selected, the internal chip selection signal "7" is applied to the input of the NOR gate circuit G1 that selects the word line WO, although this is not particularly limited. As a result, when the chip is not selected, the internal chip selection signal τ is supplied to the NOR gate circuit G1 in order to inhibit the selection operation of the word line WO. Even if all of the chips are at a low level, the high level before the internal chip selection signal causes the output to be at a low level and in a non-selected state.

This was done for the following reasons. That is, if one word line is kept in a selected state when a chip is not selected, the load M
Since O3FETQI3 to Q16 are all turned on and continue to supply a relatively large current to the complementary data line,
Transmission gate MOS F E of selected memory cell MC
T and information storage MOS FET in on state
This is because the DC current continues to flow through the terminal, increasing the reactive current.

Next, the inversion read operation of the memory cell of this embodiment will be explained with reference to the operational waveform diagram shown in FIG.

In a chip selection state where the chip selection signal C8 is at a low level, one memory cell is selected by supplying an address signal (not shown), so that, for example, the complementary data line Do becomes high level and DO becomes low level.

Then, when the address signal changes and the column selection signal YO becomes a low level non-selected state, 1. As a result, the inverted signal YO becomes high level, so that the loads MO3FETQ13 . Since Q14 is turned on, the data line DO, which is at a low level, is raised to a high level at high speed, as shown by the solid line in the figure. Therefore, when the chip selection signal C3 is set to low level and another word line is selected to read inverted memory information from another memory cell, the potentials of the complementary data lines DO rise and become the same. , the data line Do changes to low level according to the storage information of the selected memory cell.

Note that if the above MO3FETs Q13 to Q16 etc. are not provided, load MO5FETs Q5. Since only Q6 etc. are provided, the previous read level remains as shown by the dotted line in the figure. This results in
Since it takes a long time to raise the low level data line DO to high level, the read operation becomes slow.

For this reason, the selection timing of the data line is also significantly delayed, as shown by the dotted line in the figure.

〔effect〕

(By using the RAM selection signal to turn on a MOSFET with a relatively large current drive capability, the level of the complementary data line remaining from the previous read operation can be cleared quickly. This provides the effect of increasing the speed of the inversion read operation.

(2) When the chip is not selected, all word lines can be set to the non-selected state by the internal chip selection signal B, so the transmission gate MOS F that constitutes the memory cell
By turning all ETs off, the MO turns on due to the column non-selection signal.
Even though the SFET is provided, it is possible to prevent current from flowing from the data line through the memory cell.

(3) The circuit that unselects all word lines when a chip is not selected uses the first-stage cut function of the address buffer, so one input terminal is added to the NOR gate circuit, etc. that constitutes one address decoder circuit. Therefore, in the CM OS circuit, two MOS FETs are required.
Since this can be realized by simply adding , it is possible to achieve the effect of having an extremely simple circuit configuration.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the memory cell is a p-channel MO3FET and an n-channel MOSFET.
A static flip-flop circuit constructed by combining ET may also be used. Further, the load MO5FETs Q5 to Q8 may be replaced with resistance means such as polysilicon. Furthermore, the configuration of the memory array and the specific circuit configuration of its peripheral circuits can take various embodiments.

[Application field]

This invention can be widely applied to MOS static RAM.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is an operation waveform diagram for explaining an example of the inversion read operation. X-ADH...X address buffer, Y-ADB...X
Address buffer, X-D CR...X address decoder, Y-DCR...Y address decoder, MC...memory cell, DIB...write circuit, DOB...read circuit, CON...control circuit 5

Claims (1)

[Claims] 1. A first load means provided on a pair of complementary data lines constituting a memory array, and a first load means provided in parallel with these load means, when the complementary data line is in a non-selected state. A pair of second loads MO3FE controlled to be in the on state
MOS static type RA characterized by including T
M. 2. The MOS static type RAM is composed of eight CMO circuits, and the column switch MO3FET for selecting a complementary data line and the first load means and second load MO3FET are n-channel MO3FETs.
The second load MOS F
The MO according to claim 1, wherein the ET control signal is an inverted signal of the complementary data line selection signal.
S static type RAM. 3. The memory cells constituting the MOS static type RAM include MO3FETs for information storage whose gates and drains are cross-connected, and high resistance means for information storage provided between each drain and a power supply voltage. M according to claim 2, characterized in that it includes
OS static type RAM.