JP2631925B2 - MOS type RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS (Metal Insulator Semiconductor) RAM (Random Access Memory), and more particularly to a MOS static RAM formed in CMOS.

[0002]

2. Description of the Related Art MOS static RAM (hereinafter referred to as S
In the case where data input / output terminals are connected in common and data is transmitted / received to / from a common data bus, the inventor of the present invention connects the internal power supply lines (Vcc, GND) of the S-RAM It has been found that relatively loud noise is generated.

[0003]

SUMMARY OF THE INVENTION In the present inventor,
As a result of studying the cause of the noise generation, it was found that the cause was as follows.

In a conventional S-RAM, as shown in FIG.
The data input buffer circuit DIB is used, and a large through current flowing at the start of the read operation generates a large noise on the internal power supply line.

That is, as shown in the operation waveform diagram of FIG. 2, a chip selection signal CS * (a negative logic level signal CS,
Hereinafter, similarly, an asterisk (*) indicates a negative logic level) when the internal control signal C is changed to a low level.
S '* also changes to low level.

Therefore, p receiving this signal CS '*
The channel MOSFET Q ₂ is turned on and the n-channel M
OSFETQ ₄ is turned off, according to the data from the input-output terminal I / O, its output level is determined.

However, during a read operation in which the write / read control signal WE * is at a high level, the input / output terminals I / O
Until the read data from the data output buffer circuit DOB is transmitted to the input / output terminal I / O, the input / output terminal I / O is at an intermediate level of high impedance.

Therefore, the p-channel MOSFET Q of the data input buffer circuit DIB receiving the intermediate level
₁ and n are channel MOSFET Q ₃ are both turned on, a large through current flows to generate noise to the power supply line. This noise adversely affects the operation of selecting a memory cell and the operation of amplifying a read sense amplifier, causing a malfunction. Further, the through current increases the power consumption of the S-RAM.

An object of the present invention is to provide a data input buffer.
Current flowing between the power supply terminal and the circuit ground point at
It is an object of the present invention to provide a MOS-type RAM that prevents current flow and prevents generation of noise due to such a through current .

Another object of the present invention is to provide a MOS-type RAM with low power consumption.

Further objects of the present invention will become apparent from the following description and drawings.

[0012]

[Means for Solving the Problems] Has a three-state output function
Connect the output terminal of the data output buffer to the external terminal
Input signal from the signal input terminal connected in common
Is supplied to one input terminal and the chip is
Formed based on a selection signal and a write / read control signal
A CMOS logic circuit to which a control signal is supplied,
When a write operation is instructed by the control signal,
It takes in the input signal from the signal input terminal.
As a data input buffer, input from the above signal input terminal
A force signal is applied to the gate and its drain is the output point
N-channel MOSFET connected to the power supply of the circuit
The source-drain is connected between the terminal and the output point
And complementary operation to the N-channel MOSFET
Output in response to an input signal from the second external terminal.
P-channel MOSFET for applying force signal to the output point
Between the power supply terminal of the circuit and the ground potential point of the circuit
The N-channel MOSFET and the P-channel M
The source-drain is connected directly with the OSFET.
And the control signal supplied to the gate
A switch-controlled switch MOSFET is used.

[0013]

The data input buffer circuit is deactivated in the read operation in the chip selection state, so that an increase in power consumption can be prevented.

Hereinafter, the present invention will be described in detail with reference to embodiments.

[0015]

FIG. 3A shows an internal configuration of an S-RAM integrated circuit (hereinafter referred to as IC) having a storage capacity of 16 k bits and an output of 1 bit.

Each of the 16 kbit memory cells has 12 memory cells.
8 columns (rows) × 32 rows (columns) = 4096 bits (4
It is composed of four matrices (memory arrays M-ARY1 to M-ARY4) having a storage capacity of (k bits), and each matrix is arranged on the left and right sides of the row decoder R-DCR in two halves.

A row address select line (word line WL1)
To WL128, WR1 to WR128), 2 ⁸ = 25 obtained based on the address signals A _{0 to} A ₅ , A ₁₂ and A _13.
Six types of decode output signals are sent from the row decoder R-DCR.

As described above, the memory MC of each matrix is used.
EL denotes word lines WL1 to WL128, WR1 to WR12
8 and a complementary data line pair D1 described later.
1, D11 * to D132, and D132 *.

The address signals A ₅ and A ₆ are used to select only one of the four memory matrices. Address signal A ₇ to A ₁₁ to select one column in one memory matrix which is selected, is used.

The memory matrix selection signal GS is decoded into four combinations based on the address signals A ₅ and A ₆ .

Column decoders C-DCR1 to C-DCR
4 each based on the address signal A ₇ ~A ₁₁ 2 ⁵
= 32 kinds of column selection decode output signals are provided.

At the time of reading, common data line pair CD
L and CDL * are common data line dividing transistors (Q
_{1, Q 1 *; ......;} Q 4, Q 4 *) 4 minutes cracking for each memory array by, the common data line C at the time of writing
DL and CDL * are commonly connected.

Sense amplifiers SA1, SA2, SA3, S
A4 is the common data line pair CDL, CDL divided above.
Each is provided corresponding to *.

As described above, the common data line pair CDL, CDL
* Are divided into sense amplifiers SA1, SA2,
The purpose of providing SA3, SA4 is the common data line pair C
An object of the present invention is to divide the parasitic capacitances of DL and CDL * to speed up the operation of reading memory cell information.

The address buffer ADB generates fourteen pairs of complementary address signals a ₀ to a ₁₃ from the fourteen external address signals A _{0 to} A ₁₃ , respectively, and generates a decoder circuit (R-DCR,
C-DCR, GS).

The internal control signal generation circuit COM-GE includes two external control signals CS * (chip select signal), WE
(Write enable signal), CS1 (row decoder control signal), SAC (sense amplifier control signal), W
e (write control signal), DOC (data output buffer control signal), DIC (data input buffer control signal), and the like.

The circuit operation of the S-RAM IC shown in FIG. 3A will be described with reference to the timing chart of FIG. 3B.

All the operations in this IC, that is, the address setting operation, the read operation, and the write operation are performed only while one external control signal CS * is at the low level. At this time, if the other external control signal WE * is at a high level, a read operation is performed, and if it is at a low level, a write operation is performed.

First, the address setting operation and the reading operation will be described.

The address setting operation is performed by the external control signal CS *.
Is low level, it is always performed based on the address signal applied during this period. Conversely, the external control signal C
By setting S * to a high level, an address setting operation and a read operation based on an undefined address signal can be prevented.

When the external control signal CS * becomes low level, the row decoder R-DCR receives the high level internal control signal CS1 synchronized with this signal and starts operating.
The row decoder (also word driver) R-DCR is 8
Decodes the type of complementary pairs address signal _{a 0 ~ a 5, a 12} ~ a 13 selects one word line, for driving the high level.

On the other hand, four memory arrays M-ARY1 to M-ARY1
One of M-ARY4 is selected by memory array selection signals m1 to m4, and one complementary data line pair (for example, D11, D11 *) in one selected memory array (for example, M-ARY1) is a column. Selected by a decoder (eg, C-DCR1).

In this way, one memory cell is selected (address setting).

The information of the memory cell selected by the address setting operation is one of the divided common data line pairs.
And amplified by a sense amplifier (for example, SA1).

In this case, four sense amplifiers SA1, S
One of A2, SA3 and SA4 is selected by the memory array selection signals m1 to m4, and the selected 1
Only one sense amplifier has high level internal control signal SA
It operates while receiving C.

As described above, the four sense amplifiers SA1, SA
The power consumption can be reduced by disabling three sense amplifiers that do not need to be used among SA2, SA3, and SA4. The outputs of the three sense amplifiers in the non-operating state are in a high impedance (floating) state.

The output signal of the sense amplifier is amplified by the data output buffer DOB, and sent out of the IC as output data Dout from the input / output terminal I / O.

The data output buffer DOB operates while receiving the high-level control signal DOC.

Next, the write operation will be described.

When the external control signal WE * goes low, a high-level control signal We synchronized with the external control signal WE * is applied to the common data line dividing transistors (Q ₁ , Q ₁ *;...).
Q ₄ , Q ₄ *) applied to the common data line pair CDL, C
DL * are commonly connected.

On the other hand, the data input buffer DIB amplifies the input data signal Din from the outside of the IC through the input / output terminal I / O while receiving the low-level control signal DIC, and amplifies the common data line DIN. Vs. CDL, C
DL *.

The input data signal on the common data line pair CDL, CDL * is written to the memory cell M-CEL determined by the address setting operation.

FIG. 4 shows the internal configuration of an S-RAM integrated circuit (hereinafter referred to as IC) having a storage capacity of 16 k bits and an output of 8 bits.

Each of the 16 kbit memory cells has 12 memory cells.
8 examples (ko) x 16 rows (columns) = 2048 bits (2
It is composed of eight matrices (memory arrays M-ARY1 to M-ARY8) having a storage capacity of (k bits), and each matrix is arranged on the left and right sides of the row decoder R-DCR by four.

Row-related address selection lines (word lines WL1
To WL128, WR1 to WR128), 2 ⁷ = 128 decoded output signals obtained based on the address signals A _{0 to} A ₆ are transmitted from the row decoder R-DCR.

As described above, the memory of each matrix -M-
CEL is word lines WL1 to WL128, WR1 to WR1
28 and a complementary data line pair D1 described later.
1, D11 * to D132, and D132 *.

The word line intermediate buffers MB1, MB
2 are word lines WL1 to WL128, WR1 to W, respectively.
It has an amplifying action to minimize the delay time at the end of R128, and is arranged between M-ARY2 and M-ARY3 and between M-ARY6 and M-ARY7.

The address signals A _{7 to} A ₁₀ are used to select one column from each of the eight matrices.

The column decoder C-DCR provides 2 ⁴ = 16 different column select decode output signals based on the address signals A _{7 to} A ₁₀ .

The address buffer ADB generates eleven pairs of complementary address signals a ₀ to a ₁₀ from the eleven external address signals A _{0 to} A ₁₀ , respectively, and generates a decoder circuit (R-DCR,
C-DCR).

The internal control signal generation circuit COM-GE includes three external control signals CS * (chip select signal) and WE *
(Write enable signal), OE * (output enable signal), CS1 (row decoder control signal), CS12 (sense amplifier and data input buffer control signal), WC (write control signal), DOC (data output buffer) Control signal).

In this embodiment, a circuit as shown in FIG. 5 is used as the data input buffer circuit DIB in the S-RAM having the above configuration.

In this embodiment, the p-channel MOSF
ETQ ₁ and Q ₂ and n-channel MOSFETs Q ₃ and Q ₄
In CMOS NOR circuit configured 2 input (positive logic to the high level "1") is used.

[0054] to the gate of one input is MOSFET Q _2, Q ₄ of the NOR gate circuit, the control signal D
IC is applied and the other input, MOSFET Q ₁ ,
The gate of Q ₃ are connected to the input output terminal I / O.
Then, the control signal DIC is the output signal of the NAND gate circuit G ₁ receiving internal chip select signal CS ₁ and the internal write enable signal WE '*.

The data output buffer circuit DOB whose output terminal is connected to the input / output terminal I / O has the following circuit configuration. In this data output buffer DOB, the control signal DOC has a logic "1" (+ Vc
In the case of c), the output Vout becomes a logical value according to the input In, and a very low output impedance is obtained.
When OC is "0", Vout is at an undefined level unrelated to the input In, that is, a very high output impedance is obtained. As described above, a buffer having both high and low output impedances can be used for a plurality of buffer outputs.
Enables d-OR.

In the final stage, a bipolar transistor Q _{9 having} a large driving capability is provided so that a heavy load can be driven at a high speed.
There are used, Q ₉ constitute a push-pull circuit with large N-channel MOSFET Q ₁₀ of the drive capability than the P-channel MOSFET.

[0057] Control signals DIC of the data input buffer circuit DIB, when the chip select signal CS * is high (internal chip select signal CS ₁ is at the low level) is set to turn on the MOSFET Q ₄ at a high level, the MOSFET Q ₂ Turn off.

[0058]

Therefore, the output level of the input / output terminal I / O is set to the low level irrespective of the level of the input / output terminal I / O.

When the chip select signal CS * goes low and a read operation is performed, the write enable signal WE * remains high (the internal signal WE is low) and does not change. Remains unchanged at the high level. Therefore, until the read data is output from the data output buffer circuit DOB, the input / output terminal I / O is at an intermediate level under high impedance and the MOSFETs Q ₁ and Q ₃
Of the MOSFET Q ₂
Is turned off, so that a large through current does not flow. Therefore, no noise is generated on the power supply lines Vcc and GND, and the malfunction can be prevented.

[0060] In particular, to 8-bit input-output terminal I / O ₁ not shown in the embodiment of FIG. 4 S-RA having I / O ₈
In the case of M, the above eight-fold through current can be prevented from flowing through the power supply line, so that the effect is great.

Since the generation of the through current can be prevented, the power consumption can be reduced.

In the write operation, the write enable signal WE * goes low, the internal signal WE 'goes high, and the control signal DIC goes low, so that the input / output terminal I / O receives The write data is transmitted to the next stage.

The present invention is not limited to the above embodiment.

The control signal DIC may be any signal as long as it controls the data input buffer circuit DIB so as to accept data from the input / output terminal only during the write operation as described above.

The input terminal of the data input buffer circuit DIB, the input terminal of the data output buffer circuit DIB, and the output terminal of the data output buffer circuit DOB may be shared outside the IC.

The specific circuit configuration and system configuration of the S-RAM can be variously modified.

[0067]

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a conventional technique;

FIG. 2 is a timing diagram thereof.

FIG. 3A is a block diagram showing one embodiment of the present invention;

FIG. 3B is a timing chart thereof.

FIG. 4 is a block diagram showing another embodiment of the present invention;

FIG. 5 is a circuit diagram showing one embodiment of the data input buffer and the data output buffer circuit.

[Explanation of symbols]

DIB: data input buffer, DOB: data output buffer, I / O: input / output terminal,

Claims (3)

(57) [Claims] 1. A data output buffer having a tri-state output function of sending an output signal to the external terminal, the signal input is commonly connected to the outer portion terminal to one input terminal
Input signals from the force terminal is supplied, consists CMOS logic circuit control signal formed based on the chip select signal and a write / read control device signals is supplied to the other input terminal,
When a write operation is instructed by the control signal,
A data input buffer adapted to take in an input signal from a signal input terminal , wherein the data input buffer is supplied with an input signal from the signal input terminal to a gate,
N-channel M whose drain is connected to the output point
The source-drain between the OSFET and the power supply terminal of the circuit and the output point.
Connected to the N-channel MOSFET
And perform complementary operation to respond to the input signal from the signal input terminal.
P-channel MO for providing an output signal to the output point
Between the SFET and the power supply terminal of the circuit and the ground potential point of the circuit.
N-channel MOSFET and P-channel MOS
The source-drain is connected directly with the FET,
The switch is controlled by the control signal supplied to the gate.
MOS type RAM which is characterized by comprising a switch MOSFET to be pitch control. Wherein said outer portion terminal and the signal input terminal and its data output buffers and the data input buffer corresponding to <br/> consists of n, each selected memory cell of one at the same time 2. The MOS type RAM according to claim 1, wherein said MOS type RAM is provided corresponding to n memory arrays. 3. The switch MOSFET according to claim 1, wherein
P channel connected in series with the channel MOSFET
Consists Switches MOSFET, the data input buffer, contact of the output point and the circuit
The drain-source is connected to the ground potential point and
Complementary operation for P-channel switch MOSFET
With N-channel switch MOSFET
The first term claims, wherein the door or paragraph 2, wherein
MOS type RAM.