JPS58125291A - Mos static type ram - Google Patents

Abstract

PURPOSE:To prevent noise generation and to reduce power consumption by controlling FETs of an input buffer circuit and preventing a feedthrough current from flowing during reading operation. CONSTITUTION:When a chip selecting signal CS' goes down to a low level to start reading operation, a control signal DIC outputted from the NAND gate G1 of an input buffer circuit DIB is still at a high level because a write enable signal WE' is at the high level, thereby turning off a PMOSFETQ2. Therefore, an I/O has an intermediate level of high impedance and even when FETs Q1 and Q3 among PMOSFETQ1, NMOSFET Q3, Q4 forming a two-input CMOS NAND gate circuit together with FETs Q2 are both turned on, feedthrough currents flowing through the FETs Q1 and Q3 are interrupted. Consequently, noise generation based upon the feedthrough currents is prevented to obtain an MOS static type RAM with less power consumption.

Description

[Detailed description of the invention] This invention butterfly, VO day (vertical body in metal insulator) static! ! ! Regarding IRAM (Random Threatened Access Memory).

In Mo8, (vertical type RAM (hereinafter referred to as B-RAM), its data input and output gates are commonly connected,
When sending and receiving data on a common data bus,
The inventor of this application has provided 8-RAM internal power supply @(voo,
It has been found that relatively large noise is generated in the ground (GND).

As a result of examining the causes of the above-mentioned noise generation, the inventor of the present application found that the cause was as follows.

Conventionally, in the 8-RAM, as shown in FIG. 1, a data support circuit is used, and a large through current flows at the start of the evening output operation, causing large noise in the internal power supply line.

That is, as shown in the operational waveform diagram of FIG. 2, when the chip selection signal 11 becomes low level, the internal control signal 08' also changes to low level.

Then, the p-channel M0 receiving this signal O8''i
87ITQ1 is turned on, n-channel MOEIFICT
Q is turned off, and its output level is determined according to data from input/output terminal I10.

However, during a read operation when the write/read control signal wm is at a low level, the input/output end check 10 is in a high impedance state until read data from the data output buffer circuit DOB is transmitted to the input/output end check 10. It is at an intermediate level.

My friend, the p-channel MO8FIITQ+ and the n-channel k MOB F W T Q B dl from the human-powered parachutes that receive this intermediate level data are K.
#7, a large through current will occur, causing noise in the power supply circuit. This noise is caused by the selection operation of memory cells! ! The amplification operation of the outgoing sense amplifier is given a unique effect, and l
a# Causes production. Sorry, the above through current is 8-RA
Increase the power consumption of M.

An object of the present invention is to prevent the generation of noise and to provide a static filRAMi of the next MO8.

Another object of the present invention is to provide an MO8 static type RM M11t with low power consumption.

Still other objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be described in detail along with examples of implementation.

The third diagram shows the internal configuration of a B-RAM integrated circuit (hereinafter referred to as "Product") having a storage capacity of 16 bits and 1 bit.

16 bit memory cells each with 128 columns (o)
It consists of four matrices (memory arrays M-RYI to M-RY4) with a storage capacity of x32h (power?me) = 4096 bits (4 bits), and each matrix is placed on the left and right of the row decoder R-DOR. It is arranged in two parts.

Address selection layer of rota yarn (word @WL 1 ~ WL 1
28, WR1~WR128) Kd, Ato L/S scar number A
, ″-As, 2′=25 obtained based on MK
6 pieces of 9 decode output fI or a decoder R-DOR
It will be sent out.

In this way, each matrix's memory M-011iL contains words 11WLI to WL128. Any one of WRI to WR128 and a complementary data line pair Dll and DI, which will be explained later.
1 to D132 and D132.

Address signals S, A- are used to select only one of the four memory matrices. Address signals M7 to M2 are used to select one column in one selected memory matrix.

The memory matrix selection signal G8 is decoded into four combinations based on the address signals MU, MU.

Column decoders (5-DORI to 0-DOR4 are 2''=3 based on 1 for the above address signals A7 to All, respectively)
Two column selection phase decode output signals are provided.

Common data line pair ODL during reading.

ODL is a transistor for common data line IIl (Q+
.

Q++...: Q4 + Q4)K Therefore, each mail array is divided into four parts, and the common data 11ODL and CD'La are commonly combined at the time of writing.

Sense amplifiers 8M1, 8M2, 8A3, and 8A4 are provided corresponding to the divided common data line pairs ODL and 0DLK, respectively.

In this way, the common data line pairs ODL and 0DLI are divided, and each has a sense amplifier 8Al, 8mm2゜Smu3, 8mm4
t-The aim is Common Day 1 @ vs. ODL, ODL
It is possible to increase the speed of the memory cell information read operation by reducing the amount of memory cell information by 1.

The address path family DB has 14 external address signal groups.
~14 complementary address signals from M1 to ILo, respectively.
~1mk was created and the decoder circuit (R-DOR, 0-DO
R, G8).

The internal N signal generation circuit 00M-GIC has two external controls @
Upon receiving the signal τi (chip select (No. 1), Wl (write enable signal),

It sends out signals such as W decoder control signal), 8mC (sense amplifier control signal), W. (write control signal), DOO (data output puffer control signal), and D0 (data output puffer control signal).

The operation of the @3AK shown TB-RAMIQC) circuit will be explained according to the timing diagram of FIG. 3-B.

All operations in this process 0 include address setting operations,
Read operation and write operation are performed by one external control signal O8.
This is done only during low level periods. At this time, if the other external control signal wi is at a high level, a read operation is performed, and if it is at a low level, a write operation is performed.

First, address setting operation and read operation will be explained.

The address setting operation is always performed based on the address signal applied during this period when the external control signal CB is at a low level. Conversely, by setting the external control signal 08Q to a high level, address setting operations and read operations based on uncertain address signals can be prevented.

When the external control signal 08 becomes low level, the row decoder R-DORFi receives the high level O internal control signal osH- synchronized with this signal and starts operating. Complementary pair address signals a--kame S of the row decoder (plex word driver) R-pou#18all.

a+**a+st# Read to select one word at- and drive it high.

On the other hand, four memory arrays M-MURYI to M-MURY
One of the four memory array selection signals m1 to m
4, the selected one memory array H
One complementary data enzyme pair (e.g. Dll, Dll) or column decoder (or
For example, 0-DORI).

In this way, one memory cell is selected (address setting)
be done.

The information of the memory cell selected by the address setting operation is divided and sent to 11 of the next common data layer pair, where it is amplified by the sense amplifier <IPIILIdBm1).

In this case, four sense amplifiers B 1.8 MU 21 S MU 3
, 81, which one is the memory array selection signal m
1 to m4, and only one selected sense amplifier operates while receiving a high-level internal control signal 8m0.

In this way, four sense amplifiers SM1. Smu2゜8mu3,
It is possible to reduce power consumption by making three sense amplifiers that do not need to be used among the eight memory blocks non-operating. The outputs of the three sense amplifiers in the non-operating state are in a high impedance (floating) state.

The output signal of the sense amplifier is amplified by the data output buffer DOB, and output data D is output from the input/output terminal check 10. u
It is sent to the outside as t.

The data output puffer DOB operates while receiving the high level control signal DOOQ.

Next, the write operation will be explained.

When the external control signal Wll becomes low level, the high level control signal W@ synchronized with this or the common data dividing transistor (Q+ +QI:...;Qa
, Qa) and the common data line pair ODL
.

ODL or common combination.

On the other hand, during the period when Fi is receiving the low level control signal DIOI from the data capacitor 7aD, the input data signal D1n passed from the outside of the device 0 through the input/output terminal 10t is amplified and the common data line connected to the common data line Send to ODL and CDL.

The input data signal on the common data line pair ODL, ODL is written into the memory cell M-01L determined by the address setting operation.

FIG. 4 shows the internal configuration of an 8-RAM integrated circuit (hereinafter referred to as IC) having a capacity of 16 bits and an output of 8 bits.

16 bit memory cells each with 128 columns (rows)
x16 rows (column piece 2048 bits (bit notation in 2)
Eight matrices (memory array M-AR
YI to M-ARY8), and each matrix is divided into four and arranged on the left and right sides of the row decoder R-DOR.

address selection #II (word *WL+1~WL
128. WRI to WR128), address number A,
The row decoder R-DOR sends out 2'=128 p decoded output signals obtained based on .

In this way, the memory M-OEL of each matrix includes one of the words IIWLI to WL128 and WRI to WR128 and a complementary data line pair Dll and D, which will be explained later.
ll-D132, D132.

Note that the word line intermediate buffers MBI and MB2 have an amplification effect of 1[in order to minimize the delay of 1sjl' in the arrival of words @WLI to WL128 and WRI to WR128, respectively, and perform M-RY2, M-ARY3, and M-RY2, M-ARY3, and M
It is arranged between M-MU RY6 and M-MU RY7.

Address signal? =Al@ is then used to select one column from each of the above eight matrices.

Column decoder o-DcRFi above address signal m, ~
Aquarium. Provides 2'=16 decoded output signals during column selection based on .

External address signal A of address parameter DBHII
Each of the 11 pairs of complementary address signals ao-
Create IL+ot and decoder circuit (4-DOR, 0-D
OR).

Internal control KI (Iif signal generation circuit COM-GF!
signal)? In response, C3l (o utecoder control signal),
C! Ei12 (sense amplifier and data controller control signal) 1w-c (writing system flJ@), DOO
(Data output cover sofa control signal) $1-Exit.

In this embodiment, a circuit as shown in FIG. 5 is used as a substitute for the seven data buffer circuits in the $11 S-FjAM.

In the actual example with p-channel MO871'rQ+
+ Two-man C, consisting of Ql, n-channel MO8FKTQs, and Qa! The MO8 Nant gate circuit (in the case of positive logic with 'l' at high level) is used.

MO8ν which is the manual power of one side of the above Nant gate circuit G1
”The gate of Qa + Qa has the above control signal
is applied, and the other input is MO8F K T Q
The gate of 1 + Q l is connected to the input/output terminal I10. The control signal generator 0 has an internal chip select signal 08 and an internal write enable signal wm.
'2 receiving Nantes gate circuit G.

It is said to be the output signal of

The data output buffer circuit DOB whose output terminal is connected to the input/output terminal check 10 has the following circuit configuration. In this data output buffer DOB, when the control signal DOO is logic '1' (+V0°), the output is V. ut enters the crab.

Theory 8 according to this! III[, and a very low output impedance is obtained, and when DOO is % 01, vo
ut is at an undefined level that is not related to the output voltage, that is, a very high output impedance is obtained.

In this way, a buffer with both high and low output impedances t- has multiple buffer outputs Wlr@1-OR'kOr
Be female.

In the final stage, a bipolar transistor Q- with large drive capacity is used to drive heavy loads.
Q@ is the y-channel MOB1 which has a larger driving capacity than the P-channel MO8FIT! It forms a push-pull circuit together with MTQll.

When the chip select signal CB is at a high level (the internal chip select signal 08i is at a low level), the control signal generator 0 from the data manual buffer circuit is turned on at a high level.
MO8FJ] 1TQst off.

In the past, the output level was set to low level regardless of the level of the input/output terminal I/O.

Now, when the chip select signal o8 is at a low level trap and a read operation is performed, the write enable signal W1 or K is at a high level (internal signal Wll and sub-control signal C do not change to the above-mentioned high level 0 case. , until successive data is output from the data output buffer circuit DOB.

The above MO8FITQ can also be used to turn on both MO8FMTGLt and Qst when the input/output trend is at an intermediate level under high impedance.

Since it is off, no large through current will flow. Therefore, no noise is generated on the power supply line v0° and GND, and the above-mentioned operation can be prevented.

In particular, the 8-bit input/output terminals I10+ to I10. as shown in the implementation example of Figure g4. In the 8-RAM that has
This is highly effective since it is possible to prevent a through current that is 8 times the above amount from flowing through the power supply line.

Further, since the generation of the above-mentioned through current can be prevented, it is possible to reduce power consumption.

Note that during a write operation, the write enable signal wr goes to low level, so the internal signal Wr goes to low level, and the above control signal DIOtP goes to low level. I will tell you step by step.

This invention is limited to the embodiments described above.

The control i11 signal DIO may be any signal as long as it is t-controlled by the data manual buffer 7 circuit so as to accept or accept data from the input/output terminal only during the write operation as described above.

Alternatively, the input terminal of the data input 8777 circuit and the output terminal of the data output balance circuit DOB may be made common to the outside of the factory.

The specific circuit configuration and system configuration of the 8-RAM can be modified in various ways.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the advantages of the prior art. Diagram 2 is its timing diagram. FIG. 3A is a block diagram showing an embodiment of the present invention. FIG. 3B is its timing diagram. , @
FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. 5 is a circuit diagram showing an actual data input buffer and data output buffer circuit IIIAPlt. 3rd B <FEAD CYCLFn<WPITEC>'CLEn

Claims (1)

[Scope of Claims] (1) Two data output/output circuits 77 are configured with a 0M08 logic circuit that receives an internal control signal manually and receives external write data at the other input. In a static type RAM that is commonly connected to an input terminal connected to an input, the above internal control signal is a chip selection signal and a write/write signal.
The MO8 static@RAM02 is characterized in that: (1) the data buffer circuit controls the chip to be selected by the read control signal and to accept or accept write data from the outside only during a write operation; , n sets of data output puff circuits and data input buffer circuits are prepared, and n sets of memory static WRAs are prepared.
M.O.