JPS6218992B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a decoder circuit for a static semiconductor memory device.

(2) Background of the technology Memory density has been increasing steadily in recent years, but in the case of static RAM, as the storage capacity increases, the load current on the bit line also increases.
The load capacity increases and the operating speed decreases. To solve this problem, we divided the memory cell array into multiple pieces to reduce the charging current flowing through the bit lines.
The present inventor has proposed a semiconductor memory device that combines this with word line division selection to further reduce memory power consumption (Japanese Patent Application No. 1987-
(See No. 141655). An exemplary circuit diagram of this device is shown in FIG. In this example, the memory cell array is divided into two in the word line direction and the bit line direction to form four memory cell array blocks _BK0 to _BK3 . Along with the formation of this block, the word lines X ₀ to _{X N-1} and the bit lines Y ₀ to _{Y M-1} are also divided at the center. Word decoder 1 receives the block selection signal and selects word lines X ₀ to _{X N-1} or X ₀ ' to _{X N}
' Select _{the −1} side. Further, word decoder 1 receives an address input signal and selects one of word lines X ₀ to _{X N-1} or X ₀ ' to _{X N} ' _-1 . Column decoders CD and CD' select the divided bit line in the same way as the word line, and the memory cell at the intersection of the selected word line and bit line is selected, and its memory contents are read out by the sense amplifier SA. , or information can be stored in the memory cell. The present invention relates to an improvement of the word decoder section in this device.

(3) Prior art and problems In the semiconductor memory device described above, which aims to reduce memory power consumption by dividing the memory cell array, one of the word lines X ₀ to _{X N-1} is selected from the input address signal. Conventionally, a logic circuit as shown in FIG. 2 has been used as a circuit for selecting. The address input signals A ₀ to _{A N-1} are divided into signals A ₀ to _{A N-1} and ₀ to _N-1 by an address buffer (not shown) and are applied to the inputs of the NOR gates. A NOR gate has n input terminals, and its first input terminal receives an input signal.
A ₀ or ₀ is input, the input signal A ₁ or ₁ is input to the second input terminal, and the input signal A o-1 or A _{o-1 or 1} is input to the n-th input terminal in the same manner.
_o-1 is entered. Since all different combinations of these input signals correspond to each NOR gate, the number N of NOR gates is 2n. The output of each NOR gate is the word line X ₀ to _{X N-1,} respectively.
connected to. This circuit has each signal input A ₀ ,
₀ , A ₁ , ₁ , ..., A _o-1 , _o-1 are each N/
Since it is connected to two NOR gate input terminals, the load capacitance of the address buffer becomes large and there is a problem that the access time of the storage device becomes slow.

(4) Purpose of the Invention In view of the problems of the conventional circuit described above, the purpose of the present invention is to develop a word address buffer based on the idea that the word address signal is turned on and off by the signal of the most significant bit of the word address input. The purpose of this invention is to reduce the load capacity of the storage device, thereby shortening the access time of the storage device.

(5) Structure of the Invention In the present invention, a decoder circuit of a semiconductor memory device that selects a memory cell at an intersection of a word line and a bit line selected by a decoder inputting an address input signal output from an address buffer has a matrix-like structure. The memory cell array is divided into two sets of memory cell array blocks each having a word line and a bit line, and the address input signal supplied to the address decoder of each memory cell array block is divided into the highest address input signal and its inverted signal. Accordingly, there is provided a decoder circuit for a semiconductor memory device characterized by comprising a gate circuit configured to turn on/off address input signals remaining after excluding the most significant bit.

(6) Embodiment of the Invention A circuit diagram of a decoder circuit of a semiconductor memory device as an embodiment of the present invention is shown in FIG. 3, and a more detailed example in the case where the word address input is 7 bits is shown in FIG. It can be done.

Word address inputs A ₀ -A _o-1 are divided into A ₀ -A _o-1 and ₀ - _o-1 by an address buffer not shown and applied to the inputs of the circuit of FIG. The upper part surrounded by the dashed line corresponds to the upper part of the word decoder 1 in FIG.
The lower part surrounded by the dashed line similarly corresponds to the lower part of the word decoder. In the circuit in the upper half of Fig. 3, the input signals A ₀ , ₀ , A ₁ ,
₁ , . . . , A _o-2 , _o-2 are turned on or off by the transistor 31 operating as a gate depending on whether the signal A _o-1 is at a high level or a low level. One transistor 31 is provided for each input signal circuit.
are inserted in series. One transistor 32 is provided for each input signal circuit on the output side of the transistor 31, and when the transistor 31 is non-conductive, the level of the output line connected to the output thereof is held at a high level. transistor 3
1 output is connected to one input of NOR gate 33. The NOR gate 33 has (n-1) inputs, and its first input terminal has A ₀ or _0.
An input signal of A 1 or 1 is connected to the second input terminal through the transistor 31, and in the same manner, an input signal of A ₁ or ₁ is connected to the (n-1)th input terminal through the transistor ₃₁ .
₂ or _o-2 input signals are connected through transistor 31. Since NOR gates 33 are provided corresponding to all combinations of input signals, in the case of an n-bit address input, N gates are required in the entire circuit of FIG. 3, and there is a relationship of N=2n. In the circuit in the upper half of Figure 3, the Noah gate 3
3 is N/2, and transistor 31 is z(n-
(n-1) transistors 32 are used, and the same number of each element is used in the lower half circuit. In FIG. 3, all MOS transistors used as gates in each input circuit are designated by the reference numeral 31, the depletion type MOS transistor 32 is similarly designated by the reference numeral 32, and the NOR gate is designated by the reference numeral 33.

The circuit in the lower half of FIG. 3 is the same as the circuit in the upper half of FIG. 3, except that _o-1 is used instead of A _o-1 as a signal for turning on and off the transistor 31. The outputs of the NOR gates 33, of which there are N in total, are connected to word lines X ₀ to X _N-1 , respectively. When all inputs of this NOR gate 33 are at low level, a word line is selected. In the circuit described above, for example, the output _A0 signal of the address buffer is connected to N/2 input terminals of the NOR gate in the circuit shown in FIG.
In the circuit shown in Figure 3, the transistor 31 is always turned on only in either the upper half or the lower half, so it is connected to N/4 input terminals of the NOR gate, and the address buffer load is the same as the conventional one. This will be half the time compared to .

The circuit diagram of FIG. 4 is shown to explain in more detail the case where the word address signal of the embodiment of FIG. 3 is 7 bits. The transistors 31 and 32 in FIG. 3 correspond to the transistors 41 and 42 in FIG. 4, respectively, and the aggregate of NOR gates 33 corresponds to the NOR gate aggregate 43. According to this, although the number of transistors 41 and 42 is increased compared to the circuit shown in FIG. 2, the number of output lines of the address buffer 44 is increased from 14 to 14.
It can be seen that the number of NOR gate inputs is reduced to 12, and the load on the address buffer 44 is reduced from 64 to 32 NOR gate inputs. In the figure, Vcc is the power supply voltage (positive side),
Vss represents the return side of the power supply.

(7) Effects of the Invention According to the present invention, the load capacity of the word address buffer can be reduced, thereby shortening the access time of the storage device.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor memory device for explaining the present invention, FIG. 2 is a circuit diagram showing a conventional decoder circuit in a semiconductor memory device, and FIG. 3 is a semiconductor memory as an embodiment of the present invention. A circuit diagram of the decoder circuit of the device, FIG. 4 is a detailed circuit diagram of the circuit of FIG. 1...Word decoder, 31...Transistor, 32...Depression type transistor, 3
3... Noah gate, 41... Transistor, 42
...Depression type transistor, 43...Nor gate aggregate, 44...Address buffer,
BK ₀ , BK ₃ , BK ₂ , BK ₃ ...Memory cell array block, CD, CD'...Column decoder, MC ₀ ,
₀ ~ MC _N-1 , _M-1 ...Memory cell, X ₀ ~ _{X N-1} ,
X ₀ ′ ~ X _N ′ _-1 ...Word line, Y ₀ ~ _{Y M-1} , ₀ − ~ Y
_M-1 , _Y'0 ~ _{YM' -1} , ₀ '~ _{M' -1} ...Bit line.

Claims (1)

[Claims] 1 In a decoder circuit of a semiconductor memory device that selects a memory cell at the intersection of a word line and a bit line selected by a decoder inputting an address input signal output from an address buffer, a matrix-shaped memory cell array is connected to a word line and a bit line, respectively. The address input signal supplied to the address decoder of each memory cell array block is divided into two sets of memory cell array blocks each having a line, and the address input signal supplied to the address decoder of each memory cell array block is determined by the most significant address input signal and its inverted signal, excluding the most significant bit. 1. A decoder circuit for a semiconductor memory device, comprising a gate circuit configured to turn on and off an input signal.