GB2163616A

GB2163616A - A memory device

Info

Publication number: GB2163616A
Application number: GB08520743A
Authority: GB
Inventors: Kinya Mitsumoto; Shinji Nakazato; Hideaki Uchida; Akira Ide
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1984-08-22
Filing date: 1985-08-19
Publication date: 1986-02-26
Also published as: KR860002099A; GB8518670D0; JPS6151692A; GB8520743D0; KR870002654A; DE3530088A1; GB2163616B

Abstract

A memory device in which a switching element (QE1) is interposed between two data lines (D1001, D1001) pairing to each other, that the conduction of the switching element is controlled by a selecting signal applied to other switching elements (Q1001, Q1001) for the data lines, and that when the data lines are in a non-selected state, the switching element is rendered conductive, thereby to reduce the difference of the potentials of the two data lines. Since the potential difference between the pair of data lines is reduced under the non-selected state, the potentials of the respective data lines are rapidly changed to a high level and a low level on the basis of information stored in a memory cell when the non-selected state has been switched to a selected state, so that a period of time in which the information is read out can be shortened. Moreover, since the switching element is controlled by utilizing the data line selecting signal, any special control signal generator is not required, and circuitry is not especially complicated. <IMAGE>

Description

SPECIFICATION A memory device The present invention relates to a semiconductor memory device.

Recently, static RAMs have been significantly enlarged in capacity and increased in speed as described, for example, in the journal "Nikkei Electronics" published by Nikkei McGraw-Hill, Inc., dated September 26, 1983, pp. 125-139.

The inventors conducted research from the viewpoints of even further enlarging the capacity and increasing the speed of a static RAM, and have developed a technology in which a static RAM is constructed using both bipolar transistors and MOS transistors. The technology will be outlined below.

In an address circuit, a timing circuit, etc., within a semiconductor memory, an output transistor for charging and discharging a signal line of long distance and an output transistor of large fan-out are made of bipolar transistors, while logic circuits for executing logical processes, for example, inversion, non-inversion, NAND and NOR, are made of CMOS circuits. The logic circuit made of the CMOS circuit is of low power consumption, and an output signal from this logic circuit is transmitted to the signal line of long distance through the bipolar output transistor of low output impedance.Since the output signal is transmitted to the signal line by the use of the bipolar output transistor having the low output impedance, the dependence of a signal propagation delay time upon the stray capacitance of the signal line can be lessened, and this function makes it possible to fabricate a semiconductor memory of low power consumption and high speed.

On the basis of the above SRAM technology of high speed and low power consumption employing the bipolar/CMOS hybrid technique, the inventors further studied shortening access time to the memory cells. As a result, it has been revealed that when word lines and data lines are simultaneously changed-over in a data reading mode, the change-over of the data lines lags over the change-over of the word lines. This forms a cause for prolonging the access time. The situation will be explained with reference to Fig. 5.

Fig. 5 is a circuit diagram of the memory cell portion of a static RAM which was studied by the inventors before the present invention. By way of example, let us consider a case where a memory cell M5 is now selected and where a memory cell M8 is to be subsequently selected.

When the memory cell M5 is selected, a word line W1 is at a high level (H), so that transfer MOSFETs m180 and m190 are ON in a memory cell M7. Therefore, a pair of complementary data lines D2 and D2 become high (H) and low (L) levels in accordance with the information of the memory cell M7 respectively, and a large potential difference exists between the pair of complementary data lines D2 and D2. When word lines and data lines have been changed-over in order to subsequently select the memory cell M8, the potentials of the pair of complementary data lines D2 and D2 are slowly inverted into the low (L) and high (H) levels, respectively, this time in accordance with the data of the memory cell M8 because, as seen from the figure, the data stored in the memory cell M8 is reverse to the data stored in the memory cell M7.

For this reason, the period of time in which the data line potentials are switched and stabilized becomes long, and this undesirably increases the access time.

The present invention has been made in view of the problem described above.

An object of the present invention is to provide a memory device the access rate of which is raised without considerably complicating the arrangement thereof, and a typical aspect of performance of the present invention will be briefly summarized below.

Each pair of complementary data lines is furnished with a circuit for reducing the potential difference of the corresponding pair of data lines, and this circuit is controlled by a Y (column) select signal so as to reduce the potential difference between the pair of complementary data lines during a non-selected state, whereby the change-over rate of the complementary data lines is raised to consequently achieve enhancement in the access time.

In the accompanying drawings: Figure 1 is a circuit diagram showing the general circuit arrangement of a memory device according to the present invention; Figure 2 is a circuit diagram showing more concretely the circuit arrangement of essential portions in the memory device shown in Fig.

1; Figure 3 is a timing chart showing an example of operation of the memory device shown in Fig. 2; Figure 4 is a circuit diagram of the essential portions of a memory device showing another embodiment of this invention; and Figure 5 is a circuit diagram of the memory cell portion of a memory device which was studied by the inventors before the present invention.

Embodiment 1 Now, a typical embodiment of this invention will be described with reference to the drawings. First of all, the general arrangement of a RAM will be explained in conjunction with Fig.

1.

Shown in Fig. 1 is the internal arrangement of a static RAM whose storage capacity is 64 kilobits and whose inputs and outputs are executed in single-bit units. Various circuit blocks enclosed with a broken line IC are formed in a single silicon chip by semiconductor integrated circuit technology.

The static RAM of the present embodiment has four matrices (memory arrays M-ARY1 to M-ARY4) each having a storage capacity of 16 kilobits (=16384 bits), thereby to have the total storage capacity of 64 kilobits (=65536 bits).The four memory arrays M-ARY1 to M ARY4 have arrangements similar to one another, and each of them has memory cells arranged in 128 rows X 128 columns therein.

An address circuit, which serves to select a desired memory cell from among the memory arrays each having the plurality of memory cells, is constructed of an address buffer ADB, row decoders R-DCR0, R-DCR1 and R DCR2, column decoders C-DCR1 to C-DCR4, column switches C-SW1 to C-SW4, etc.

Though not especially restricted, a signal circuit which handles the reading and writing of information is constructed of a data input buffer DIB, data input intermediate amplifiers DIIA1 to DllA4, a data output buffer DOB, a data output intermediate amplifier DOIA, and sense amplifiers SA1 to SA16.

Though not especially restricted, a timing circuit which serves to control the operations of reading and writing information is constructed of an internal control signal generator circuit COM-GE and a sense amplifier select circuit SASC.

Decode output signals produced on the basis of address signals A0-A8 are sent from the row decoders R-DCR1 and R-DCR2 to the address select lines of the row group (word lines WL11-WL1128, WL21-WL2128, WR11-WR1128, and WR21-WR2128). Each of the row decoders R-DCR1 and R-DCR2 are connected to row decoder R-DCR0 which has a function of selecting one of R-DCR1 or R DCR2. Among the address signals A0-A8, those A7 and A8 are used for selecting one memory matrix from among the four memory matrices M-ARY1 through M-ARY4.

The address buffer ADB receives address signals A0-A15, and forms internal complementary address signals aO-a15 based on them. The internal complementary address signal sO is composed of an internal address signal aO which is inphase with the address signal A0, and an internal address signal aO which is phase-inverted to the address signal A0. The remaining internal complementary address signals a1-a15 are similarly composed of internal address signals al-a15 and internal address signals al-a 15.

Among the internal complementary address signals aO-a15 formed by the address buffer ADB, those a7, a8 and a9-a15 are supplied to the column decoders C-DCR1 through C DCR4. The column decoders C-DCR1 through C-DCR4 decode these internal complementary address signals, and supply select signals obtained by the decoding (decode output signals) to the gate electrodes of switching insulatedgate field effect transistors (hereinbelow, termed "MISFETs") 01001. Q1001, Q1128, Q1128, 02001, Q2001, 03001, Q3001, Q4001, Q4001, etc., within the column switches C-SW1 through C-SW4.

One word line designated by the combination of the external address signals A0-A8 is selected from among the word lines WL11-WL1128, WL21-WL2128, WR11-WR1128, and WR21-WR2128 by the row decoders R-DCR 1 and R-DCR2 stated above, while one pair of complementary data lines designated by the combination of the external address signals A7, A8 and A9-A15 is selected from among a plurality of pairs of complementary data lines Do 001, D1001-D1128, D1128; D2002, D2002-D2128, D2128; D3001, D3001-D3128, D3128; and D4001, D4001-D4128, D4128 by the column decoders C-DCR1 through C-DCR4 and the column switches C-SW1 through C-SW4 stated above. Thus, the memory cell M-CEL located at the point of intersection between the selected word line and the selected pair of complementary data lines is selected.

In a reading operation, switching MISFETs 01, Q1-Q4, Q4; Q5, Q5 (not shown); Q8, Q8; 09, 09 (not shown); Q12, 012; 013 and Q13 (not shown); and 016, 016 for M ARY1-M-ARY4, respectively, are brought into "off" states by a control signal WECS delivered from the internal control signal generator circuit COM-GE, though this is not especially restrictive. Thus, common data lines CDL1, CDL1-CDL4, CDL4 and the write signal input intermediate amplifiers DIIA1-DIIA4 are electrically decoupled.Bias circuits for the pair of common data lines are comprised of a plurality of MISFETs, B1-B4, B5-B8 (not shown), B9-B12 (not shown), and B13-B16 (not shown) for M-ARY1-M-ARY4, respectively, and are brought into "on" states when the corresponding memory array is selected by a control signal CS1, CS2, CS3 or CS4 derived from COM-GE. The information of the selected memory cell is transmitted to the common data lines through the selected pair of complementary data lines. The information of the memory cell transmitted to the common data lines is sensed by the corresponding one of the sense amplifiers SAl-SAl 6, and is externally provided through the data output intermediate amplifier DOIA as well as the data output buffer DOB.

In the present embodiment, 16 sense amplifiers are provided. Among these sense amplifiers SAl-SAl 6, one sense amplifier, namely, the sense amplifier whose input terminals are coupled to the selected pair of complementary data lines through the common data lines, is selected by a sense amplifier select signal S1,S2 ... or S16 from the sense amplifier select circuit SASC and carries out the sens ing operation.

In a writing operation, switching MISFETs Q1, 01-04, Q4; Q8, 08; 012, 012; and Q16, 016 are brought into "on" states by a control signal WECS from the internal control signal generator circuit COM-GE. In a case where, by way of example, the column decoder C-DCR1 has brought the switching MIS FETs Q 1001 and 01001 into "on" states in accordance with the address signals A7-A15, the output signals of the data input intermediate amplifier DIIA1 are transmitted to the pair of complementary data lines D1001 and D1001 through the pair of common data lines CDL1 and CDL1 as well as the MISFETs Q1 and Q1, and 01001 and 01001.If the word line WL11 is selected by the row decoder R DCR1 on this occasion, information corresponding to the output signals of the data input intermediate amplifier DIIA1 is written into the memory cell disposed at the point of intersection between this word line WL11 and the complementary data lines D1001, D 1001.

Though not especially restricted, the pair of common data lines CDL1 and CDL1 are composed of four common data line pairs (sub common data line pairs) in the present embodiment. In the figure, two of these four common data line pairs are shown. Likewise to the illustrated common data line pairs, the remaining two common data line pairs are adapted to be coupled to the data input intermediate amplifier DIIA1 through the switching MlSFETs 02, 02 and Q3, 03 respectively.

The input terminals of one sense amplifier and the input/output electrodes on one side, of the switching MISFETs numbering 32 are coupled to each of the four common data line pairs. That is, the input terminals of the sense amplifier SA1 and the input/output terminals of the switching MISFETs 01001, 01001-01032, Q1032 are coupled to the first common data line pair; the input terminals of the sense amplifier SA2 and the input/output terminals of the switching MISFETs 01033, Q1033-Q1064, 01064 are coupled to the second common data line pair; the input terminals of the sense amplifier SA3 and the input/output terminals of the switching MISFETs 01065, 01065-01096, Q1096 are coupled to the third common data line pair; and the input terminals of the sense amplifier SA4 and the input/output terminals of the switching MISFETs 01097, 01097-01128, 01128 are coupled to the fourth common data line pair. In the writing operation, these four common data line pairs are electrically coupled to one another through the switching MISFETs Q1, Q1-Q4, Q4, whereas in the reading operation, they are electrically decoupled from one another. Thus, stray capacitances to be coupled to the input terminals of the sense amplifier can be diminished in the reading operation, so that the speed of the reading operation can be raised.By the way, in the reading operation, only the sense amplifier whose input terminals are coupled to the sub common data line pair, to which the information from the selected memory cell has been transmitted through the switching MIS FETs, is selected and carries out the sensing operation. The other common data line pairs CDL2, CDL2-CDL4, CDL4 have arrangements similar to that of the common data line pair CDL1, CDL1 described above. The internal control signal generator circuit COM-GE is constructed in accordance with well-known principles to receive two external control signals, namely, CS (chip select signal) and WE (write enable signal) and generate a plurality of control signals CS1, CS2, CS3, CS4, WECS, WECS, DOC, etc.

Similarly, the sense amplifier select circuit SASC is constructed in accordance with wellknown principles to receive the chip select signal CS and the internal complementary address signals a7-s15 and form the sense amplifier select signals S1 to S16 described above and internal chip select signals CS, CS.

These signals CS and CS may contribute, for example, to low power consumption by conducting constant currents used for the sense amplifiers "off" state when the IC chip is not selected (CS=H level).

In the above, the general arrangement of the static RAM has been briefly explained. Noteworthy here is that the respective pairs of complementary data lines are provided with MISFETs QE1-QE4128 for reducing the potential differences between the data lines, the conduction control of which is performed by the column select signals produced from the column decoders (C-DCR1 through C-DCR4). In addition, whereas the MISFETs 01001, 01001-04128, 04128 as the column switches are n-channel MISFETs (n-MIS), the MIS FETs QE1-QE4128 for reducing the potential differences between the data lines are p-channel MISFETs (p-MIS).

That is, the p-MISFETs QE1-QE4128 and the n-MISFETs 01001, Q1001-Q4128, 04128 have their conduction controls performed complementarily by the column select signals.

Accordingly, when the pair of complementary data lines is non-selected (in other words, when the column select signal is at the low (L) level), the corresponding one of the p-MIS FETs QE1-QE4128 for reducing the potential difference between the data lines turns "on" to reduce the potential difference of the nonselected pair of complementary data lines. In contrast, when the column select signals provided from the column decoders (C-DCR1-C DCR4) have become the high (H) level, the n MISFETs 01001, 01001-Q4128, Q4128 being the column switches turn "on", while at the same time the MISFETs QE1-QE4128 for reducing the potential differences between the data lines turn "off", whereby the operation of equalizing the potentials of the pair of complementary data lines ends automatically.

Fig. 2 is a circuit diagram which shows more concretely part of the memory device illustrated in Fig. 1.

The embodiment shown in the figure is so constructed that the stored information written in the selected memory cell is read out through common data lines CDL1, CDL2 as well as a sense amplifier or a read sense circuit SA1, and that such common data lines CDL1, CDL2 and read sense circuits are disposed in a plurality of divided groups. More specifically, in this 64-kilobit RAM, the common data lines CDL1, CDL2 and the read sense circuits are disposed in 16 divided groups, any of which is selected and activated.In Fig. 2, circuits which have a logical symbol whose output side is marked black are quasi CMOS circuits wherein an output transistor for charging and discharging the stray capacitance of an output signal line is made of a bipolar transistor and wherein a logical process such as inversion, non-inversion, NAND or NOR is executed by a CMOS circuit. Address buffer ADB, a part of column decoder C-DCR1 and word line drivers WD1 and WD2 in row decoder R-DCR1 are shown as examples of the quasi CMOS.

Also, circuits using an ordinary logical symbol are pure CMOS circuits. As shown in Fig.

2, in the address buffer ADB, there are arranged non-inverting and inverting circuits G7-G15 which receive the address signals A7-A 15 of TTL levels at their inputs from outside by way of example and which supply their complementary output signal lines with the non-inverted outputs a7-a15 and the inverted outputs a7-a 15. The output transistors of the non-inverting and inverting circuits G7-G15 are made of the bipolar transistors as stated above. Therefore, even when the output signal lines of the non-inverting and invert- ing circuits G7-G15 are arranged over long distances on the surface of the semiconductor chip, these non-inverting and inverting circuits G7-G15 can be operated at high speed.

Next, the column decoder C-DCR1 will be briefly described.

It includes 2-input NAND circuits G74-G77, G78-G81 and G82-G85 and 3-input NAND circuits G86-G93 to which the internal address signals a7-a 15 and a7-a 15 derived from the address buffer ADB are applied.

Further, the output signal lines of the NAND circuits G74-G93 are arranged to extend over relatively long distances and are connected to the input terminals of a large number of NOR circuits G94-G95 within the column decoder C-DCR1. Therefore, the stray capacitances of the output signal lines of these NAND circuits G74-G93 have large capacitance values.

Accordingly, the 3-input NAND circuits G86-G93 are constructed of quasi CMOS 3input NAND circuits whose output transistors are bipolar, and the 2-input NAND circuits G74-G85 are constructed of quasi CMOS 2input NAND circuits whose output transistors are bipolar.

On the other hand, since the output signal lines of the 3-input NOR circuits G94-G95 are connected to the inputs of inverters G100-G101 with short distances, the capacitance values of the stray capacitances of the output signal lines of these 3-input NOR circuits G94-G95 are small. Accordingly, these 3input NOR circuits G94-G95 are constructed of pure CMOS 3-input NOR circuits.

Further, since the output signal lines of the inverters G100-G101 are connected to the input terminals of 2-input NOR circuits G98-G99 with short distances, the capacitance values of the stray capacitances of the output signal lines of these inverters G100-G101 are small.

Accordingly, these inverters G100-G101 are constructed of well-known pure CMOS inverters.

In the same sense as the quasi CMOS circuits in the address buffer ADB and column decoder C-DCR1, word line drivers including bipolar transistors as output transistors thereof can be operated at high speed.

Next, the memory cell M-CEL of 1 bit which constitutes the memory array M-ARY will be described.

The memory cell M1, for example, is composed of a flip-flop in which the inputs and outputs of a pair of inverters consisting of load resistors R1, R2 and n-channel MISFETs m15, m16 are cross-connected, and n-channel MlSFETs m13, m14 which serve as transfer gates.

The flip-flop is employed as means for storing information. The transfer gates are controlled by the address signal which is applied to the word line X1 connected to the row decoder (X decoder), and the transmission of the information between the pair of complementary data lines D1001, D1001 and the flip-flop is controlled by the transfer gates.

In the reading operation, MOS field effect transistors Ql and Q1 of read/write circuit 100 are brought into "off" states by the write control signal WECS, and the information stored in the memory cell is read out through the data output intermediate amplifier DOIA and data output buffer DOB as well as the read sense circuit SA1 which has been activated by a read sense circuit-selecting signal S1 produced from the read sense circuit-selecting circuit SASC. A circuit B1 comprising MISFETs Z1-Z4 functions as a bias circuit for the common data lines CDL1 and CDL2 during the reading operation. More specifically, each common data line CDL1 and CDL2 is biased in accordance with the on-resistance ratio of Z2/Z4 and Z 1 /Z3, respectively, when the WECS signal level represents the read mode in a chip selected condition (WECS=H level) and CS1 level represents the memory array or mat selected condition (CS1=H level).

In the writing operation, the MOS field effect transistors Ql and Ql are brought into "on" states, while the read sense circuit SA1 is brought into an "off" state by a read sense circuit-selecting signal S1, and the bias circuit B1 does not supply any bias to common data lines CDL1 and CDL2 so that input data is written into a predetermined memory cell through the data input buffer DIB as well as the data input intermediate amplifier circuit DIIA.

Now, let us consider a case where the memory cell M1 is selected and where the memory cell M4 is to be subsequently selected. When the memory cell M1 is selected, the output (column select signal) of the 2input NOR circuit G99 is at the low (L) level, and a p-MISFET m31 for reducing the potential difference of the pair of complementary data lines turns "on" to reduce the potential difference of the non-selected data lines D1002 and D1002. Next, when the output of the 2-input NOR circuit G99 has become high (H), n-MISFETs QE2 and Q1002 connected to the pair of complementary data lines D1002 and D1002 are rendered conductive, and approximately simultaneously therewith, the p MISFET QE2 for reducing the potential difference of the data lines is turned "off", whereupon data is read out.

More specifically describing the reduction of the potential difference, the p-MíSFET m31 works as an impedance when it turns "on" and the current flows from the data line D1002 with high potential to the data line D1002 with low potential through the impedance. Accordingly, the potential of the data line D1002 can decrease while the potential of the data line D1002 can be raised.

Fig. 3 shows as a timing chart an example of operation in the reading mode of the memory device illustrated in Fig. 2.

In Fig. 3, sym Ai denotes an address select signal, symbols X1, X2 denote row select signals for selecting the word lines W1, W2, and symbols Y1, Y2 denote column select signals for selecting the data lines. Here, note is taken of the data lines D1002 and D1002 which are selected by the select signal Y2.

First, when these data lines D1002 and D1002 are in the non-selected state, the reduction of the potential difference is steadily performed as described above, regardless of the potential level with "high" or "low" of the word line W1 or W2. Thus, the potential difference between the data lines D1002 and D1002 under the non-selected state is reduced from Vw' to Vw (in the figure, dotted lines indicate the potential changes of the data lines in the case where the present invention is not applied). Next, at the same time that the data lines D1002 and D1002 have been selected, the potential equalizing operation is ended, and the column switches are rendered conductive. Then, the respective potentials of the selected data lines D1002 and D1002 are complementarily changed in accordance with the stored content of the selected memory cell M4.At this time, the selected data lines D1002 and D1002 are respectively changed into the low (L) and high (H) levels according to the stored content of the selected memory cell M4 quickly with a small potential amplitude, because the potential difference Vw between the lines has been sufficiently reduced in the non-selected state beforehand.

Owing to the fact that only the data lines under the non-selected state are subjected to the potential equalizing operation in the way described above, the potentials VL1 and VL2 of the respective common data lines L1 and L2 switch as illustrated in Fig. 3, and the period of time required for the switching of the potentials of the data lines on the occasion of selection can be shortened to Tod 1 from Tpd3 in the prior art. This makes it possible to shorten a read access time Taa. Further, it is to be noted here that the period of time for executing the potential difference reducing operation is not one that has to be specially inserted. Instead, the potential difference reduction is effected by utilizing the so-called idle time during which the data lines are in the non-selected state.Thus, any time loss for the potential difference reduction is avoided, and the read access time Taa can be sharply shortened. Moreover, the operation timing control of the potential difference reduction can be performed automatically by the Y select signal for selecting the data lines without resorting to any special timing signal. Thus, the arrangement for the timing control is extremely simple. In addition, special margins need not be set for the switching of the data line potential difference reduction MISFET, and the provision of this MISFET does not prolong the access time at all.

The size of the p-MISFET m31 may be designed as small as W/L=10,am/2,um=5, for example, where W and L are gate width and gate length, respectively. The resistance of the p-MISFET at its "on" state needs to be a significant value. If this resistance is too low, the retention of stored information might be adversely affected by alpha particles. Also, the stored information of the memory cell M3 might be destroyed through the transfer gates m18 and m19 which are turned "on" by the high potential level of the word line W1, as the result of the potential difference of the pair of the data lines D1002 and D1002 being reduced too much.

In our commercial product 64K static RAM, W/L of the p-MISFET is employed with 10/2=5 and about 8kQ of on-resistance. Preferably, the range of on-resistance of the p MISFET may be 5-20 kQ. Of course, the invention is not limited to these values since other values might be appropriate depending on the particular circuit construction.

The p-MiSFET m31 having W/L=5 may be obtained by arranging within an area located between the conductors which are to be the pair of data lines, whose pitch is 13cm, for example. In accordance with this arrangement, the MISFET for reducing the potential difference can be formed for layout in integrated circuit form on the semi-conductor chip without requiring a large space.

Embodiment 2 Fig. 4 shows another embodiment of this invention.

In the embodiment illustrated in the figure, two p-channel MOS field effect transistors m300 and m300' are used for each pair of data lines in order to equalize potentials. Only the pair of data lines D1 and D1 in the nonselected state is connected to, for example, a power source Vcc thereby to reduce the potential difference between the lines. Even the arrangement in which the selected pair of data lines is connected to a fixed potential in this manner can attain an effect similar to that of the foregoing embodiment.

Effect In a memory device wherein the stored content of a selected memory cell is read out by detecting potentials which appear on selected data lines, a potential difference reducing circuit which reduces the difference of the potentials of data lines in non-selected states is provided for each pair of data lines and has its conduction controlled by a Y select signal, whereby the switching time of the states of the selected data lines can be shortened by the simple additional arrangement and without especially inserting a period of time for potential difference reduction. This brings forth the effect that a read access time can be efficiently shortened.

While, in the above, the invention made by the inventors has been concretely described in conjunction with embodiments, it is needless to say that this invention is not restricted to the foregoing embodiments, but that it can be variously altered within a scope not departing from the subject matter thereof. For example, the pair of data lines may well be such that only one of them has its potential changed in accordance with the stored content of a selected memory cell, while the other is a dummy to which a reference potential is applied. Also, although the transistors for reducing data line potential differences (e.g. QE1, etc.) have been shown as MISFETs, it is to be understood that other switching elements could be used including, for example, bipolar transistors.

Applicability While, in the above, the invention made by the inventors has been chiefly described as to the case of applying it to MOS type static RAM technology which forms the background field of utilization thereof, it is not restricted thereto but is also applicable to, for example, a ROM or a dynamic RAM. The invention is applicable to devices which include, at least, the condition that the stored content of a selected memory cell is read from a potential change.

Claims

1. A memory device including: (a) a plurality of memory cells which store information therein; (b) an address circuit which selects a specified memory cell from among said plurality of memory cells; and (c) a plurality of word lines and a plurality of pairs of complementary data lines, which transmit signals between said memory cells and said address circuit; wherein said each pair of complementary data lines is provided with a potential difference reduction circuit which reduces a potential difference between the pair of complementary data lines under a non-selected state and which is controlled by a complementary data line pair-selecting signal produced from said address circuit.

2. A memory device according to Claim 1, wherein said potential difference reduction circuit is constructed of a switching element one end of which is connected to one of two data lines constituting said pair of complementary data lines, and another end of which is connected to the other data line.

3. A memory device according to Claim 2, wherein said switching element is an insulated-gate field effect transistor.

4. A memory device according to Claim 3, wherein the respective data lines are connected with said address circuit through MISFETs of a first conductivity type, the MISFET as said switching element is of a second conductivity type, and the complementary data line pair-selecting signal produced from said address circuit is applied to input terminals of said MISFETs of the first and second conductivity types in common.

5. A memory device according to Claim 1, wherein said potential difference reduction circuit is constructed of a plurality of switching elements which are interposed in series between two data lines constituting said pair of complementary data lines and whose operative states are controlled in common by the complementary data line pair-selecting signal produced fromsaid address circuit, and a fixed potential is applied to a middle point of a series path which is formed of said plurality of switching elements.

6. A memory device according to Claim 5, wherein the respective data lines are connected with said address circuit through MISFETs of a first conductivity type, said plurality of switching elements are MIS FETs of a second conductivity type, and the complementary data line pair-selecting signal produced from said address circuit is applied to -input terminals of said MISFETs of the first and second conductivity types in common.

7. A memory device according to Claim 1, wherein active elements which constitute said each memory cell are MISFETs of a first conductivity type, and said address circuit is constructed of MISFETs of the first conductivity type, MISFETs of a second conductivity type, and bipolar elements.

8. A memory device according to Claim 7, wherein said bipolar elements in said address circuit are elements for charging and discharging signal lines of long distances, and driving elements of large fan-out.

9. A memory device according to Claim 1, wherein said memory device is a static memory device.

10. A memory device constructed and arranged to operate substantially as herein described with reference to Figs. 1 to 4 of the accompanying drawings.

11. A memory device comprising: a plurality of memory cells which store information therein; a plurality of word lines and a plurality of pairs of complementary data lines coupled to said plurality of memory cells so that each memory cell is coupled to a word line and a pair of complementary data lines; an address circuit coupled to said word lines and to said complementary data line pairs, said address circuit including means for selecting predetermined memory cells by producing a word line selection signal to select a predetermined word line and producing a complementary data line pair-selecting signal to select a predetermined pair of complementary data lines; and potential difference reduction means coupled to each of said pairs of complementary data lines and said address circuit, said potential difference reduction means including means for reducing a potential difference between the respective data lines of pairs of complementary data lines which are not selected by said address circuit.

12. A memory device according to claim 11, wherein said potential difference reduction circuit is constructed of a plurality of switching elements each of which is respectively connected to two data lines constituting a pair of complementary data lines.

13. A memory device according to claim 12, wherein said switching elements are insu lated-gate field effect transistors.

14. A memory device according to claim 13, wherein the respective data lines are connected with said address circuit through MIS FETs of a first conductivity type, wherein the switching element MISFETs are of a second conductivity type, and wherein the complementary data line pair-selecting signal produced from said address circuit is applied to input terminals of said MISFETs of the first and second conductivity types in common.

15. A memory device according to claim 11, wherein said potential difference reduction circuit is constructed of a plurality of switching elements which are each respectively interposed in series between two data lines constituting said pair of complementary data lines and whose operative states are controlled in common by the complementary data line pairselecting signal produced from said address circuit, and wherein a fixed potential is applied to a middle point of a series path which is formed of said plurality of switching elements.

16. A memory device according to claim 15, wherein the respective data lines are connected with said address circuit through MIS FETs of a first conductivity type, wherein said plurality of switching elements are MISFETs of a second conductivity type, and wherein the complementary data line pair-selecting signal produced from said address circuit is applied to input terminals of said MISFETs of the first and second conductivity types in common.

17. A memory device according to claim 11, wherein active elements which constitute each said memory cell are MISFETs of a first conductivity type, and wherein said address circuit is constructed of MISFETs of the first conductivity type, MISFETs of a second conductivity type, and bipolar elements.

18. A memory device according to claim 17, wherein said bipolar elements in said address circuit are elements for charging and discharging signal lines of long distances, and driving elements of large fan-out.

19. A memory device according to claim 11, wherein said memory device is a static memory device.

20. A memory device comprising: a plurality of memory cells which store information therein; a plurality of word lines and a plurality of data line pairs connected with said memory cells so that each memory cell is connected to a word line and to a pair of data lines; an address circuit connected with the word lines and with said data line pairs, including means for selecting a specified memory cell from among said memory cells by producing a word line selecting signal to select a predetermined word line and by producing a data line pair selecting signal for selecting a predeter mined data line pair; a read-out circuit connected with a pair of data lines coupled to a memory cell selected by said address circuit and which derives the stored information from the selected memory cell; and a plurality of electrical circuits respectively associated with each of said pairs of data lines, wherein each of which electrical circuits is activated when the pair of data lines to which it is connected are non-selected.

21. A memory device according to claim 20, wherein each of said electrical circuits is formed of a switching element connected between the respective pair of data lines to which it is coupled.

22. A memory device according to claim 21, wherein said switching element is an insulated-gate field effect transistor.

23. A memory device according to claim 22, wherein the respective data lines are connected with said address circuit through insulated-gate field effect transistors of a first conductivity type, wherein the switching element insulated-gate field effect transistor is of a second conductivity type, and wherein the data line pair-selecting signal produced from said address circuit is applied to input terminals of said field effect transistors of the first and second conductivity types in common.

24. A memory device according to claim 20, wherein said each electrical circuit is formed of a plurality of switching elements which are interposed in series between the pair of data lines and whose operative states are controlled in common by the pair of data lines pair-selecting signal produced from said address circuit.

25. A memory device according to claim 24, wherein a fixed potential is applied to a middle point of a series path which is formed of the switching elements.

26. A memory device according to claim 24, wherein the pair of data lines are connected with said address circuit through insulated-gate field effect transistors of a first conductivity type, wherein said switching elements are insulated-gate field effect transistors of a second conductivity type, and wherein the data line pair-selecting signal produced from said address circuit is applied to input terminals of said field effect transistors of the first and second conductivity types in common.

27. A memory device according to claim 20, wherein active elements which constitute said each memory cell are insulated-gate field effect transistors of a first conductivity type, and wherein said address circuit is formed of insulated-gate field effect transistors of the first conductivity type and a second conductivity type, and bipolar elements.

28. A memory device according to claim 27, wherein said bipolar elements in said address circuit are elements for charging and discharging signal lines of long distances, and driving elements of large fan-out.

29. A memory device according to claim 20, wherein said electrical circuit has a predet- ermined value of impedance set to reduce a potential difference between the pair of data lines.

30. A memory device according to claim 29, wherein said predetermined value of impedance is in a range between 5kQ and 20kin.

31. A memory device formed in a semiconductor chip comprising: a plurality of memory cells which store information therein; a plurality of word lines and a plurality of data line pairs connected with said memory cells so that each memory cell is connected to a word line and to a pair of data lines; an address circuit connected with the word lines and with said data line pairs, including means for selecting a specified memory cell from among said memory cells by producing a word line selecting signal to select a predetermined word line and by producing a data line pair selecting signal for selecting a predetermined data line pair; a read-out circuit connected to a pair of data lines coupled to a memory cell selected by said address circuit and which derives the stored information from the selected memory cell; and a plurality of electrical circuits respectively associated with each of said pairs of data lines, wherein each of said electrical circuits is activated when the pair of data lines to which it is connected are non-selected, each of said electrical circuits being so arranged within an area interposed between the pair of data lines to which it is connected.