JPS61120393A - Address decoder circuit - Google Patents

Abstract

PURPOSE:To reduce the size of an address decoder circuit by using transistors (TR) to which common address signals are inputted in common, and connecting remaining TRs of respective address decoders to said TRs in parallel and constituting plural address decoders. CONSTITUTION:An address decoder 20 which selects a word line W0 when address signals A0, A1, A2, and A3 are all at a high level and an address decoder 21 which selects a word line W1 when the address signals A0, A1, A2, and A3 are all at the high level share the n channel TRs T3, T4, and T5 to which those common address signals A1, A2, and A3 are inputted at their gates. Other TRs of the address decoders 20 and other TRs of the address decoder 21 are connected in parallel to the series circuit of those shared TRs T3 T4, and T5, and the address decoders 20 and 21 constitute one unit.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an address decoder circuit and a RAM.

The present invention relates to an address decoder circuit (particularly a row address decoder circuit) for selecting an address for each memory cell in a ROM or the like.

[Conventional technology]

FIG. 6 schematically shows the overall configuration of this type of memory, in which some of the address signals A0 to A (for example, A0 to A , ) are used for row selection, and the remaining portions (for example, A, .1 to A,) are used for column selection.

That is, address signals A0 to A are passed through the row address register 3 to Ao, τ. ,AI,τ,·-A,,A.

These address signals are input to the row address decoder group 2, and the word line connected to the output side of a specific row address register is selected according to the state of each address signal.

On the other hand, the remaining address signals AI+1 to AI80 are passed through the column address register 5 to A. , 1,1m + I + '
-' A n +T7, and each of these address signals is input to the column address decoder group 4, and a specific column address decoder is selected according to the state of each address signal, and the selected column address decoder Depending on the output of each column selector 70°71, -7
N is the column selector 70 from the memory cell array 1
, 71, -71 respectively, one pair is selected and connected to input/output lines X, , X, , -Xl, respectively.

Furthermore, a clock signal CK and a write enable signal WE
etc. are sent to CK, ■, and ridge through register 6.

The clock signal controls the operation of each address register 3, 5, and the clock signal and write enable signal are used for each column selector.
0, 71, -7 A to control reading or writing through the selector.

In the figure, block 70 shown as a column selector
,71. -71 includes a read amplifier, a write amplifier, an output sofa, and the like.

As is clear from the above description, the row address decoder group used for row selection of the memory cell array receives the address signal (A11.λ-, A I
n A In-A-, A, ) depending on the state of
It is composed of a plurality of row address decoders (2'' in this example) from which a row address decoder is selected, and one word line is connected in correspondence with each row address decoder. A row address decoder is arranged corresponding to each memory cell column in each row of the core memory cell array.

FIG. 3 shows an example of a conventional circuit for one of the address decoders. The address decoder 20 performs the following operations when all four address signals Aa, AI, Az, and A3 are at high level. This selects word line W0.

That is, the address decoder 20 receives the clock signal GK
is input to the P-channel transistor T. (The marked transistors in each figure indicate P-channel transistors) and each address signal A to its gate.

, A1. N-channel transistors T and o to which A□ and As are input, respectively.

T0n, T4°, Ts. and an inverter 201 consisting of a P-channel transistor T6 (1) and an n-channel transistor T. Note that DD is, for example, a 5-channel DC power supply.

First, while the clock signal CK is at a low level, the transistor T1° is conductive, the parasitic capacitance present on the input side of the inverter 201 is precharged, and the input side becomes high level. (Note that this precharging is performed in all address decoders while the clock signal CK is at a low level.) Next, when the clock signal becomes a high level, each address signal A0. Δ1.
Δ2. If A3 are all at high level (in other words, all their inverted signals are at low level), at that point, transistors T2°,'r,. ,T. ,T.

are all conductive (at this time, the transistor T
In the address decoder 20, the input side of the inverter 201 is at a low level, in other words, its output side is at a high level, and the word line W0 is selected. At this time, in other address decoders, at least one address signal input thereto becomes low level, so all of these address decoders become non-selected.

FIG. 5 shows the layout of such a conventional address decoder (the above-mentioned address decoder 20 as an example) using a plane pattern of each transistor. 2 corresponds to the width of one column of memory cells.

By the way, in recent years, memory cells in RAM, ROM, etc. have been gradually miniaturized due to improvements in their circuits, and the width β of the memory cells has also been reduced. It is becoming increasingly difficult to create a layout in which liquids are arranged vertically (in the vertical direction of the page) along the liquid l.

In particular, as memory capacity increases and the number of address lines increases, the number of transistors to which address signals are input also increases, making layout increasingly difficult. There was a problem that the layout had to be long and narrow in the direction (left and right direction of the page), and the efficiency of the layout was reduced.

Note that the address decoder 20 shown in FIG. 5 includes, in order from the right side, an n-channel transistor T7°, which also constitutes the inverter 201, and a p-channel transistor T7.
,. , a P-channel transistor Tl01 to which the clock signal CK is input, and address signals A@, A, to the gates thereof, respectively.

n-channel transistors Tie and Tz to which A z and A z are input; , Ta. , T5° are laterally arranged elongated, the P-channel transistors TIO and Ti0 and the n-channel transistor 'rzo.

T3゜, Ta. ,T. share a source/drain region at their connection. Further, in the figure, each address line is shown as a dotted line, among which the address lines that supply address signals A e, A r, A z, and A 3 are connected to transistors T2 and T, respectively.
3°.

T4°, connected to the gate of 'r'so.

Further, although the layout of the address decoder 20 is shown in FIG. 5, an address decoder 21 (for example, an address signal τ,
A1. A decoder that selects the word line W1 when each of A z and A 3 becomes high level is connected to the word line W1, and the row address decoder group 2 is configured in the same manner.

[Problem that the invention seeks to solve]

The present invention has been made to solve the above-mentioned problems, and for a plurality of address decoders corresponding to each memory cell column, among a plurality of transistors each receiving a predetermined combination of address signals, mutually Based on the idea of sharing only the transistors to which a common address signal is input, multiple address decoders are treated as one unit, and efficiency is improved by allowing a margin in a narrower area than the conventional example shown above. The purpose is to enable a good layout and to reduce the size of the address decoder circuit.

[Means for solving problems]

According to the present invention, there is provided an address decoder including a transistor to which a clock signal is input, and a plurality of transistors to which a specific combination of address signals is respectively input, wherein a part of the plurality of transistors has a common For a plurality of address decoders including transistors to which the common address signal is input, the transistor to which the common address signal is input is shared, and the remaining transistors in each of the address decoders are connected to the shared transistor. Address decoder circuits are provided that are connected in parallel to form the plurality of address decoders.

[For production]

According to the above configuration, the total number of transistors can be reduced by making the plurality of address decoders share the transistors to which a common address signal is input, and the plurality of address decoders can be laid out as one unit. This improves layout efficiency and makes it possible to downsize the address decoder circuit.

〔Example〕

FIG. 1 shows an embodiment of an address decoder circuit according to the present invention, in which an address signal Ao is used.

An address decoder 20 that selects word line W0 when A, , Am, and A3 are all at high level, and an address signal τ. , A In A z , and A are all at high level, the address decoder 21 selects the word line W1.
0, 21, the common address signal A
n-channel transistor T, with I, A z, and A3 each input to its gate; 3. T 4° and T5 are shared, and the shared transistor T 3
．． For the series circuit of T a and T, the other transistors in the address decoder 20 (i.e., the P-channel transistor Tl0I to whose gate the clock signal CK is input; the n-channel transistor T2 to whose gate the address signal A0 is input;゜), and the other transistors in the address decoder 21 (i.e., the P-channel transistor T1, whose gate receives the clock signal GK, and the N-channel transistor T1, whose gate receives the address signal τ) in parallel. The address decoders 2o and 21 are connected as one unit.

Note that 20 is an inverter which inverts the potential at the connection point between transistors T1° and T2° and supplies its output to the word line w0. As described above, 211 is an inverter that inverts the potential at the connection point between the transistor 711 and TZI and supplies its output to the word line W, and the transistor Th. T? It consists of +.

Then, during the period when the clock signal GK is at low level,
In each address decoder 20, 21, transistors T10 and TZI are conductive, and the connection point between transistors TIO and Tto and the transistor Tll are turned on.
The parasitic capacitance present at the connection point between T2I and T2I is precharged.

When the clock signal CK becomes high level in the next step A, the address signals A o, A + , A z, and A3 are temporarily set according to the state of each address signal at that time.
are all at high level, the potential at the connection point between transistors T1° and T2° in the address decoder 20 becomes low level, this is inverted by the inverter 201 and a high level potential is output, and the word line W0 becomes low level. selected. Also, suppose the address signal τ. ,AH,
If Az and A3 are all at high level,
The potential at the connection point between transistors Tll and TzI in the address decoder 21 becomes low level, this is inverted by the inverter 211, a high level potential is output, and the word line W1 is selected.In short, the circuit of FIG. The difference from the conventional example shown in the figure is that in the two address decoders 20 and 21,
Common address signals A +, A z, A 3 are input to the gates of the transistors T3゜T, respectively.
a. The point is that Ts is shared.

FIG. 4 shows the layout of the address decoder circuit of FIG. 1 by a plane pattern of each transistor.

As shown in the diagram, in this embodiment, two address decoders 20 and 21 are considered as one unit, and this corresponds to two memory cell columns connected to word lines W0 and Wl, respectively. Placed.

Regarding the address decoder 20, the inverter 2
N-channel transistor F that constitutes 01. , also a P-channel transistor T6゜, and a P-channel transistor T whose gate receives the clock signal CK.
The IOs are sequentially arranged horizontally, while the address decoder 2
1, the n-channel transistor F and the P-channel transistor Th constituting the inverter 211 have a clock signal GK input to their gate.
The layout is similar to that of FIG. 5 in that the channel transistors Tl+ are sequentially arranged in the horizontal direction, but as mentioned above, in the circuit of FIG. 1, the address signals A,
, A, ,A, are input to the gates of the transistors T's, T-, Ts, respectively, and the two decoders 2
0゜21 is shared, so the two decoders 2 end up
At 0°21, the transistors to which the address signal is input are T2°, TzI, T3,
A total of five transistors, T4 and T, are required, and therefore, it is possible to arrange these transistors with a margin in the vertical direction along the width 21 of the two columns of memory cells, and the horizontal length Ll of the decoder circuit is reduced accordingly. It is possible to significantly shorten the lateral length L2 of the decoder circuit shown in FIG. 5.

In FIG. 4, each address line is also shown as a dotted line, among which are address signals Ao and τ. .

A1. Δ2. A: The address lines that supply I are connected to transistors Tzo, Tz+, Ts, Ta, and T, respectively.
connected to each gate of s. Further, the clock signal CK is supplied to each gate of the transistors T, , T, , and the power supply voltage DD is applied to the transistors T11 and T, respectively. the source/drain regions of and the transistor T,. It is also shown that it is supplied to the source and drain regions of the TRI.

FIG. 2 shows four address decoders 20 and 21 as another embodiment of the address decoder circuit according to the present invention.
, 22 , and 23 are configured as one unit.

As shown in the diagram, the address decoder 20 receives address signals A O, A I, A z, -A 3. The address decoder 21 is a decoder that selects the word line W0 when all the signals are at high level. .

τ+, Az, '-'A? is a decoder that selects the word line W1 when all are at high level, and the address decoder 22 selects the word line W1 when all of the address signals Ao, τ+, Az
, -A When all y are high level, the word wAW
It is a decoder that selects Z, and is also an address decoder 2.
3 is an address signal τ. , -λ-6A2. --A7 is a decoder which selects word line W3 when all A7 are at high level.

And these four address decoders 20 and 21.

For 22 and 23, the common address signal A
! , A3. As, As, A6. Transistors Ta, Ts, T6 . T7. Tll,
T9 is shared, and the other transistors T1°, T2°, T, in the address decoder 20 are connected to the series circuit of these transistors T4 to T. , other transistors Tz + TZI + T:l in address decoder 21
+, other transistors T in address decoder 22
1□, T2□, T3□, and other transistors TI3, Ttx + T1 in address decoder 23
3 are connected in parallel, and the 4 address decoders are combined into 1 address decoder.
Construct as one unit. Note 201, 211, 221
, 231 are each address decoder 20 , 21 , 22
, 23.

In this embodiment, regarding the four address decoders,
Since the common address signals At to A7 share the transistors T4 to T whose gates are input, the total number of transistors can be reduced accordingly.
In arranging the four address decoders as one unit so as to correspond to the four memory cell columns connected to the word lines W0 to W, for example, each address decoder may be arranged in accordance with the embodiment shown in FIG. In each inverter 20
1. The transistors constituting 211, 221, and 231 and the transistors TIG to TI3 to which the clock signal CK is input to their gates are arranged horizontally, and each transistor to which the address signal is input to the gate (
That is, T2° to T0,T. It is conceivable to arrange the transistors T33 to T33 and shared transistors T4 to T9 in the vertical direction, for example, along the width 41 of the four columns of memory cells, and by performing such a layout, the horizontal length of the decoder circuit can be reduced. The fact that the length can be shortened is similar to the case of the embodiment shown in FIG.

〔Effect of the invention〕

According to the present invention, for a plurality of address decoders,
Since the plurality of address decoders are configured as one unit by sharing the transistors to which a common address signal is input, the total number of transistors to configure the plurality of address decoders is reduced accordingly. Therefore, even when memory cells are miniaturized and there are many address lines, it is possible to simplify the layout when arranging a plurality of address decoders in correspondence with each memory cell column, and to leave room in a narrow area. It becomes possible to perform efficient layout.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an address decoder circuit as one embodiment of the present invention, FIG. 2 is a circuit diagram of an address decoder circuit as another embodiment of the present invention, and FIG. 3 is a circuit diagram of an address decoder circuit as another embodiment of the present invention. A circuit diagram showing a conventional example of a decoder circuit, FIG. 4 is a plan view showing a circuit pattern when the address decoder circuit of FIG. 1 is laid out, and FIG.
FIG. 6 is a plan view showing a circuit pattern when the address decoder circuit shown in the figure is laid out, and FIG. 6 is a block diagram showing the overall configuration of a memory including this type of address decoder. (Explanation of symbols) l...Memory cell array. 2... Row decoder group, 20, 21, 22, 23... Row decoder, 4
. . . Column decoder group, 70, 71, ------ 71 . . . Column selector. Upper copy -1- Almost 1- SS

Claims (1)

[Claims] 1. An address decoder comprising a transistor to which a clock signal is input, and a plurality of transistors to which each of a specific combination of address signals is input,
For a plurality of address decoders in which some of the plurality of transistors include a transistor to which a common address signal is input, the transistor to which the common address signal is input is shared, and the shared transistor is On the other hand, an address decoder circuit characterized in that the remaining transistors in each of the address decoders are connected in parallel to form the plurality of address decoders.