JPS59132489A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent useless area from being produced in a memory array by turning on/off a switch belonging to at least the same memory block at the same time by the same decoder and reading or writing data of plural bits at the same time. CONSTITUTION:Circuit symbols MA11, MA12 are main amplifiers and five amplifiers are provided corresponding to common I/O line groups CDG1, CDG2 respectively. The data amplified in a sense amplifier SA is outputted to the common I/O line group CDG through a column swithc C-SW turned on by a column decoder C-DCR in the timing of a control signal phipa outptted from a control circuit CTL. Further, an output of a column address decoder is applied to the column switch C-SW by bringing only one of control signals phiyL and phiyR fed to a column address decoder C-DCR in response to an address signal to a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of collectively reading or writing a plurality of pinpoint data.

When configuring a memory so that data input/output can be performed in units of 1 byte (8 bits), conventionally the memory array was divided into 8 blocks MMo-MM, as shown in Figure 1.
A method has been proposed in which the memory mat is divided into seven memory mats (hereinafter referred to as memory mats), and data of one pin is read or written from each memory mat. However, in such a cloak configuration method, the input/output vanofer circuit 'r/O is drawn out from each memory mat.
Line 1, -1. The load capacity of the I10 line is large, and the load capacity of each I10 line is unbalanced. Therefore, there were disadvantages in that the access time became long and a large amount of power was required to drive the I10 line.

Furthermore, recently, in a memory having a xN bit structure such as a byte structure, there has been a demand for an odd number bit memory such as x9 bits due to the need to provide a parity bit in addition to the data bits. However, the first
The cloak configuration method shown in FIG. 5 has a problem in that when configuring an odd number of bits of memory, a wasted area (blank space) is generated in the memory array due to the layout of the memory mat.

Therefore, when configuring a memory with an xN-bit configuration, the present invention aims to shorten the access time by reducing the load capacity of the L/(J line drawn out from the memory array to the input/output cover sofa and allowing for a well-balanced design. , and the purpose is to be able to reduce power.

Another object of the present invention is to enable a memory having an odd bit configuration to be laid out without creating wasted area within a memory array, thereby reducing chip size.

The present invention will be explained below using the drawings.

- As an example, we constructed an embodiment in which the present invention is applied to a bit dynamic L (, AMC Random Access Memo!
This will be explained using FIG.

In diagram W2, IM-ARYL, M-ARY)L,
Memory capacitor and switch MO8FIEiT respectively
This is a memory array arranged in the form of a known 1MUs type memosa memory cell. Memory array M-A-YL is connected to common I10 line group 0DG as shown in the figure.
I, (31J()2 is sandwiched between a memory block M k3 of 256 rows x 4 columns and a memory block MB of 256 rows x 5 columns.
Memory mats MMI and MM2 are arranged alternately in 64 stages.
It consists of

However, in memory mats MM1 and MM2, the order of the four-column memory blocks and the five-column memory blocks is reversed. As a result, each memory mat MM1 and MM2 is configured into a 256×288 matrix. And each memory mat MMI and IVIM
In the center of 2 are row address decoders R-DCRI and R-1.
) OR2 is provided. Further, between the common I10 line groups 0DG1 and 0DG2, column address decoders 0-1)OR1 to 0- for selecting all columns (data lines) in the memory block MB located on both the left and right sides thereof are provided.
, DCR64 are installed.

In addition, common I1 of each memory block MBI to MB64
On the 0 line group 0DG1.0JJG2 side, a column address decoder 0-1) is turned on and off by 0 to 1 to C-DOR64, and the internal data line is connected to the common I10 line group C.
1) A column switch 0-8W is provided for connection to ()1,0DG2.

Furthermore, common I of each memory block IMBI to MB64
/(J line group CI) Gl, 01) A sense amplifier 8A is provided on the side opposite to G2.

Note that the memory array M on the right side indicated by the dashed line
Since the memory array M-ARYL has exactly the same structure as the memory array M-ARYL described above, the explanation thereof will be omitted.

The circuit symbol +4-ADH is a row address buffer, and an external address signal A is supplied from an external terminal. -Receive Aヮ, internal address signal, ll
i, form ai. This internal address signal - @a
1+a+ is the row address decoder R-DC)L
l, is supplied to -DCH12 to form a word line selection signal.

The circuit indicated by the circuit symbol 0'1'L is a control circuit, which receives external address signals A, .

An appropriate internal control signal φ based on the chip select signal C8 and the like. 3. Form φ8 etc.

The row address buffer 1i-ADB receives a control signal φ from the control circuit 0'II'L. Based on 5, the external address signal A is taken in, and the internal address signal ai is
, ai. In addition, the above-mentioned row Atrestecoder R-
DC general 1. -DCI (, 2 is the control circuit CT
In synchronization with the control signal φ from L, memory array M-A
RY 1. A word line selection signal is supplied to M-ARY 2.

The circuit symbol (3-ADH) is a column address buffer, which receives external address signals A8 to A3 supplied from external terminals and at the timing of control signal φ.5 from control circuit CT L. An internal address signal aJIaJ is formed based on the column address coder (, -1).
The signal is supplied to the OJ-LL to C-IJO boxes 64, and the corresponding column switch C-5W is turned on in synchronization with the control signal φ from the control circuit CTL.

Circuit symbol MAI 1. MAI 2 shows that
The main amplifier is the common I10 line group 0DGI,
Five of them are provided corresponding to 0DG2.

The control signal φ,a output from the control circuit OTL
At the timing of , the data amplified in the sense amplifier SA is sent to the column decoder 0'D (3RIIC
Therefore, the signal is output to the common I10 line group CI)G through the column switch e-SW which is turned on. Then, the data signal output to the common 110 line group C1)(),
The main amplifier M A IC is amplified at the timing of the control signal width 3 supplied from the control circuit OTL.

Circuit symbol 1 (indicated by JB is human output) < Sofa circuit, based on the control signal φrw supplied from the control circuit OTL, the 9-bit readout is amplified by the main amplifier MAVC. Connect data to external terminal.

- Input to D8 or external terminal. - Write data supplied externally to D8 to common 110i'1ii
Tell iI$01)()1.0D()2.

It should be noted that the input/output cover circuit 10B has data read from the memory array M-AbYR of the center right 11]
21 to the main amplifier M that amplifies the data, MA2
The read signal from 2 is also supplied.

In addition, the control circuit OT responds to address signals A and 4.
Column address telecoder U-DCRVC supplied from L, 1. Or, when φ9, θu5chi, -0000σ) go to low level, the output of the column address decoder is not supplied to the column switch (C8W), and the left and right memory Array M-
ARYL or to 4-ARYRσ) either - only from 10,000, main amplifier MAII.

12 and then read out to M at 21.22 and is amplified, input/output circuit, OB terminal terminal l). - So that it is output to D8, ℃
Hit.

FIG. 3 does not show a circuit diagram of a specific embodiment of the main conventional circuit shown in FIG. 1. Unless otherwise specified, MOSFETs are formed in an n-channel type. I will explain it as if it were.

In the drawing, memory array M-Ai is also shown as YL (or M-A
The memory block MB having a four-column configuration in the memory mantle MMl of 6(1j) on the left side of RYR) is representatively illustrated in only the - column to show the configuration. Each column in the memory block MB is arranged parallel to each other. Complementary data lines arranged, 1)
, switch MO8FETQ,.

The input/output nodes of each of the plurality of memory cells composed of ~Q22 and MO8 capacitors are distributed and coupled with a predetermined regularity, as shown in the figure.

A precharge switch MO8FBTQ, which is turned on and off by a timing signal φpcw, is provided between the pair of complementary data lines.

Sense amplifier S A is p-channel MO8FETQ7
．． C! consisting of Q, and n-channel MUSFET Q6゜Q@! It is composed of an MO8 (complementary MO8F'ET) latch circuit, and its pair of input/output nodes are coupled to the complementary data line, IJ. The latch circuit may also include, but is not limited to, a parallel p-channel M
(℃ power supply voltage V.0 is supplied through J S F1 No. TQ+2.Q+=, parallel form n channel x"A 0
The ground potential of the circuit is also supplied through 8 F' ET Q+n + Qu. These MOSFE'
I'Q. ~Q5. is used in common for other sense amplifiers 8A provided in the same row.

The gate of the above-mentioned MUSFET Qu+-Qtz has a complementary timing signal φp21 for activating the sense amplifier SA.
．． Magnetic tube - is applied, MO8FETQ,...

The above signals φ, a8 ., are applied to the gates of Ql, . Aiko Yu timing a little later than φpai No. 8 φ φ
The opening force should be Dpa2+ pa2. This is because when the sense amplifier SA is operated with a minute read voltage from the memory cell, the drop in the level of the data line is suppressed by using a relatively small conductance MOS F.
This is to prevent this by limiting the current by E T Q+n and Ql2.

After the voltage difference between the complementary data lines is greatly increased by the amplification operation of the sense amplifier SA, MO8I''ETQ, which has a relatively large conductance.

Turn on Q and p to speed up the amplification operation. By performing the amplification operation of the sense amplifier SA in two stages in this way, high-speed reading is performed while preventing the complementary data line from falling on the high level side.

Can you do that?

The row decoder ↓ is also -1) 0) t is shown as a representative of one circuit (eight word lines), for example, an n-channel Mo5FE that receives address signals a, ~a7.
TQ*2~Q16 minutes Yopi p Channel M (JSF E
T Q-7~Q41 Complete TeJ7-#t1. f, knee C
The eight word line selection signals described above are formed by a NAND circuit having a MOS In configuration. The output of this NANI) circuit is inverted by a CMOS inverter IVI and cut M
MO8F'ETQ through USFETQ4□~QAa
,.

~Supplied to the gate of Q57.

Also, address signal a. The eight word line selection control signals φxo to φ8□ formed by the combination of the code signals formed by , a, , a2 and the control signal φ8 are the Mo5.
It is transmitted to each word line via FE'l''Q, .~Q57.

Moreover, between each word line and the ground type 1, there is a MUsF'
B'l''Q, ~Q, is not provided, and the above N is provided at its gate.
By applying the output of the AND circuit, unselected word lines are fixed to the ground potential.

Furthermore, each word line has a reset MOS F.
E T Q An ” Q u is provided, and these MOS F E
By turning on TQ, o-Q, and l□, the selected word line is reset to the ground level.

Column switch C = 8W is representative.
, complementary data D, L), common I10 line 01J,
selectively binds to CD.

In Figure 2, the common I10 wires CD and CD are each represented by one line, but specifically, as shown in Figure 3, VC,
Each common 11 wire is formed in a pair, resulting in ten I10 wires on one side. Complementary data lines D of each column in memory block MB are coupled to corresponding common 110 lines CD, CD. However, if the memory block MB is configured in 4 columns, 5
One pair of the common 1.10 OD and CD of the pair will not be connected to the data line 1) and D.

Column switches 0-8W in the same memory block MB
Switches MO8FETQ, which constitute the.

Q, 2. A selection signal from the same column address decoder 0-DOB is supplied to the gates of .

Column address decoder O-D O)L receives internal address signals a, -a8 . NAND circuit G with input signal, and this N A N ], ) circuit G
, and the control signal φ,5 (or φ5.R) from the control circuit OTL as input signals.
It is composed of OR circuits G2 and G2'.

The above N A N'D circuit G1 receives an internal address signal a
p-channel M, 08F receiving 8~a1 at the gate
ET Q 81~Q g- and n channel A/MU
8 FE TQ117~Q92 “C0MO8
It is configured in a circuit, and when address signals a8 to a1 are all set to high level, the selection signal (low level)
form.

Further, the NOOR circuit 2 is connected in series between the power supply voltage V and the output C canode, and each gate receives a control signal φ, L (or φ, R) and the NANI) circuit G1.
p-channel MOS configured to receive the output of
P' E T Qas , a p channel M connected in parallel between Qa4 and the output node and the ground point of the circuit, whose gate receives the same signal as Q9qI QO4.
0 by OS FET Qas,Q,on
It is configured as an M08 circuit. In this r0K circuit G2, the output becomes high level when both the control signal φyL and the NAND circuit output are low level, and the four pairs of column switches M OS F E TQQ connected to the output node
10G77. ...turn on at the same time.

The NAND circuit G includes the Non4 circuit G.

A Not(circuit 02' with exactly the same configuration as that of the Not(circuit 02') is connected.However, five pairs of column switches MO5FET are connected to the output node of the N(JR circuit a2') and are turned on and off at the same time. There is.

Column switch 0-8 W also complementary data line,
A precharge MO8FETQ4n is provided between the common I10 line CD and 100cm connected to the common I10 line CD, respectively.

A main amplifier MA having substantially the same circuit configuration as the sense amplifier SA is connected to this common 1/U line OD, 01). Also, common l 10 wire CD.

The output node of the input buffer DIB is connected to the CD, and when the input buffer DIB is operated by the control signal φrw, the input data signal supplied to the external terminal IJo-D8 at that time is connected to the common line 110 (01), Send to CD4. Ru. The signal is then supplied to the complementary data line 1 through the column switch (j-8W) which is turned on by the column address decoder 0-L)OR.

In addition, if not shown, Juki common I10 line 01J.

Similarly to the above, the main amplifier MA, the input buffer DiB, and the output buffer 1) UB are connected to the other four pairs of common ilO lines other than CD, respectively.

As explained above, in the circuit of this embodiment, the memory array is composed of a plurality of memory blocks,
The data lines of each column in the memory block are connected via column switches to multiple pairs of common 1/U lines arranged in parallel to each other, and a main amplifier is connected to each common 1/U line. Further, column switches belonging to a pair of left and right memory blocks are simultaneously turned on and off by the same column address encoder, so that 9-bit data is read or written at the same time. Therefore, compared to the mat structure type memory as shown in FIG. 1, it is possible to reduce the load capacitance of the I10 line and achieve a well-balanced design. Therefore, reading data,
The writing speed) W is increased, the access time can be shortened, and the driving power of the I10 line can be reduced, thereby reducing power consumption.

Furthermore, according to the present invention, odd number bits such as ×9 bits
A memory having a node configuration can be laid out without creating any wasted area in the memory area. Further, since a decoder is shared in pairs for a plurality of column switches (nine in the embodiment), the layout is easy and the chip size can be reduced.

In the above embodiment, a case has been described in which the dynamic RAM is applied to a dynamic RAM having a ×9 bit configuration, but the present invention can also be applied to a 1(, AM) having an even bit configuration such as ×8 bits. Furthermore, the present invention can be easily applied not only to ×9-bit memory but also to other odd-numbered bit configuration memories.Furthermore, the present invention can be applied not only to dynamic l-(, AM, but also static l-LAM and) LOM (read-read memory).
It can also be applied to memory (only memory).

Furthermore, in the circuit of the embodiment, a memory block with a 4-column configuration and a memory block with a 5-column configuration are arranged on both sides of the column decoder, and a total of 9 bits of data is read out from both at the same time. However, a memory block having nine columns may be arranged only on one side of the column decoder. Furthermore, there is no need to divide the memory array into left and right halves as in the circuit of the embodiment.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing an example of a configuration method of a memory array in a conventional memory, FIG. 2 is a block configuration diagram showing an embodiment of a semiconductor memory device according to the present invention, and FIG. 3 is a diagram showing the main parts thereof. FIG. 2 is a circuit configuration diagram showing a specific example of a circuit. M-ARYL, M-, A) LYR...Memory array, M
B...Memory block, R-I)CkL...Row address decoder, C-DOR...Column address decoder, C
-8W...Column switch, CL), CD...Common data @ (common 110 line), SA...Sense amplifier,
MA...main amplifier, CTL...control circuit, IOB...input/output vanofer circuit.

Claims (1)

[Claims] 1. A memory array is composed of a plurality of memory cells or a plurality of memory blocks arranged in a matrix, and a plurality of common chips arranged in parallel to each other.
data lines of each column or row in each memory block are connected to this common data line via a switch, and at least the switches belonging to the same memory block are simultaneously turned on by the same decoder. A semiconductor memory device characterized in that it is turned off so that multiple bits of data can be simultaneously read or written.