JPS60170091A - Sensor circuit - Google Patents

Abstract

PURPOSE:To obtain stable actions with high sensitivity at a high speed and at low power consumption by providing a control means to set the 2nd sense amplifier to the enable condition by delaying the prescribed period after the 1st sense amplifier is brought into the enable condition to obtain an output from the 2nd sense amplifier. CONSTITUTION:At a time t0, potentials of bit lines BL are set, and a change is started. At a time t1 when the potential of the bit line B1 comes to be differ clearly from the other, a control signal SE1 becomes an ''H'' level, which causes MOS trasistors Q11 and Q12 to be on. Then a sense amplifier SA1 is brought into the enable condition. First, differential amplitude outputs ms and ms of the sensor amplifier SA1 are lower to the prescribed level, and at a time t2 one ms and the other start changing to ''H'' and ''L'' levels, respectively. At a time t3 when levels of the outputs ms and ms of the sense amplifier SE1 come to be different each other, a control signal SE2 becomes ''H'' level, MOS transistors Q13 and Q14 becomeon, and a sense amlifier SA2 is brought into the enable condition.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to, for example, a sense circuit in a semiconductor memory, and particularly relates to increasing the operating speed and stabilizing the operation.

[Technical background of the invention and its problems]

Conventionally, a sense circuit in a CMO8 semiconductor memory is configured as shown in FIG. 1, for example.

This circuit is called a current mirror type sense circuit, and in the figure, Q□ and Q2 are a pair of N-channel type auxiliary input MoS transistors, and Q4 is a P-channel type MO8) transistor constituting the current mirror circuit. It is. The above MOS transistors Q+, Qt
One end is commonly connected, and this common connection point and the grounding point GND
In between, there is an N-channel MOS transistor (Q) whose dart is set conductive at the power supply voltage VCC and acts as a constant current source.
.

is inserted and connected. In addition, the above MO8) transistor Q 1
The bit lines BL, BL (or data lines 5, D) are connected to the gates of +Q, respectively, and the power supply voltage V is connected to the other end through transistors Q3, Q4 (MO8), respectively.
Terminals 117.11° to which CC is applied are connected. Furthermore, the darts of the MO8) registers Q3 and Q4 are commonly connected, and this common connection point is connected to the MO8) 27
A connection point A between transistors Q1 and Q is connected. and,
Bit line hole.

Based on the potential of BL, MOS) transistor Q1. Q2
conduction is controlled, and a differential amplified output D0 is obtained from a connection point B between MOS transistors Q2 and Q4.

In the above configuration, for example, the potential of the pit line (or data line) input to the transistor Q (MOS) is constant, and the potential of the bit line BL (some b is the data fi
! When only the potential of D) changes, the output signal D0 is obtained by changing the mutual conductance gm of MOS transistor Q2, and when the potential of bit line BL is constant and only the potential of bit line n changes, , MOS transistor Q
Due to the change in the mutual conductance gm of □, the potential at the connection point A changes, and based on this potential change, the MOS) Lanzostar Q8. A sense output is obtained by changing the supply current of the current mirror circuit composed of Q4.

However, such a configuration has the disadvantage that the sensing speed is slow, and this becomes particularly noticeable when the potential level of the bit line BL changes at a level close to the power supply voltage VCC.

In order to eliminate such drawbacks and speed up the sensing operation, the present applicant proposed in Japanese Patent Application No. 58-134149 that the above-mentioned current mirror type sensing circuits were connected in cascade in two stages as shown in Fig. 2. A circuit is proposed. This circuit is
The output differentially heated by the first-stage sense amplifier 7'SA, which is made up of Most transistors Q, ~Q, is further differentially amplified by the second-stage sense circuit SA, which is made up of Mos transistors Q6 to Qlo. So, the first stage sense amplifier SA
, the output is at a sufficiently high (H'') level or low ('
The output D0 is obtained by amplifying the state of the previous small level difference set to the L#) level by the second stage sense amplifier SA.

This enables sensing operation to be faster and more sensitive than with a single-stage sense amplifier.

However, in the configuration shown in FIG.
OS) Ground point GND via transistors Qa, Qt and Q (or terminal 11, to MOS) Ground point GND via transistors Qa-Qx and Q)
DC through current flowing to the MO
S) There is a DC through current flowing through the transistors Q1, y, QV and Q to the ground point GND (or from the terminal 113 to the ground point GND through the MOS transistors Q9, Q6 and Q). For this reason, there was a drawback that the stain power consumption was greater than that of the - membrane configuration.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide an excellent sense circuit that is fast, highly sensitive, and provides stable operation with low power consumption.

[Summary of the invention]

That is, in the present invention, in order to achieve the above object, a first sense amplifier is supplied with a differential input signal, and a second sense amplifier is supplied with a differential amplified output from the first sense amplifier. In addition to providing an amplifier, a control means is provided for enabling the first sense amplifier and setting the second sense amplifier to the enable state after a predetermined period of time after a difference in output level has been established. It is configured to obtain output.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows the basic configuration. The first sense amplifier SA has differential input signals IN, , IN, (
For example, the potential of pit line hole, BL) is supplied, and its differential amplification output 0UT1. OUT is the second sense an 7'S
A, respectively. Above 1. Control signals BB, BE are supplied from the control circuit 12 to the second sense sensors SA and SA, respectively.
First, the sense amplifier SA1 is enabled by the control signal 8E, and the first stage differential amplification output OUT, OU
After there is a level difference between the control signals SE and T, the sense amplifier SA is enabled.
A differential amplification output D0 is obtained from A.

FIG. 4 shows an example of the configuration of the circuit shown in FIG. 3 above. In the figures, the same components as in FIG. 2 are given the same reference numerals, and the parts corresponding to those in FIG. 3 are given the same reference numerals, and their explanation will be omitted. That is, between the MOS transistors Q3 and Ql in FIG. 2, an N-channel MOS transistor is connected.
A transistor Q□1 is inserted and connected between the MOS transistors Q4 and Q, and an N-channel type yDS transistor Q1. Insert and connect the above MO8) transistor Q1t
, Qti are commonly connected, and the control signal sE□ is supplied from the control circuit 12 to control conduction.
) Insert and connect transistor Q□, and connect MOS ) N-channel type MOS between transistors Q1゜ and Q7.
) transistor Q14 is inserted and connected, the transistors (hs+(ha) of the above MO8) are connected in common, and the control signal BE is sent from the control circuit 12.

is supplied to control conduction.

Next, the operation of the above configuration will be explained with reference to the timing chart of FIG. First, time t0
At , the potentials of the bit lines BL and BL are set and begin to change (assuming that the bit line BL drops to the "L" level), and the difference in potential between the bit m cage and BL is established. At the starting time t□, the control signal SE1 becomes “H”.
” level.This causes the MOS transistor QI
IIQI! is in the on state, and the sense amplifier SA1 is in the enable state. At this time, the control signal SE is "L#
Since it is a level, MOS) Lannostar Q1s, Q14
is in the off state, the sense level decreases, and at the subsequent time t2, ms starts changing to the ``H# level'' and i starts changing to the ``L'' level.

Then, the output mB of the sense amplifier SE1, ma
At time t3, when a difference in the levels of 1 and 1 appears, the control signal BE becomes 6H# level, MOS 1 transistors Q1s and Q14 are turned on, and the sense amplifier SA
, becomes enabled. Therefore, sense amplifier SA
1 differential amplification output ms, “i” is senser 7fSA
2, and the output D0 becomes "L level" at time t4. In the above embodiment, the control signal S
Although EX and SE are generated by the control circuit 12, a signal obtained by delaying the control signal BE by a predetermined period of time may be used as BB.

By the way, sense amplifier SA1 and SA are enabled in a time-shifted manner.
This is because if 8A and 8A are enabled at the same time, the second-stage sense amplifier SA2 will operate before the output of the first-stage sense amplifier 7'SA1 is determined, and the output D0 will become unstable. That is, as shown in the timing chart of FIG. 6, at time t1 when the potentials of the bit lines BL and BL begin to differ, it is not determined whether the MOS transistors Ql and Ql are on or off.
When the state changes, the output side of the sense level decreases.

The potential of the shore also decreases. As a result, the MOS transistors Qa and Qy are turned off, so that during the time tl +68 until the differential amplification output mB, 1 is determined,
The ``H# level is output to the output D0.This ''H#
This level signal is supplied to the next stage circuit as noise, resulting in unstable operation and reduced reliability.

FIG. 7 shows another embodiment of the present invention, in which the present invention is applied to a sense circuit whose output becomes high impedance when disabled. In the figure, the same components as those in FIG. 4 are given the same reference numerals, and the explanation thereof will be omitted. That is, a P-channel type MOS transistor QlB is inserted between the connection point C between the MOS transistors Q9 and Qxs in FIG. 4 and the terminal 111 to which the power supply voltage VCC is supplied, and this MOS transistor Q1
A control signal SE is supplied to dart s to control conduction.

In addition, MOS as an output node of the sense angle SA
An inverter 13. whose input terminal and output terminal are respectively connected to the connection point between transistors Q1° and Ql4. ．．
A latch circuit 14 consisting of 13□ is provided.

In the above configuration, the sense amplifier SB! When enabled, MOS transistor Q18 is in an off state, so a sensing operation is performed in the same way as in the circuit shown in FIG. On the other hand, when disabled, MO8)
Ransistor Q8. is on, connection point C is “H”
MOS transistors Qe and Ql. is in the off state. Therefore, the output terminal (MOS) transistor Q□.

and Q□4) becomes a high impedance state. Note that the previous output is latched in the latch circuit 14. Of course, even in such a configuration, the same effects as in the above embodiment can be obtained.

FIG. 8 shows another embodiment of the present invention. In each of the above embodiments, the MO
S) Between the transistor and the differential input MO8) M as a switch resistor whose conduction is controlled by the control signal
(OS) A transistor was provided, whereas a MOS transistor (MOS) was used as a current source in FIG. 2.
The conduction of Qs is controlled by control signals SE□ and SE output from the control circuit 12, respectively. In the figure, the same components as those in FIG. 2 are given the same reference numerals, and their explanation will be omitted. Note that although a MOS (MOS) Lannostar Q for setting the output to high impedance and a latch circuit 14 are provided elsewhere, these may be provided depending on the characteristics required of the sense circuit.

In the above configuration, a control signal sg (“H level)” is supplied from the control circuit 12 to the MOS transistor Q.

When SA is turned on, sense amplifier SA is enabled and sense operation is performed. When a level difference occurs between the outputs ms and ms of the sense amplifier SA□, when the control signal SE (H" level) is supplied, the MOS transistor Q is turned on, and the sense amplifier SA is turned on. Sense operation is started.

Therefore, even in such a configuration, the same sensing operation as in each of the above embodiments is performed and the same effects can be obtained.

9 and 10 are for explaining other embodiments of the present invention. In each of the above embodiments, the load is of a current mirror type, but the load is of the control signal SE. P-channel type MOS whose conduction is controlled by the inverted signal of 8E) transistor Q□s+
Qst and N-channel type MOS) transistor Qt
s + Qxs. The circuit shown in FIG. 9 (sense amplifier SA) has a two-stage configuration as in each of the embodiments described above, and a control signal is supplied from each control circuit to enable the sense amplifier in the first stage of the cell and output its sense output. After a level difference occurs between m@ and ms, the second stage sense amplifier is set to the enabled state to obtain an output.

Of course, even in such a configuration, the same operation as in each of the above embodiments is performed.

FIG. 10 shows still another embodiment of the present invention, in which a latch type sense amplifier 8 is used as the second stage sense amplifier.
Ab f, provided. That is, for example, the first stage sense amplifier SA is constructed of a current mirror type,
Differential amplification output OUT of input signals IN, , IN,
, OUT, second stage latch type sense antenna f SAL
supply to. This latch type sense amplifier SAL is a P-channel type MOS transistor Q. A CMOS inverter 15 consisting of an N-channel MOS transistor Qs1, and a P-channel MOS transistor Q
The input terminal and output terminal of a CMOS inverter 16 consisting of a transistor 2□ and an N-channel type MOS transistor qzs are respectively connected to each other. The common connection point between MO8) transistors Q2° and Q2ffi is a P-channel MOS transistor Q24 which is controlled by a latch signal φL.
The connection point between the MOS transistors Q21 and Q23 is connected to the terminal 116 to which the power supply voltage VCC is applied through the N-channel MOS transistor Q2G, which is controlled by the inverted signal 5 of the latch signal φL. It is connected to the ground point GND via. One output end of the sense amplifier SA1 is connected to the connection point between the input end of the CM) S inverter and the output end of the CMOS MOS inverter, and a differential amplified output OUT is supplied to the connection point between the input end of the CMOS inverter and the output end of the CMOS inverter. CMOS inverter L! The other output terminal of the sense amplifier SA1 is connected to the connection point with the output terminal of the sense amplifier SA1, and the differential amplified output OUT is supplied.

Furthermore, at the connection point between the input end of the CMOS inverter U and the output end of the CMOS inverter, an N-channel MOS transistor Q26 controlled by the chip enable signal CE and a P channel transistor Q26 controlled by the chip enable signal a are connected. A latch circuit 14 is connected through a transmission gate E formed by connecting a transistor qzy (type MOS) in parallel, and an output is output from the latch circuit 14. get.

The latch signal φ1. The lice is supplied from the control circuit 12, and first, the control signal SE1 is sent to the sense 777''SA.
In a state where a level difference occurs in the output of the sense amplifier SA1, the latch signal φL is supplied to the second stage sense amplifier 5AL (7) to perform a sensing operation. Then, the sense output is latched by the latch circuit 14 via the transmission dirt hole.

Even in such a configuration, the basic operation is the same as in each of the embodiments described above, and the same effects can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, high speed is achieved.

It is possible to provide an excellent sense circuit that has high sensitivity, low power consumption, and stable operation.

[Brief explanation of drawings]

1 and 2 are diagrams each showing a conventional sense circuit, FIG. 3 is a schematic diagram for explaining a sense circuit according to an embodiment of the present invention, and FIG. 4 is a diagram showing a conventional sense circuit. 5 and 6 are timing charts for explaining the operation of the circuit shown in FIG. 3, and FIGS. 7 to 10 are enlarged views showing other embodiments of the present invention, respectively. FIG. IN, , IN,...Differential input signal, SA□...
1st sense anf, 0UT1. OUT,... differential amplification output of the first sense amplifier, SA,... second sense amplifier, 12... control circuit (control means), Do...
・Output signal. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 5 Figure 6 Figure 1j2

Claims (6)

[Claims] (1)' A first sense amplifier to which a differential input signal is supplied, a second sense amplifier to which a differential amplified output from this first sense amplifier is supplied, and the first sense amplifier are in an enabled state. , then after a predetermined delay,
1. A sense circuit comprising: control means for setting a second sense amplifier to an enable state, and configured to obtain an output from the second sense amplifier. (2) The sense circuit according to claim 1, wherein the sense amplifier is a current mirror type sense amplifier. (3) The sense circuit according to claim 1, wherein the sense amplifier is a latch type sense amplifier. (4) The sense circuit according to claim 1, wherein the sense amplifier is a sense amplifier having a load controlled by a chip enable signal. (5) The control means is configured to enable/r the sense amplifier.
5. A sense circuit as claimed in any one of claims 1 to 4, characterized in that it comprises switching means for setting the false state and a control circuit for controlling the switching means. (6) The second sense amplifier has means for setting the output to high impedance when disabled, and a latch circuit for latching the output. The sense circuit according to any one of .