JPS60171696A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To miniaturize constitution of a clamp circuit without hindrance to a high speed action by fixing a decoder output at the time of non-selection by low impedance in a clamp circuit. CONSTITUTION:An output terminal is connected to word lines Wn-Wn+3 of a multi-output decoder formed by an NOR circuit NOR, an NAND circuit NAND, an amplifier AMP, etc., which are simultaneously operated by a antiphase input. Said output terminal is connected to drains of clamping transistors T10-T13 whose sources are connected to grounds, etc., at a low potential. The transistors T10-T13 forming a clamp circuit by only one transistor are on by a high level output from the circuit NAND through the circuit NOR when the lines Wn- Wn+3 are not selected, and the lines are clamped to a low potential of grounding, etc., by low impedance. On the other hand, when they are selected, the decoder operates at a high speed in the same manner, and the constitution of a clamp circuit can be smaller without hindrance to an accelerated action.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor memory device, and particularly to a decoder circuit thereof.

Semiconductor memory devices are becoming larger in capacity due to miniaturization of patterns. Among these, one typical memory cell is a one-transistor memory cell that can be highly integrated. The following will be explained using an N-channel MO81 transistor memory as an example. FIG. 1 is a block diagram of an l-transistor memory. In the figure, XD is a row decoder and YD is a column decoder.

M is a memory cell 1 bit, C is a decoder output clamp circuit, 8A is a digit sense amplifier, and row decoder output signal, Wn, W11+1, ... are digit lines, and Ilo controls writing and reading. Signal line, Ax o, Ax “H”・Ax n
* and AYO.

Ays, ..., AYn are signal lines in phase with the address signal from the outside, Ax ' HAx "s ... t
Axn s and Ayo, Ay+, .

Ayn is a signal line having a phase opposite to that of the external address signal.

The negative phase signal line is the output of the address amplification circuit, and is normally at a low potential before operation.

The decoder shown in the figure is composed of a multi-input, one-output logic circuit, usually a NOR gate. Therefore.

In the figure, as many multi-input NOR gates as there are word lines are required. However, as the memory capacity increases, the number of address pits and the number of word lines increase proportionally. For this reason, if the conventional data shown in FIG. 1 is applied to a large capacity memory as is, the number of input bits to each NOR gate will increase, and a NOR gate with a large area will be required. This further slows down the driving speed of the NOR gate,
This is also a major drawback when it comes to speeding up. Furthermore, especially in large-capacity memories, the pitch between adjacent word lines becomes short, making it extremely difficult to arrange a large NOR gate for each word line.

Therefore, a decoder circuit as shown in FIG. 2 (al) is used. This decoder circuit has one NOR gate assigned to multiple word lines (four in the figure). The line selection address and the upper bits of the edge are input to the NOR gate, and the NOR gate is connected so that the output is commonly given to one input terminal of the AMP (ANDNO gate amplifier circuit) installed for each word line. establish.

The lower pin of address Ax (or the signal obtained by decoding it) is supplied to the other input terminal of each AMP. This is used for word line selection. In this way, the number of N01% gates and the area occupied by them can be reduced, making it possible to cope with higher integration and smaller volumes. A similar decoder can also be applied to the digit line selection (address Ay) decoder YD. A decoder with such a configuration is hereinafter referred to as a multi-output decoder.

Figure 2 Q) l and (cl are the circuit diagrams of one memory cell M and the clamp circuit jliIIC, respectively. W is the word line, D is the digit line, and P is the precharge signal D
D indicates the power supply voltage, respectively.

Furthermore, FIG. 3(a) shows NO in the block diagram of FIG. 2(a).
The circuit diagram of the R gate, FIG. 3(t)l, is a circuit diagram corresponding to the AMP. AO, A, 1. ...An is the address signal Ax o g Ax 1+ "n" or Ay
o , Ay 1 , −= , corresponds to Ayn, and A
o, Al, ... An are Ax of the address signal
o, A-xl, -Axn or Ayo, AY
l, corresponds to Ayn.

To simplify the explanation below and make it easier to understand, one NOR gate is provided for four word lines.
Take N0R4 output decoder as an example.

In this case, PDo to PD are word line selection signals generated by decoding the lower two bits of the address.

As patterns become finer, the capacitance between adjacent wires and the capacitance between vertically crossing wires increases as a percentage of the total capacitance of the wires, so the capacitance between word lines and digit lines increases, and the capacitance between word lines and digit lines increases. Noise is generated from other word lines and digit lines, and the circuit (main circuit and sense amplifier) often malfunctions. To suppress this noise, it is necessary to clamp the unselected decoder outputs to a fixed (eg, ground) potential with low impedance during operation. However, in the conventional clamp circuit (2nd o (c)), as the memory cell becomes smaller and the wiring pitch for forming word lines and digit lines becomes smaller, it becomes difficult to form this between the pitches. Also, in order to lower the impedance, if the transistor Q in Figure 2 (C) is increased,
Since the 7 lip-flop circuit is inverted when selected, the rise of the output line is delayed.

In other words, there is a disadvantage that the operating speed is correspondingly slow.

(9th Object of the Invention) The present invention provides a decoder circuit which fixes the decoder output at low impedance when not selected, clamps it to the ground potential, for example, and can operate at high speed when 1 is selected.

(Structure of the Invention) The present invention provides a first method for commonly selecting a plurality of word lines (or digit lines) in a semiconductor memory device in which word lines and digit lines are arranged in a matrix and memory cells are provided at each matrix intersection. means for selecting one of the word lines (or digit lines) selected by the means of brother-in-law 1; The invention is characterized by comprising means for holding the word line (or digit line) at a fixed potential when the word line (or digit line) is in a non-selected state.

Further, the holding means is formed between adjacent word lines (or between digit lines).

Furthermore, the holding means can be realized by at least one MOS transistor, and is integrated on a memory chip in a very small area regardless of the distance between word lines (between digit lines).

(Description of Embodiment) FIG. 4 is a circuit diagram of a multi-output decoder showing an embodiment of the present invention.

Here, an l'J OB circuit and a NAND circuit are used. NAND circuit inputs N0I (, circuit and reverse phase address signal (for example, NOIv) input cuff 5% Ao e AI w
4 pAs e A4 to f and NAND input is friend,
An example of this is shown in FIG. 5.

Since the output CLP of the NAND circuit is precharged by the precharge signal P, it holds a high potential before the decoder operation. T again. -Ta11 are clamp transistors provided for each word line. The clamp circuit according to this embodiment is composed of a NAND circuit and a clamp transistor, and since only one NAND circuit is required per four outputs of one decoder, it does not occupy a large area. Further, when the decoder output is made to have a low impedance, the clamp transistors TIO to T13 may be made thicker, and even in that case, the conventional clamp circuit shown in C in FIG. The NAND circuit can operate simultaneously with the NOR circuit, and no extra drive signal is required. Moreover, when the NOR circuit is selected, that is, when the logic I11'' is output, the clamp transistors 11□.~T+3 are all turned off, so the four A
Among the MPs, only one of P Do-P D3 selected by one signal becomes the output 111+1 and the potential rises, but since the others are at low potential, the decoder output is clamped to a low potential through the amplification circuit AMP. Ru. Therefore, the AMP decoder output in which NOR is selected and the amplifier circuit drive signal is not selected is also connected to the clamp transistor T.
Even though I o '''-T + B is off, the potential is stable.

If the NOR circuit is still not selected, the output CLP of the NAND circuit is at a high potential (logic 11111), so the decoder output is always at a low potential (ground (earth) potential in the example).
be clamped to.

As described above, according to this embodiment, each output terminal of the multi-output decoder is connected to the drain of a transistor whose source is connected to a constant potential, and an address signal having a phase opposite to that of the NOR circuit of the decoder is input. The former is a NAND circuit that outputs the ON potential of the transistor and operates simultaneously with the NOR circuit.
By inputting the output of the circuit to the gate of the transistor, a decoder output circuit is realized in which the decoder output can be clamped to the ground potential with low resistance when not selected, and which can operate at high speed when selected. be able to.

FIGS. 6 and 7(a) and 7(b) are circuit diagrams showing other embodiments of the present invention. In FIG. 6, the NOR circuits A, MP, and TI to TIS may be the same as those in FIG.

INV is an inverting circuit that operates in response to a pulse S, and is provided in place of the N A N J) circuit in FIG. 4. However, it is assumed that the output CLP is at a high potential before the pulse S rises. S is the above-mentioned inverting circuit 'f: PDo-PD with the operating pulse.

It is a pulse that rises at approximately the same time as one of them is selected and rises. Figure 6(a).

[Yes]) are two examples of the above-mentioned inverting circuit iNV. Figure 6(a) shows an example using 7 flip-flops, but compared to a conventional clamp circuit, the flip-flop has 4 outputs (
Since only one is required per four word lines, the area may be small. Also, when making the decoder output a low impedance, it is sufficient to increase the size of the transistors Tl0-T18.
Even so, sufficient definition can be achieved between each word line. The inversion circuit drive signal S is still the amplifier drive signal PDo-PD3.
Synchronized with T10-TlB when NOR is selected
are turned off all at once, so no speed reduction occurs. In this state, one of the PDo-PDs is selected and the output of that AMP rises, but the other AMPs become low potential outputs, so the decoder The output is clamped to a low potential.

Therefore, the decoder output when NOR is selected and the drive pulse is not selected is also maintained at a stable potential even though transistors T1o to 'I'1m are off.

In this way, in this embodiment, the individual output terminals of the multi-output decoder are connected to each drain of a transistor whose source is connected to a fixed potential, the output of the NOR circuit is input, and the on-potential of the transistor is set before operation. By inputting the output of an inverting circuit that operates in the same phase as the amplifier circuit to the gate of the transistor, the decoder output when not selected is clamped to a fixed potential with low resistance, and high-speed operation is possible when selected. A decoder output circuit can be realized.

As described above, according to the present invention, the clamp circuit for each word line can be made very small and does not impede high-speed operation in any way, so it is very effective as a decoder for large-capacity memories. Although a word line decoder circuit is illustrated in this embodiment, it is obvious that a similar circuit can be used as a digit line decoder circuit. In addition, each clamp transistor has one transistor per word.
Since only one word line is required, it can be formed so as to fit sufficiently between adjacent word lines. Furthermore, since the spacing between word lines/digit lines can be made smaller than in the past, a memory with a larger capacity can be provided.

Furthermore, the present invention is not limited to N-channel l-transistor memories, but can also be applied to transistor memories (CMO81) or other memories (for example, 6-transistor memories). Furthermore, it does not have to be an IN0R4 output decoder, but may be an IN0Rs output decoder, an IN0R16 output decoder, or the like.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional one-transistor memory, Figure 2 (a) is a conventional decoder circuit diagram, and Figure 2 (b) is a block diagram of a conventional one-transistor memory.
A circuit diagram of a transistor memory cell, FIG. 2(c) is a conventional clamp circuit diagram, FIG. 3(a) is a NOR circuit diagram,
Figure (b) is an AMP circuit diagram, Figure 4 is a decoder circuit diagram of one embodiment of the present invention, Figure 5 is a NAND circuit diagram, and Figure 6 is a decoder circuit diagram showing another embodiment of the present invention. Figure 7(a)
, (b) are inversion circuit diagrams, respectively. XD: Row decoder, YD: Column decoder, M: Memory cell, C: Clamp circuit, SA: Digit sense amplifier ,
W" t...word line which is the row decoder output,
Yn... Column decoder output, Dn...
Digit line, Ilo...Read, write bus, Axng 40...Row address, AY□
, A, Column address, NOR... NOR circuit, 'AMP... Amplification circuit, PDo-FD,...
...Amplifier circuit drive signal, P...Precharge signal, NAND...NAND circuit, T...
, -T, ... Clamp transistor, VDD
...Power supply voltage, INV...Inversion circuit 5
・;1,・. Representative: Yo Uchihara, patent attorney. ＼ No. IUfE Chi 2 diagram (a) $ 2 m (b) Chi 2 Flash C (:) Bud 3 diagram (a) Rod 3 Figure Cb) Potato 4 Figure VDI) Sheep 5 Figure pD Yuka Z Figure 7 ( a, □) Chrysalis Fig. 7 (-b)

Claims (1)

[Claims] In a semiconductor memory device having decoder means for commonly selecting a plurality of word lines (or digit lines), when the plurality of words I9 (or digit lines) are in a non-selected state, a circuit is provided that clamps the plurality of words I9 (or digit lines) to a fixed potential. A semiconductor memory device characterized by realizing at least one transistor.