JPH0421956B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device that can improve access time and reduce power consumption.

[Prior art]

FIG. 1 is a block diagram showing a conventional semiconductor memory device. In the figure, 1 is a memory cell arranged in a matrix, the detailed circuit of which is shown in FIG. 2, 2a and 2b are a pair of complementary bit lines, and 3 is a memory cell on the same row when selected A word line for activating cell 1, 4 a row decoder for decoding row address information, 5 a row address signal line, and 6a and 6b the bit lines 2a and 2.
Bit line loads are respectively connected to b, and 7 is a power supply terminal.

Note that in the memory cell 1 shown in FIG.
Reference numerals a and 8b are load elements constituted by MOS transistors, resistors, etc., 9a and 9b are inverter transistors, 10a and 10b are access transistors, and 11a and 11b are store nodes of the memory cell 1.

Next, the operation of the semiconductor memory device having the above configuration will be described, as an example, in the case where store nodes 11b and 11b are written to "H" level and "L" level, respectively.
First, in the case of reading, the address information of the cell to be read is input to the address signal line 5.
Then, when this word line 3 is activated, it becomes “L”
Access transistor 1 storing the level
0b becomes conductive. Therefore, a current flows from the power supply terminal 7 through the path of the bit line load 6b, the bit line 2b, the access transistor 10b, and the inverter transistor 9b, allowing reading.

In a semiconductor memory device with this configuration, all memory cells on the same row are activated, so current flows from the power supply to the memory cells in all columns, and when configuring a large capacity static RAM with many columns, current consumption is reduced. growing. Therefore, in order to reduce current consumption, a semiconductor memory device as shown in FIG. 3 has been proposed. In this case, the row decoder 4 is arranged in the center of the memory cell plane, the word line is divided into the left word line 3a and the right word line 3b, and only the word line of the selected memory cell group of the left and right memory cell groups is used. By activating
Of all the columns, only half of the columns generate current paths. Note that 12a and 12b are AND gates that select the left word line 3a or the right word line 3b, respectively, and 13a and 13b are gate signal lines that open the AND gates 12a and 12b, respectively.

Next, FIG. 4 is a layout diagram showing a conventional semiconductor memory device constructed based on the idea of FIG. 3.
In this case, the row decoders 4a and 4b are arranged in a plurality of columns, and the word lines 3a to 3d are divided by a multiple thereof, thereby reducing the number of DC current paths.

However, conventional semiconductor memory devices require a large number of row decoders. For this reason,
This method had drawbacks such as an increase in chip area, which impairs speed performance and yield.

[Summary of the invention]

Therefore, an object of the present invention is to provide a high-speed, low power consumption, and large-capacity semiconductor memory device.

This invention includes N memory cell groups in which a memory cell array in which memory cells are arranged in a matrix is divided in the column direction, and N memory cells provided corresponding to each of the N memory cell groups. A memory cell group selection line that selects a specific one of the cell groups, a row decoder that decodes the row address information of the memory cell group to be accessed, and a memory cell group that is connected to the output terminal of the row decoder and that connects N memory cells. It consists of a preword line arranged across the groups, a word line provided corresponding to each of the N memory cell groups, and activated as a memory cell group selection line, and a memory cell group selection line. The configuration is such that it is connected to a memory cell group selector output, and the memory cell group selector output is also connected to a column decoder, and will be described in detail below using an embodiment.

[Embodiments of the invention]

FIG. 5 is a block diagram showing an embodiment of the semiconductor memory device according to the present invention, and shows, as an example, a case where three memory cell groups 1a, 1b and 1c are arranged in the column direction. In the same figure,
14a, 14b and 14c are memory cell group selection lines 15 for selecting the memory cell groups 1a to 1c;
are front word lines 16a, 16b and 16c arranged in parallel in the same direction as word lines 3a to 3c.
are AND gates whose input terminals are connected to the prefix word 15 and the memory cell group selection lines 14a to 14c, respectively, and whose output terminals are connected to the word lines 3a to 3c, respectively. Further, 17a to 17c are memory cell group selectors to which the upper column address signal of the column address information is input, and the memory cell groups 1a, 1
In order to select a specific memory cell group from b and 1c, a selector output is output, and a memory cell group selection signal line corresponding to the selected memory cell group is activated. The memory cell group selectors 17a to 17c also function as predecoding means for column selection.
Its outputs are coupled to column decoders 18a-18c, each receiving a lower column address signal of the column address information and decoding the column address information of the memory cell to be accessed in the corresponding memory cell group.

Note that in order to reduce the memory cell area, the word lines 3a to 3c are formed of a polysilicon layer in the same layer as the gates of the MOS transistors 10a and 10b, and the pre-word lines 15 are these word lines 3a to 3c. It is formed of a polysilicon layer other than this polysilicon layer or a metal wiring layer of aluminum, molybdenum, molybdenum silicide, or the like.

Next, the operation of the semiconductor memory device with the above configuration will be explained. First, for example, memory cell group 1
When selecting a memory cell in a, the row address information of the memory cell group 1a to be accessed is decoded by the row decoder 4, and one of the front word lines 15 is activated. Then, when a selection signal is applied to the memory cell group selection line 14a, the AND gate 16a opens and the word line 3a is activated. Therefore, the column current flowing from the power source (not shown) to the memory cell group 1a through the bit line (not shown) flows only in the columns in the selected memory cell group 1a.
Furthermore, since the memory cell group selectors 17a to 17c function as predecoders for column selection, the input signals of each column decoder 18a, 18b, and 18c are a column address signal indicating a column within the memory cell group and a corresponding memory cell group. Since the selector output is the selector output of the selector, each column decoder 18a to 18c can be simplified, and the layout area can be significantly reduced compared to the case where a normal column decoder is configured.Moreover, each column decoder 18a -18c, the corresponding memory cell group selectors 17a-1
Since the selector output from 7c is input,
Since only the bit lines 2a and 2b to which the memory cells to be selected are connected in the memory cell group in which the memory cells to be selected exist are selected, the stray capacitance on the selected bit lines does not increase and the selected bit lines' It also has the effect that the time delay required for charging and discharging is suppressed, thereby suppressing the delay in the speed of reading information from the memory cell to be selected and the speed of writing information to the memory cell to be selected.

Note that although the selection of the memory cell 1 in the memory cell group 1a has been described above, it goes without saying that the same can be done for the other memory cell groups 1b and 1c. Furthermore, although we have explained the case where the memory cell group is divided into three, N (N≧2)
Of course, the same thing can be done even if it is divided into two parts. Furthermore, if only the front word line 15 is made of a low-resistance material, even if the resistance of the word line is somewhat high, the length is short, so the capacitance is small, and memory cells can be accessed at high speed. . In addition, the AND gates 16a to 16c have two input terminals and one output terminal, so the circuit configuration is simplified.
The increase in chip area is negligible. Furthermore, it goes without saying that the row decoder 4 may be placed at the center of the chip or at the edge of the chip. Furthermore, although the row decoders are arranged at the ends of the chips in the above embodiments, they may of course be arranged at the center of the chips.

〔Effect of the invention〕

As described in detail above, according to the semiconductor memory device according to the present invention, row selection is performed hierarchically such that memory cell selection is performed in two stages: front word line and word line. Since the number of columns with DC current paths can be reduced, it is possible to construct a high-speed, low-power, large-capacity semiconductor memory device.

In addition, since the memory cell group selector functions as a predecoder for column selection, the column decoder can be simplified and the layout area can be significantly reduced. Since it receives the selector output of the group selector and the lower column address signal of the column address information, only the bit line to which the memory cell to be selected is connected in the memory cell group in which the memory cell to be selected exists is selected. This also has the effect of suppressing delays in the speed of reading information from the memory cell to be selected and the speed of writing information to the memory cell to be selected.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional semiconductor memory device, FIG. 2 is a detailed circuit diagram of the memory cell in FIG. 1, FIG. 3 is a block diagram showing another conventional semiconductor memory device, and FIG. 4 is a block diagram showing a conventional semiconductor memory device. FIG. 5 is a layout diagram showing another conventional semiconductor memory device, and FIG. 5 is a block diagram showing an embodiment of the semiconductor memory device according to the present invention. 1...Memory cell, 1a and 1b...Memory cell group, 2a and 2b...Bit line, 3...Word line, 4...Row decoder, 5...Row address signal line, 6a and 6b...Bit line Load, 7...
Power supply terminal, 8...Load element, 9...Inverter transistor, 10...Access transistor, 1
1...Store node, 12a and 12b...AND gate, 13a and 13b...gate signal line, 14a to 14c...memory cell selection line, 15
. . . Front word line, 16a to 16c . . . AND gate, 17a to 17c . . . Memory cell group selector, 18a to 18c . . . Column decoder. Note that the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. A memory cell array in which memory cells are arranged in a matrix is divided and arranged in the column direction, and a high-order column address signal of the column address information is inputted to N memory cell groups, and a memory cell group selector for selecting a specific memory cell group among the N memory cell groups; and a memory cell group selector provided corresponding to each of the N memory cell groups, and configured to receive a selector output of the memory cell group selector. a memory cell group selection line provided corresponding to each of the N memory cell groups, each receiving a selector output of a corresponding memory cell group selector, and a lower column address signal of the column address information; a plurality of column decoders that decode the column address information of the memory cell to be accessed in the corresponding memory cell group; a row decoder that decodes the row address information of the memory cell to be accessed; connected and said N
a prefix word line arranged across the N memory cell groups; and a prefix word line provided corresponding to each of the N memory cell groups, which controls the activation state of the memory cell group selection line and the selection of the prefix word line. A semiconductor memory device comprising: a signal; and a divided word line activated based on a signal.