JPH0758589B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a dynamic RA.
It is related to the reduction of the power consumption of M.

[Conventional technology]

As a semiconductor memory device with a self-refresh function,
Virtual static RAM (hereinafter referred to as "VSRAM") is known. This VSRAM is a dynamic RAM
Substantially static with memory cells used for
It realizes RAM. That is, each memory cell is formed using one MOSFET and one capacitor, and refresh-related operations for this memory cell are performed on-chip. Therefore, the user does not need to prepare a circuit for refreshing, and VSRAM
Is a memory that does not burden the user.

FIG. 2 is a block diagram showing the entire structure of such a VSRAM, and FIG. 3 is a circuit diagram around a conventional memory cell included therein. This device is K. Nogami et.al., "1-
Mbit Virtually Static RAM ", 1EEE J. Solid−State Cir
cuits, vol, SC21 No. 5, Oct, 1986.

In the figure, the VSRAM of FIG. 2 includes a memory array 1 including a two-dimensional array of memory cells M _ij (i = 1 to m, j = 1 to n) shown in FIG. When the memory array 1 is normally accessed (that is, externally accessed for reading and writing data), the row address RA and the column address CA are set at the timings shown in FIG. 4A.
Are externally supplied, and these addresses RA and CA are respectively buffered in the row address buffer 7 and the column address buffer 12. Of these, the row address RA output from the row address buffer 7 is supplied to the address multiplexor 8. . When the refresh operation is not performed, the arbiter circuit 11 switches the address multiplexer 8 to the row address buffer 7 side in response to the normal access request ACSREQ.
RA is applied to row decoder 3. The row decoder 3 decodes the row address RA, selects one row in the memory array 1, and selects one of the word lines WL _i (i = 1 to m) shown in FIG. 3 for the selected row. Are activated as shown in FIG. 4 (b).

At the time of data reading, data is read from the memory cells (for example, M _{21 to} M _2n ) belonging to the row thus selected, and all the sense amplifiers SA _j (j = 1 to 1) included in the sense amplifier group 2 are read. n) is activated so that the detection and amplification of these data can be performed by the bit lines BL _ja , L.
performed on _jb (j = 1 to n). This operation is shown as data D in FIG. 4 (d).

On the other hand, the column address CA buffered in the column address buffer 12 is passed through the timing generator 6 to the column decoder 4
Given to. The column decoder 4 decodes this column address CA to select a specific column in the memory array 1,
Of the I / O gate transistors Q _ja and Q _jb (j = 1 to n) in the figure, the transistor for the selected column is turned on.

The data for the selected column is transferred to the buffer register 5 in FIG. 2 via the I / O line 21 and the line 22.
After being held by the input terminal, it is output to the input / output pin via the input / output buffer 14 at the timing of FIG. 4 (e). The buffer register 5 is provided to transfer the data of the memory cell to the buffer register 5 to release the memory cell from the normal access at an early stage, thereby extending the executable period of refresh.

On the other hand, the refresh of the VSRAM is carried out by utilizing the period in which the word line WL _i , the memory cell M _ij , and the sense amplifier group 2 are not used by normal access. Examples of such periods include the period of waiting for the address queue during normal access and the period of decoding addresses.
Besides, there is a period during which the output circuit is driven.

Specifically, first, the refresh timer 10 clocks a time corresponding to the data holdable time in the memory cell M _ij, and at the time when refresh is required, the refresh timer 10 outputs a refresh request signal REFREQ to the arbiter circuit 11. To be done. In response to the output from the refresh timer 10, the refresh address counter 9 outputs the address to be refreshed to the address multiplexer 8.

The arbiter circuit 11 is controlled by the control circuit 13 and the timing generator 6. When the memory cell is released from the normal access, the arbiter circuit 11 switches the address multiplexer 8 and supplies the refresh address RFA output from the refresh address counter 9 to the row decoder 3.
As a result, the designated word line is activated as shown in FIG. 4 (c), and the refresh of the memory cell belonging to the designated row address is started. Bit line BL _niv in this operation, the activation state of BL _jb are indicated by signal RF in FIG. 4 (d).

If the memory cell M _ij is being used for normal access at the time the refresh request signal REFREQ is applied, the memory cell M _ij is brought into a refresh standby state until the use is completed. Then, the refresh operation is performed after the memory cell M _ij is released from the normal access.

On the contrary, when a normal access request is issued during the refresh operation, the normal access operation is executed after the memory cell is released from the refresh operation.

[Problems to be solved by the invention]

Since the conventional VSRAM is configured as described above, the selected memory cell (for example,
All of the memory cells (M _{21 to} M _2n ) belonging to the same row as M ₂₂ ) are bit line BL by the rise of the potential of word line WL _2.
connected to _ja , BL _jb (j = 1 to n). Then, all the sense amplifiers SA _j (j = 1 to n) are also activated.

However, it is only the selected memory cell M ₂₂ that actually reads data, and the other memory cells M _2j (j ≠ 2) and bit lines BL _ja , BL _jb (j ≠) belonging to the same row.
2) and the operation of the sense amplifier SA _j (j ≠ 2) is not necessary. Nevertheless, in the conventional semiconductor memory device, there is a problem that the power consumption is large because the unnecessary portion is also activated to use the electric power for charging and discharging the bit line.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of reducing power consumption during normal access.

[Means for solving problems]

A semiconductor memory device according to the present invention is a memory array in which memory cells each including one MOSFET and one capacitor are arranged in a matrix including rows and columns, and each memory cell is divided into a plurality of groups each having a plurality of columns of memory cells. A plurality of bit line pairs respectively arranged in each column of the memory array and connected to a plurality of memory cells in the arranged column, a plurality of sense amplifiers connected to the plurality of bit line pairs, the memory array A plurality of sub-word lines, each sub-word line being arranged in each row in each group, connected to a plurality of memory cells in the arranged row, extending in the row direction in the memory array over the plurality of groups, Corresponding to any one of the plurality of sub-word lines arranged in each of the plurality of main word lines, Corresponding to the main word line selected by the row decoder, which is connected between each main word line and the sub word line corresponding to the main word line. A plurality of sub-word line selecting means for selecting any one of the sub-word lines in accordance with an address signal, a common wiring for a sense amplifier that is provided in common to the plurality of sense amplifiers, and transmits a predetermined potential, A sense amplifier connected to a bit line pair connected between a sense amplifier and the sense amplifier common line and connected to a memory cell connected to a selected sub-word line, and the sense amplifier traffic line. It is configured to include switching means for connecting in accordance with an address signal.

[Action]

According to the present invention, a sense amplifier and a sense amplifier connected to a bit line pair connected between a plurality of sense amplifiers and a common wiring for sense amplifiers and connected to a memory cell connected to a selected sub-word line. By providing the switching means for connecting to the common wiring for use in accordance with the address signal, a predetermined potential is transmitted to the sense amplifier corresponding to the selected sub-word line to selectively activate the sense amplifier.

Therefore, of the plurality of memory cells, the plurality of bit line pairs, and the plurality of sense amplifiers, a part or all of the unnecessary portion for normal access is not operated, thereby reducing power consumption.

〔Example〕

An embodiment in which the present invention is applied to VSRAM will be described below. The overall configuration of this embodiment is similar to that of the device shown in FIG. 2, and the difference from the conventional device is the configuration of the memory array 1 and its peripherals. Therefore, in the following, the first example showing the memory array 1 and its peripheral circuits in this embodiment is shown.
The description will proceed centering on the figure.

First, in this embodiment, two types of lard lines are provided as word lines in the memory array 1. One of them is the main word line WLM _i (i
= 1 to m). The other one is a sub-cell provided for each two memory cells (for example, M ₁₁ and M ₁₂ , M ₁₃ and M ₁₄ ) connected to the memory cell M _ij side and adjoining each other along the row extending direction. Word line WLS _if (i = 1 to m, f = 1 to k; k = n /
2). Then, each sub word line WLS _if and main word line WL
_{Between i} and the first switching circuit SWB _if (i = 1 to 1
m, f = 1 to k) are respectively inserted.

Also, between these sense amplifiers SA _j and the sense amplifier activation signal line 25 which is given from the timing generator 6 of FIG. 2 and extends to the sense amplifiers SA _i (j = 1 to n) of FIG. Is the second switching circuit SWA _j (j
= 1 to n) are inserted.

Since the memory cell array 1 includes many rows and columns,
As shown in the figure, a plurality of these first and second switching circuits SWB _if and SWA _j exist, and these are formed using, for example, MOSFETs. Then, these switching signals are given from another decoder 4 via a switching signal line (not shown).
In the following, the bit line pair BL is arranged along the row extending direction.
_en , consider a combination of two BL _jb pairs, and collectively refer to the memory cells, sense amplifiers, etc. belonging to each combination part,
These are called "fth group" (f = 1,2, ..., k) in the order closer to the row decoder 3.

Next, the operation of this embodiment will be described. First, at the time of normal access, the row address RA for normal access is given to the row decoder 3 by the judgment of the arbiter circuit 11 in FIG. In parallel with this, a signal corresponding to the column address CA is given to the column decoder 4.

The column decoder 4 identifies the group including the column to which the memory cell to be accessed belongs, based on the column address CA. For example, when memory cell M _{13 in} FIG. 1 is accessed, the second group including the column to which this memory cell M ₁₃ belongs is specified.

Then, all the first and second switching circuits SWB _{12 to} SWB _m2 ; SWA ₃ , SWA ₄ included in the second group are turned on, and the remaining switching circuits SWA _j (j ≠ 3,4), SWB _ij. (J ≠
Turn off all 2).

In this way, only the portions related to the column to which the memory cell M ₁₃ to be accessed belongs are electrically connected to each other and activated, and then the row decoder 3 sets the main word line WL.
Drive M ₁ . In this process, the column address CA is input at the same time as the row address RA, so the main word line
The waiting time on the side of the row decoder 3 until the start of driving WLM ₁ is substantially zero.

First switching circuits SWB _{12 to} SWB _m2 included in the second group
Are all on, the potential change of the main word line WLM ₁ driven by the row decoder 3 is
₁₂ to open the gates of the memory cells M ₁₃ , M ₁₄ . The data stored in these memory cells M ₁₃ and M ₁₄ are extracted as the potential difference between the bit line pairs BL _3a and BL _3b ; BL _4a and BL _4b . Further, when the sense amplifier activation signal is applied to the sense amplifier activation signal line 25, these are detected and amplified by the sense amplifiers SA ₃ and SA ₄ , respectively.

At this time, since the switching circuits SWA ₃ and SWA ₄ are turned on and the remaining switching circuits SWA _j (j ≠ 3, 4) are all turned off, only the two sense amplifiers SA ₃ and SA ₄ receive the sense amplifier activation signal. Connected to line 25. As a result, the transmission speed of the sense amplifier activation signal can be improved, and the sense amplifiers SA ₃ and SA ₄ can be activated in an early stage to perform the detection / amplification operation at high speed.

After that, the I / O gate signal from the column decoder 4 causes I / O
The gate transistors Q _3a and Q _3b turn on, and the sense amplifier SA ₃
2 is transferred to the buffer register 5 of FIG. 2 via the I / O line 21 and the line 22. After that, the potential of the main word line WLM ₁ (hence the potential of the sub word line WLS ₁₂ ) falls, and the first and second switching circuits SWB _{12 to} SWB
B _m2 ; SWA ₃ and SWA ₄ are turned off. Then, the bit line BL _3a ,
BL _3b ; BL _4a and BL _4b are precharged, and all memory cells M _ij are released from normal access.

Next, the operation at the time of refresh will be described. As an example, consider the case where the memory cells M _{11 to} M _1n connected to the main word line WLM ₁ are refreshed. In this case, the arbiter circuit 11 switches the address multiplexer 8 based on the refresh request REFREQ, so that the refresh address RFA is given to the row decoder 3.

On the other hand, the arbiter circuit 11 gives a signal for refreshing to the column decoder 4 via the timing generator 6. Based on this, the column decoder 4 uses the first and second switching circuits SWB _if and SWA _j (i = 1 to m, f = 1 to k, j =
All of 1 to n) are turned on.

Therefore, when the potential of the main word line WLM ₁ rises, all the potentials of the sub-word lines WLS _if (f = 1 to k) in the first row also rise, and the memory cells M _{11 to} M _{1n in} the first row also rise. The data stored in each of the bit lines BL _ja , BL _jb (j = 1 to
n). Then, when the sense amplifier activation signal is applied to the sense amplifier activation signal line 25, each of the sense amplifiers SA _{1 to} SA _n starts the detection / amplification operation. As a result, the data on the bit lines BL _ja , BL _jb (j = 1 to n) is amplified, and the data is taken into the memory cells M _{11 to} M _1n to perform refresh.

After that, the main word line WLM ₁ and the sub word line WLS _1f (f =
1-k) fall, the first and second switching circuit SW
All of B _if , SWA _j (i = 1 to m, f = 1 to k, j = 1 to n) are turned off, and bit lines BL _ja , BL _jb (j = 1 to n) are precharged. . As a result, the memory cell 1 is released from the refresh operation.

That is, all the first and second switching circuits are turned on at the time of refresh, and at this time, the refresh operation similar to that of the conventional device is performed. It is not necessary to turn on the first switching circuits SWB _if (i ≠ 1, f = 1 to k) for rows other than the row to be refreshed, but the potentials of the main word lines WLM _{2 to} WLM _m for them are Since it does not rise, as described above, the first switching circuit SWB _jf (i = 1 to m, f = 1
There is no problem even if all of ~ k) are turned on.

Although the present invention is applied to VSRAM in the above embodiment,
The present invention is also applicable to PSRAM (pseudo-static RAM) that can be used like static RAM while using a dynamic RAM memory cell consisting of one transistor and one capacitor. This PSR
For AM itself, see H. Kawamoto et.al., “A 288K C
MOS Pseudostatic RAM "IEEEE J.Solid-State Circuits
vol.SC-19, No. 5, Oct, 1984.

The reason why the present invention is applicable to all such self-refresh type semiconductor memory devices is that the distinction between the normal access and the refresh operation can be known at a relatively early timing.

Further, in the above embodiment, the sub word line and the first switching circuit are provided for every two memory cells adjacent to each other along the row extending direction, but it is not always necessary to use two memory cells as a unit. Instead, an arbitrary number of memory cells may be used as a unit. When the first switching circuit is provided between the main word line WLM _i and each memory cell M _ij , it is not necessary to provide the sub word line, and the first switching circuit is provided between the main word line and each memory cell. It may be inserted directly.

〔The invention's effect〕

As described above, according to the present invention, a bit line pair connected between a plurality of sense amplifiers and a common wiring for sense amplifiers and a memory cell connected to a selected sub word line is connected. By providing switching means for connecting the sense amplifier and the common wiring for the sense amplifier according to the address signal, a predetermined potential is transmitted to the sense amplifier corresponding to the selected sub-word line to selectively select the sense amplifier. Since it is activated, unnecessary parts are not activated and power consumption can be reduced.

In addition, by connecting the common wiring for sense amplifiers commonly provided for multiple sense amplifiers only to the sense amplifiers corresponding to the selected sub-word line, the speed of transmission of a predetermined potential is improved and the sense amplifiers are quickly activated. The detection / amplification operation can be performed at high speed by setting the active state.

[Brief description of drawings]

FIG. 1 is a partial circuit diagram showing a memory cell and a part of its peripheral circuit in one embodiment of the present invention, FIG. 2 is a block diagram showing the entire structure of VSRAM, and FIG. 3 is a memory cell in a conventional VSRAM. A partial circuit diagram showing a part of the peripheral circuit,
FIG. 4 is a timing chart showing an operation example of VSRAM. In the figure, 1 is a memory cell, 2 is a sense amplifier group, 3
Is a row decoder, 4 is a column decoder, M _ij is a memory cell, SA _j
Is a sense amplifier, WLM _i is a main word line, WLS _if is a sub word line, SWB _if is a first switching circuit, and SWA _j is a second switching circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] 1. A memory array in which memory cells each including one MOSFET and one capacitor are arranged in a matrix of rows and columns, and each memory cell is divided into a plurality of groups each having a plurality of columns of memory cells. Placed in each column in
A plurality of bit line pairs connected to the plurality of memory cells in the arranged columns, a plurality of sense amplifiers connected to the plurality of bit line pairs, and arranged and arranged in each row in each group of the memory array. A plurality of sub-word lines connected to a plurality of memory cells in a row, any one of a plurality of sub-word lines extending in the row direction in the memory array over the plurality of groups and arranged in each group. Corresponding to each main word line and each main word line, a plurality of main word lines arranged corresponding to each of the main word lines, a row decoder selecting one of the above-mentioned main word lines according to an address signal. A plurality of sub word lines, each of which is connected to the sub word line and selects one of the sub word lines corresponding to the main word line selected by the row decoder in accordance with the address signal. Sub word line selection means, a common wiring for sense amplifier that is provided in common to the plurality of sense amplifiers and transmits a predetermined potential, is connected between the plurality of sense amplifiers and the common wiring for sense amplifier, and is selected. A semiconductor memory device comprising switching means for connecting a sense amplifier connected to a bit line pair connected to a memory cell connected to a sub word line and the sense amplifier common line in response to an address signal. 2. A sense amplifier common wire is arranged in parallel with a main word line, and a switching means is provided corresponding to each sense amplifier, and between the corresponding sense amplifier and the sense amplifier common wire. 2. The semiconductor memory device according to claim 1, further comprising a plurality of switches connected to each other and selectively conducting in response to an address signal. 3. The sub word line corresponding to the main word line selected by the row decoder is selected in all the groups at the time of refresh, according to claim 1 or 2. Semiconductor memory device.