JP2720158B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a main / sub bit line structure, for example, for reducing the power consumption of a DRAM (Dynamic Random Access Memory). It is about technology that is effective to apply.

(Prior art)

In the DRAM, the storage capacity and the degree of integration have been increased, so that the storage capacity constituting the memory cell has been reduced, and the number of memory cells coupled to the bit line has been increased, thereby increasing the parasitic capacity of the bit line. , The amount of signals read to the bit lines tends to be smaller.

As a countermeasure, mat division or bit line division is performed to reduce the driving load of the sense amplifier.
In particular, in such a case, there is a main / sub bit line method as a method for preventing peripheral circuits such as a column switch circuit and a column address decoder from increasing according to the number of divisions of the bit lines.

In the main / sub bit line system, a plurality of sub bit lines each having a memory cell coupled thereto are commonly connected to a main bit line via a switch element, and these switch elements are selected by a memory cell selected based on a word line selection signal. Are controlled so as to make the sub-bit line including the bit line conductive to the main bit line.

As an example of a document describing the main / sub bit line method, see the IEICE CDM87-1 (April 2, 1987).
1 date).

[Problems to be solved by the invention]

However, in the conventional main / sub bit line type DRAM, the above-mentioned switch element has a sub bit line including a memory cell selected based on a word line selection signal and a sub bit line sharing a word line with the main bit line. , All the main bit lines are individually made conductive to the sub-bit lines, and the main bit lines that are not actually used for reading data also load the sense amplifier connected to the selected sub-bit line. Will be constituted. Moreover,
Lass for refreshing memory cells in word line units
Even in a refresh operation such as only refresh, the main bit line constitutes a load for each sense amplifier. As described above, when the main bit line becomes an undesired load for the sense amplifier, parasitic capacitance exists in the main bit line, and particularly in the main / sub bit line method, the main bit line is relatively long. When a large number of main bit lines serving as a desired load are charged and discharged by individual sense amplifiers, there is a problem that power consumption increases.

It is an object of the present invention to provide a main / sub bit line type semiconductor memory device capable of reducing power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of sets of a plurality of sub-bit lines each having a memory cell coupled thereto are commonly connected to a main bit line via a selection switch circuit, and the main bit line is selectively connected to a common data by a column switch circuit. The selection switch circuit included in the semiconductor memory device that enables conduction to a line has a circuit configuration for selectively conducting a desired sub-bit line of a desired main bit line to the main bit line. For example, the selection switch circuit includes a first switch circuit for commonly selecting a desired sub-bit line in each main bit line.
A switch element and a second switch element which is connected in series to the first switch element in each main bit line and selectively controls conduction of a sub-bit line selected by the first switch element to a desired main bit line. It is possible,
In this case, the first switch element has a one-to-one correspondence between the sub-bit line including the memory cell selected based on the word line selection signal and the sub-bit line sharing the word line with the sub-bit line. Switch control to select,
The second switch element can perform switch control so that the main bit line that is made conductive to the common data line by the column switch circuit is made conductive to the sub-bit line.

(Operation)

According to the above-described means, a main bit line that is not made conductive with the common data line at the time of data reading can be controlled to be non-conductive with the sub-bit line. By being able to control the bit line to be non-conductive with the sub-bit line, the number of main bit lines that are an undesirable load for the sense amplifier is reduced overall, in other words,
The power consumption when the sense amplifier charges and discharges the main bit line is reduced as a whole of the semiconductor memory device, whereby the power consumption of the semiconductor memory device employing the main / sub bit line system is reduced.

〔Example〕

FIG. 3 shows a main / sub bit line system according to an embodiment of the present invention.
FIG. 1 is a block diagram showing the entire DRAM, FIG. 1 is a circuit diagram representatively showing a structure relating to a predetermined main bit line pair in the memory cell array shown in FIG. 3, and FIG. 2 is a circuit diagram showing a predetermined structure shown in FIG. FIG. 3 is a detailed circuit diagram related to a sub-bit line pair.

Although the DRAM of this embodiment is not particularly limited, it is formed on one semiconductor substrate by a known semiconductor integrated circuit manufacturing technique, and furthermore, as shown in FIG.
For MBLi, ▲ ▼, four sub-bit line pairs SBLi ₁ ,
It has a 4-mat configuration with ▲ ▼ to SBLi ₄ and ▲ ▼.

First, a DRAM according to the present embodiment will be schematically described with reference to FIG.

This DRAM has a memory cell array 1 in which a plurality of dynamic memory cells are arranged in a matrix. Although the memory cells are not particularly limited, they are coupled to the sub-bit line pairs laid out according to the folded data line system via data input / output terminals of equal number every other, and the selection terminal of each memory cell is Is coupled to the word line of the column corresponding to. The selection of a word line is performed by the row address decoder 2. The row address decoder 2 decodes an internal row address signal a ₀ , ▼ to ai, ▼ supplied from a row address buffer and an address latch 3 and drives a corresponding predetermined word line to a selected level. . Internal row address signal a ₀ , ▲ ▼ to ai, ▲ ▼
Are formed based on row address signals A _{0 to} Ai supplied from the outside.

One end of each sub-bit line pair is connected to a differential amplification type sense amplifier. When these sense amplifiers start operating, they detect a small potential difference between a pair of sub-bit lines and amplify it. Also, a bit line precharge circuit is provided for each sub-bit line pair for detecting a potential difference between the sub-bit line pairs with a sense amplifier and applying a determination level to each sub-bit line pair before amplifying the potential difference.

On the other hand, a desired one of the sub-bit line pairs is selectively conducted to the main bit line pair in units of four.
The main bit line pair is commonly connected to a common data line pair 7 via a column switch circuit 6. The column switch circuit 6 includes a column selection switch element for selectively making the main bit line pair conductive to the common data line pair 7, and these switch elements are controlled by a selection signal output from the column address decoder 8. Switch controlled. This column address decoder 8 receives internal column address signals aj, ▲ from a column address buffer and an address latch 9.
▼ to an, ▲ ▼ are supplied. These internal column address signals aj, ▼ to an, ▼ are formed based on externally supplied column address signals Aj to An.

The common data line pair 7 is coupled to a data input / output circuit 10 including a main amplifier, a data input buffer, and a data output buffer.

The timing controller 11 controls the internal timing of the entire DRAM. The timing controller 11 is supplied with ▲ (row address strobe), ▲ (column address strobe), and ▼ (write enable) signals as external control signals. The signals ▲ and ▼ are used as basic signals for setting the operation mode and for generating the internal timing. The signal ▲ is a signal instructing a read / write operation. The timing controller 11 forms various internal control signals for controlling the inside according to a predetermined procedure based on the external control signal. FIG. 3 shows a timing chart for activating the sense amplifier after the word line selection operation is determined. Sense amplifier signal φsa and ▲
A precharge signal φpc for instructing bit line precharge during a signal negation period is representatively shown.

In the DRAM of the present embodiment, the assertion period of the above-mentioned signal is an access cycle, and when the signal is asserted, the timing controller 11 controls the operation of each section according to its internal control procedure. That is, the row address signal A ₀ ~Ai and the row address buffer and address latch 3 column address signal Aj~An is in a predetermined order
And the column address buffer 9 and the address latch 9, and the fetched address signal is decoded by the row address decoder 2 and the column address decoder 8, and the memory cell corresponding to the input address signal becomes conductive to the common data line pair 7. Memory cell data is externally supplied from the data input / output circuit 10 or data supplied from the data input / output circuit 10 is written to the addressed memory cell in accordance with an operation instruction such as a memory read / memory write. It is.

Next, the configuration relating to a pair of main bit lines MBLi, ▲ ▼ will be described in detail with reference to FIGS. 1 and 2. FIG.

The main bit line pair MBLi, ▲ ▼ is not particularly limited, but is made of a metal such as metal silicide or aluminum.
▼ 4 sets of sub-bit lines SBLi ₁ , ▲ sharing
▼ to SBLi ₄ and ▲ ▼ are not particularly limited, but are made of polycrystalline silicon or silicide also serving as a selection terminal electrode of the memory cell. Although not particularly limited, the sub-bit lines SBLi ₁ , ▲ ▼ and SBLi ₂ , ▲
As shown in FIG. 1, ▼ is laid in two rows in a nested state, and similarly, the sub-bit line SBLi ₃ , ▲ ▼
And SBLi ₄ , ▲ ▼ are nested in two rows.

Main bit line pair MBLi, ▲ representatively shown in FIG.
▼ is coupled to the common data line CD, ▲ ▼ via an N-channel type column selection MOSFET Q2 which is switch-controlled by the output selection signal of the column address decoder 8. Sub-bit line pair SBLi ₁ , ▲ ▼ to SBLi ₄ , ▲
▼ indicates a one-transistor type memory cell in which an N-channel type selection MOSFET Q1 and a storage capacitor Cs are connected in series.
MCs are alternately coupled via their data input / output terminals.
Although the storage capacity Cs of each memory cell MC is not particularly limited, a voltage Vdd corresponding to half of one power supply voltage Vdd of the circuit is used.
/ 2 is given. Note that in FIG.
Indicated by marks.

In the present application, a plurality of memory cells connected to the pair of sub-bit lines is referred to as a memory block.

The selection terminal of each memory cell MC is coupled to a plurality of representatively shown word lines WLL and WLR for each column. Although the selection level of the word lines WLL and WLR is not particularly limited, the power supply voltage V
Bootstrap level is set to dd or higher.

Sub-bit line pair SBLi ₁ , ▲ ▼ to SBLi ₄ , ▲
▼ respectively show a precharge circuit (represented by PRC in FIG. 2) and sense amplifiers SAi _{1 to} SAi _4.
Is joined to.

Although the precharge circuit PRC is not particularly limited,
A pair of N-channel type equalizing MOSFETs Q11 and Q12 that leak and balance a pair of sub-bit lines by being turned on at a predetermined timing during a chip non-selection period, and via a coupling node of both MOSFETs Q11 and Q12 In order to compensate for a leak current, a precharge voltage Vdd / 2 can be supplied to each sub-bit line pair. Equalize MOSFET
Q11 and Q12 are switch-controlled by the precharge signal φpc, which is controlled to a high level during a chip non-selection period. The precharge circuit PRC precharges the bit line pair to a desired level for the operation before starting the memory access, and gives a judgment level Vdd / 2 when reading the memory cell data.

Sense amplifier SAi ₁ ~SAi ₄ is not particularly limited, as in the second diagram showing the details, a complementary MOS static structure composed of P-channel type sense amplifier portion SAp and N-channel sense amplifier section SAn Is done. The N-channel sense amplifier SAn couples the drain electrodes of N-channel MOSFETs Q3 and Q4, whose source electrodes are commonly connected, to a pair of sub-bit lines, and connects the gate electrode of the MOSFET Q3 to one sub-bit line, and the MOSFET Q4. Is cross-connected to the other sub-bit line. Similarly, P
The channel-type sense amplifier section SAp couples the drain electrodes of P-channel MOSFETs Q5 and Q6, whose source electrodes are commonly connected, to a pair of sub-bit lines, and connects the gate electrode of MOSFET Q5 to one sub-bit line and the gate of MOSFET Q6. An electrode is cross-connected to the other sub-bit line.

The common source electrodes of the P-channel sense amplifier SAp and the N-channel sense amplifier SAn are coupled to a power supply terminal Vdd via a P-channel MOSFET Q7 functioning as a constant current source. The common source electrode of SAn is coupled to the other power supply terminal Vss, such as the ground terminal of the circuit, via an N-channel MOSFET Q8 functioning as a constant current source. In addition, MOSFETQ7,
Q8 is the sense amplifier signal φsa are both turned on by being asserted to the high level, thereby respectively activate the sense amplifier SAi ₁ ~SAi _4. The activated sense amplifier differentially amplifies the sub-bit line pair so that the common source voltage of the P-channel type sense amplifier SAp and the N-channel type sense amplifier SAn is attained in accordance with the minute potential difference. .

Here, four pairs of sub-bit line pairs SBLi ₁ , ▲ ▼
SBSBLi ₄ , ▼▼ share one main bit line pair, and constitute 4 mats as a whole memory cell array.
Four sub-bit line pairs sharing one main bit line pair are commonly connected to the main bit line pair via the selection switch circuits 20, respectively. The selection switch circuit 20 is configured to selectively enable a desired sub-bit line pair in a desired main bit line pair to the main bit line pair. For example, a memory cell selected based on a word line selection signal In addition to the so-called mat selection function for selecting the sub bit line pair sharing the word line with the sub bit line pair including the sub bit line pair, the individual sub bit selected by the mat selection function, A function of controlling a line pair to be non-conductive with respect to the main bit line on a main bit line basis is provided.

In the selection switch circuit 20 of this embodiment, the mat selection function has four pairs of sub-bit line pairs SBLi ₁ ,
SBLi ₄ , ▲ ▼ to main bit line pair MBLi, ▲
N-channel first MOSFET Qf ₁ to enable conduction to ▼
Achieved by Qf ₄ . The first 1MOSFETQf ₁ ~Qf _4, as can select sub-bit line pair to which the memory cell to be addressed in the read / write operation is coupled, it is switch-controlled based on the address decode result.

The function of controlling each sub-bit line pair selected by the mat selection function to be non-conductive with respect to the main bit line in units of the main bit line is a function of each sub-bit line pair SBLi ₁ , ▲
▼ to SBLi ₄ , ▲ ▼ and main bit line pair MB
Between the _first MOSFET Qf _{1 to} Qf ₄
This is achieved by an N-channel type second MOSFET Qsi interposed in series with the second MOSFET. The second MOSFET Qsi is not particularly limited, but includes a main bit line pair MBLi, ▲ including the second MOSFET Qsi.
▼ represents the common data line CD,
The switch is controlled by the column selection signal output from the column address decoder in order to control the conduction in ▲ ▼.

Therefore, for example, based on an externally supplied address signal, the pair of sub-bit lines SBLi ₁ , ▲ in FIG.
When a predetermined memory cell coupled to ▼ is selected, the first MOSFET Qf ₁ and the second MOSFET Qs are controlled to be turned on, so that the memory cell is connected to the sub-bit line pair SBLi ₁ ,
From ▲, conduction is made to the common data line CD, ▼ via the main bit line pair MBLi, ▼▼. At this time, the main bit line pair MB included in the memory cell array 1
The second MOSFETs related to the main bit line pair (not shown) other than Li and ▲ ▼ are controlled to be off. Thereby, the sense amplifiers for each sub-bit line pair from which the memory cell data selected by the predetermined one word line driven to the selected level is read, that is, the sense amplifiers SAi ₁ in all the columns (not shown) including the sense amplifiers SAi ₁ are used. the sense amplifier in the selected memory mat there is a sense amplifier SAi ₁ except, amplifying operation i.e. substantially refresh without the load of the main bit line pair (not shown) corresponding to each for access target memory cell An amplification operation for the operation can be performed.

According to the above embodiment, the following effects can be obtained.

(1) All the main bit line pairs that are not made conductive to the common data line CD, ▲ ▼ during memory access can be controlled to be non-conductive to the sub-bit lines, so that at least the individual senses included in the selected memory mat The number of main bit lines that cause an undesired load on the amplifier is reduced overall, whereby the power consumption when the sense amplifier charges and discharges the main bit line can be reduced as a whole DRAM.

(2) In a refresh operation such as ras-only refresh for refreshing memory cells in word line units, all output selection signals of the column address decoder 8 are set to the non-selection level. As a result, during the refresh operation, all the second MOSFETs Qs are controlled to be turned off, so that the main bit line, which is an undesired load for each sense amplifier, is not conducted at all to the sub-bit line pair, and In operation, all power consumption when the sense amplifier charges and discharges the main bit line can be omitted.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited thereto, and can be variously modified without departing from the gist thereof.

For example, in the main / sub bit line structure of the above embodiment, two pairs of sub bit lines are laid in a nested state in two columns, respectively, so that the formation region of the sense amplifier can be effectively obtained. The present invention is not limited to this, and may be configured such that sets of each sub-bit line pair are laid in one column. Further, the sense amplifier may be of a shared sense type commonly used for two sets of sub-bit lines. Further, the number of sub-bit lines sharing the main bit line is not limited to four sets and can be determined as appropriate.

Further, the selection switch circuit 20 of the above embodiment is configured by connecting the first and second MOSFETs in series. However, when a circuit for specially generating a switch control signal for achieving the functions of both MOSFETs is provided, the selection It is also possible to replace a pair of switch elements with one switch element.

In the above description, the case where the invention made by the inventor is applied to a DRAM, which is a field of application as the background, has been mainly described. However, the present invention is not limited thereto, and a pseudo SRAM (static random An access memory, a virtual or virtual storage SRAM, a frame buffer memory, and the like can be widely applied to semiconductor storage devices of various dynamic formats, as well as semiconductor storage devices of various volatile and nonvolatile storage formats. The present invention can be applied to a device provided with a main / sub bit line system in which at least a plurality of sub bit lines coupled to memory cells are commonly connected to a main bit line via a selection switch circuit.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.

That is, the selection switch circuit that connects each of the plurality of sub-bit lines to the main bit line has a circuit configuration in which a desired sub-bit line in a desired main bit line is selectively made conductive to the main bit line. The main bit line that is not made conductive to the common data line during memory access can be controlled to be non-conductive to the sub-bit line, and as a result, the number of main bit lines that cause an undesired load on the sense amplifier can be reduced as a whole. Power consumption when the sense amplifier charges / discharges the main bit line can be reduced as a whole of the semiconductor memory device, whereby the power consumption of the semiconductor memory device employing the main / sub bit line method can be reduced. There is an effect that reduction of the amount can be achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a main / sub bit line type DR according to an embodiment of the present invention.
FIG. 2 is a circuit diagram representatively showing a configuration relating to a predetermined main bit line pair in AM, and FIG. 2 is a detailed circuit diagram relating to a predetermined sub-bit line pair shown in FIG. FIG. 3 is a block diagram showing the entire DRAM of the main / sub bit line system. 1 ... memory cell array, 2 ... row address decoder, 6 ... column switch circuit, 8 ... column address decoder, MBLi, ▲ ▼ ... main bit line pair, SBL
i ₁ , ▲ ▼ to SBLi ₄ , ▲ ▼… sub-bit line pair, WLL, WLR… word line, MC… memory cell, SAi
_{1 to} SAi ₄ Sense amplifier, 20 Selection switch circuit, Q
f _{1 to} Qf ₄ …… First MOSFET, Qsi …… Second MOSFET, CD, ▲
▼ …… Common data line.

Claims (1)

(57) [Claims] A plurality of memory cells having a selection terminal and a data input / output terminal; a plurality of word lines to which the selection terminals of the plurality of memory cells are respectively connected; and a data input / output terminal of the plurality of memory cells. A memory block including a plurality of sub-bit lines to which output terminals are connected; a plurality of main bit lines provided corresponding to a plurality of the memory blocks; and a plurality of the main bit lines and a plurality of the memory blocks, respectively. A first switch element and a second switch element connected in series between the sub-bit line and a common data line to which each of the plurality of main bit lines is connected via a column switch circuit; A precharge circuit provided for each of the sub-bit lines for pre-charging the sub-bit line to an operationally desirable level before the start of selection of a memory cell; A sense amplifier circuit for amplifying a signal of the sub-bit line after the selected memory cell is selected, wherein the first switch element includes a memory cell including a memory cell to be selected based on a word line selection signal. The second switch element is controlled to connect a sub-bit line to a main bit line, and the second switch element selects the main bit line connected to the common data line by the column switch circuit based on a bit line selection signal. A semiconductor memory device, which is controlled so as to be connected to a sub-bit line of the memory block including a memory cell to be included.