JPS632197A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the area of chips by arranging a one column of sense amplifiers respectively between blocks in the relation that one is operated while the other is not operated to reduce the number of sense amplifiers remarkably. CONSTITUTION:A memory cell array block corresponding to a row address RA8-0 and a memory cell array block corresponding to a row address RA8=1 are not selected at the same time. Then a sense amplifier SA is connected to bit lines BL'1 and the inverse of BL'1 via transistors (TRs) T1, T2 as a switch means and connected similarly to bit lines BL2 and the inverse of BL2 via TRs T3, T4 as a switch means. The ON/OFF of the TRs T1, T2 is controlled by the inverse of a signal phi8 and the ON/OFF of the TRs T3, T4 is controlled by the signal phi8. Thus, the split operation of the memory cell array is enabled and the number of sense amplifier arrays is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that performs a dividing operation of a memory cell array.

[Traditional technique 4! ] In recent years, with the progress of higher integration in highly integrated memory devices such as dynamic MO3-RAMs, lower power consumption has been desired. Dynamic type MO8-RA
In M, the charge/discharge current of the bit line occupies a large proportion of the total current consumption. Therefore, in each active cycle, only the memory cell array block associated with input address g is operated, and the others are not operated, reducing the bit line charging/discharging current to 1/2, 3/4, etc. (hereinafter referred to as memory cell array block g). (referred to as a splitting operation) is being performed. Fourth
This conventional example is shown in FIG.

Figure 4 shows, for example, 1M Pit Dynamic MO8-RA.
This shows the case of M, and the entire memory cell array is row 7.
It is divided as shown in the figure by address RA8 (8 represents the 8th bit of the address) and column address CA8.

Thus, for example, external row 7 address input RAS-0
In the case of , the block corresponding to RAS-1 (#2.#2
', #4. #41 does not need to operate, the sense amplifier drive signal (φS) is not activated for these, and the bit line is kept in a precharged state.

FIG. 5 is a circuit diagram showing in detail a part of the semiconductor memory device shown in FIG. 4. As shown in the figure, this semiconductor device GI includes a plurality of bit line pairs BL, BL.

...-, a plurality of words M WL arranged across this bit line pair, and ip! at the intersection of the bit line and the word line. A memory cell MC that is set to H, a sense amplifier SA that is arranged for each bit line pair and detects and amplifies the 7th bit line in response to a sense amplifier drive signal φS, and a column decoder output that is selected according to a column address. The gate transistors GT, GT for connecting the bit line pair BL, 8L to the data line pair 1, 10, 110 and the receiving precharge clock φpr short the bit line pair BL, BL to (1/2) Vcc. (Vcc is Wm voltage)
and 7') a precharge transistor for charging.

[Problems to be Solved by the Invention] In the conventional device as described above, as shown in FIG. 4, the area occupied by the sense amplifier array is large, which not only increases the chip size but also causes There is a problem in that the size increases and the burden on the package also increases.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device in which the number of sense amplifiers can be significantly reduced and the chip surface consumption can be reduced.

Means for Solving Problem L] A semiconductor memory device according to the present invention has a plurality of memory cell array blocks which operate in a divided manner, and which are adjacent to each other, and when one operates, the other does not operate. One column of sense amplifiers is arranged between certain blocks, and a switch means is inserted between the sense amplifiers and the memory cell array blocks.

[Operation] The switch means in the present invention connects the sense amplifier and one memory cell array block and the other memory cell array block.

iI! This allows two memory cell array blocks to share one column of sense amplifiers.

[Actual Example] FIG. 1 is a diagram showing the overall configuration of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a part of the semiconductor memory device shown in FIG. 1 in detail. As shown in FIG. 1, sense amplifiers (#1, #2, . . . ) are arranged in one column between each memory cell array block divided by row one node RA8. Here, the memory cell array block corresponding to O-address RA8-0 [5] and the memory cell array block corresponding to row address RA8-1 are not selected at the same time. Therefore, the sense amplifiers are arranged in one column between adjacent memory cell array blocks such that when one operates, the other does not operate. Specifically, as shown in FIG. 2, the sense amplifier SA (sense amplifier #2 is shown in FIG. 2) includes transistors T1. It is connected to the pit 11BL=1.8LM via T2, and the transistor T3. It is connected to bit line BL2.8L2 via T4. Transistors T1 and T2 are turned on and off by signal φ8, and transistors T3 and T
4 is turned on and off by signal φ8. These signals φ8. φ8 is a signal generated according to row address RAS-0, RAS-1. The other configuration of this embodiment is the same as the conventional device shown in FIGS. 4 and 5,
Corresponding parts are given the same reference numbers.

FIG. 3 is a timing chart showing the operation timing of the above embodiment. In FIG. 3, the solid line indicates the case of row address RAS-1, and the dotted line indicates the case of row address RAS-1.
- Indicates the case of 〇. The operation of the above embodiment will be explained below with reference to FIG.

In the case of row address RA 8-1, signal φB-゛1''
The sense amplifier SA (#2) is connected to the memory cell array block (#2), and the bit line pair 8m2. B
The potential of L2 is detected and amplified.

At this time, the sense amplifier S (#2) does not act at all on the pit line of the memory cell array block (#1i side. Therefore, the bit line pair BL-1, BL-8Ll maintains the precharged state. On the other hand, the row address In the case of RAS-0, this is the opposite, and the memory cell array block (9
The potential of the pit mW on the 11 side is sensed, and at this time, the sense amplifier SA (#2) is connected to the memory cell array block (#2).
2) side does not have the same effect. Therefore, in this embodiment, the memory cell array can be divided in the same manner as in the conventional devices shown in FIGS. 4 and 5.

As described above, in the above embodiment, one column of sense amplifiers is shared by two memory cell array blocks.
Not shown in FIG. 4 are sense amplifier rows #2 and #3. #4 and #5.
#6 and #7 can each be configured in one row, and the number of sense amplifier rows as a whole is reduced from eight rows to five rows, and the chip area can be reduced.

Note that in the above embodiment, the entire memory cell array is divided into four parts for each column decoder, but
The number of divisions may be any number.

Further, in the above embodiment, the entire memory cell array is divided into two according to the row address RA8-0.1.

Although the case of a 1/part division operation in which only one of these is made a is shown, this division number is the same in other cases such as 1/4, 3/4, etc.

C. Effects of the Invention] As described above, according to the present invention, the memory cell array can be divided and the number of sense amplifier rows can be reduced, so low power consumption and high integration are possible. A semiconductor memory device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the overall configuration of a semiconductor memory device of the present invention. FIG. 2 is a circuit diagram showing details of a portion of the semiconductor memory device shown in FIG. 1. FIG. 3 is a timing chart showing the operation timing of the embodiment shown in FIGS. 1 and 2. FIG. FIG. 4 is a diagram showing the overall configuration of a conventional semiconductor memory device. FIG. 5 is a circuit diagram showing details of a part of the conventional i-position shown in FIG. In the figure, WL is a word line, BL and BL are pit lines, SA is a sense amplifier, and 1 to T4 are transistors as switching means.

Claims (1)

[Scope of Claims] A memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the intersections of these word lines and bit lines, the memory cell array being divided into a plurality of blocks. In a semiconductor memory device that is divided into blocks and in which some of the blocks selectively operate in each active cycle, when one of the plurality of adjacent blocks operates, the other operates. Sense amplifiers are arranged between blocks that are in a non-operating relationship, and the sense amplifiers are arranged in one column between each of the blocks, and there is a connection between the sense amplifiers and one block and between the other block. A semiconductor memory device further comprising a switch means for connecting and disconnecting between the two.