JP2554640B2 - Semiconductor memory device - Google Patents

Description

Description: [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using both MOS technology and bipolar technology.

(Prior Art) MOS type semiconductor memory devices are remarkably miniaturized and highly integrated. In fields such as large computers that require high speed, 4K or 16K static RAM (sRA
M) is often used. However, if the gate length of the MOS transistor is reduced to about 0.5 μm, the external power supply must be lowered in order to secure the reliability of the element, and it is difficult to increase the speed only by reducing the size as before.
Therefore, in sRAM, the speed is increased by introducing a bipolar transistor, which has a larger current drive capability than the MOS transistor. Dynamic RAM (dRA
Similarly, in M), the speedup by introducing a bipolar transistor is considered.

For example, a circuit in which a bipolar transistor is introduced into a CMOS structure is called a BICMOS circuit. Such a BICMOS circuit is used for a differential amplifier, a word line driving circuit having a large load capacitance, an output stage of a clock circuit, and the like. In particular, in the case of a minute input signal, the bipolar transistor has a conductance about 10 times larger than that of the CMOS, and the differential amplifier can be operated at a high speed simply by swinging the input / output line having a large load capacitance very small.

However, introducing a bipolar transistor into a sense amplifier row or a word line drive circuit (a part called a core circuit together with the memory cell array) continuously arranged around the memory cell array has a big problem in relation to the pattern area and the degree of integration. . This is because the bipolar transistor is essentially unsuitable for high integration and has a large pattern area as compared with the MOS transistor. This will be described below with reference to the drawings.

FIG. 12 is a block diagram showing the overall structure of the dRAM. With respect to the memory cell array 11, a sense amplifier row 12, a Y decoder 13, and a column selection circuit 14 are arranged along the vertical cell arrangement, and an X decoder 15 and a word line drive circuit 16 are arranged along the horizontal cell arrangement. Has been done. Reference numeral 17 is an input circuit, and 18 is an output circuit.

FIG. 13 shows one sense amplifier SA in FIG. 12 and a part of a bit line pair BL, ▲ ▼ connected to it. MC
Is a memory cell, DC is a dummy cell, WL is a word line,
DWL indicates a dummy word line. As is well known, the memory cell MC and the dummy cell DC are composed of one MOS transistor and one capacitor, but recently
For high integration of dRAM, the area of one memory cell is becoming smaller and smaller by using a trench type capacitor structure. However, when the pitch width l of the sense amplifier SA is large, the core circuit pitch is determined by the pitch width l of this sensor amplifier SA, and therefore the vertical length L of the chip is also defined by the pitch width l of this sense amplifier SA. However, no matter how the size of the memory cell is reduced, the chip size cannot be reduced and the density cannot be increased. The same problem occurs when a bipolar transistor is introduced in the word line drive circuit.

(Problems to be solved by the invention) As described above, when a bipolar transistor is introduced into a circuit portion continuously arranged in a memory cell array such as a sense amplifier or a word line drive circuit, when a MOS transistor is used Since it requires a larger area than the above, there is a problem that it is not possible to achieve high density of memory and downsizing of chip size.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor memory device capable of high integration while introducing a bipolar transistor to achieve high speed operation.

[Structure of the Invention] (Means for Solving the Problems) According to the present invention, circuits such as a sense amplifier column and a word line drive circuit continuously arranged around a memory cell array are arranged in each selected row or column. A MOS transistor and a bipolar transistor, which are independently provided in the first circuit, and which are shared by a plurality of rows or columns and are connected to a selected row or column line through a switching circuit It is characterized by comprising a plurality of second circuits consisting of.

Particularly, in the first invention, the first circuit is a main sense amplifier provided for each bit line pair, and the second circuit is a pre-sense sense amplifier shared by a plurality of bit line pairs. To do. Further, in the second invention, the first circuit is a decoder driver provided for each word line, and the second circuit is a decoder driver output stage shared by a plurality of word line pairs. And

(Operation) In the present invention, since the second circuit including the bipolar transistor capable of high-speed operation is arranged so as to be shared by a plurality of bit line pairs or a plurality of word lines, the core circuit pitch is set to be smaller than the pitch of the second circuit. The pitch can be small, for example, the minimum pitch determined by the cell size.

Specifically, when the present invention is applied to a sense amplifier system, a CMOS-based main sense sense amplifier is provided for each bit line pair as a first circuit, and a BICMOS-configured presense sense amplifier is provided as a second circuit. One amplifier is provided for each of a plurality of bit line pairs. If you do this,
The core circuit pitch is not determined by the BICMO circuit, but can be determined by the cell size. Moreover, it is possible to prevent the memory chip size from increasing as compared with the case where a BICMOS circuit having a large area is provided for each bit line pair.

If the present invention is applied to the word line drive circuit side, the same operation can be achieved by configuring one driver output stage (second circuit) to be shared by a plurality of decoder driver circuits (first circuit). Is obtained.

(Example) Hereinafter, the Example of this invention is described.

FIG. 1 shows the configuration of the sense amplifier section of the embodiment applied to the dRAM. CMOS sense amplifiers 1 ₁ and 1 ₂ (first circuit) are
It is provided for each individual bit line pair for main sense and rewriting. BICMOS sense amplifier 2 (second circuit) includes two bit line pairs BL ₁ , ▲ ▼ and BL ₂ , ▲
It is for presense shared by ▼. BICMOS sense amplifier 2 and two bit line pairs BL ₁ , ▲ ▼ and BL ₂ ,
▲ ▼ switching between the complementary signal phi _x determined by the X address _is performed by the transfer gate MOS transistor Q ₁₁ to Q _14, which is controlled by phi _{x '.} For the CMOS sense amplifiers 1 ₁ and 1 ₂ , clocks φ ₂ and φ having different rising speeds depending on which of the two bit line pairs is selected.
₂ 'is input. The same configuration is repeatedly arranged in the vertical direction to form a core circuit.

FIG. 2 shows a concrete configuration example of the CMOS sense amplifiers 1 ₁ and 1 ₂ . This CMOS sense amplifier includes n-channel MOS transistors Q ₂₁ , Q ₂₂ and p-channel MOS transistors Q ₂₃ ,
Flip-flops consisting of Q ₂₄ , inverter INV ₁ for clocking these flip-flops in a complementary manner
And n for short-circuiting the bit line pair BL, ▲ ▼
It is composed of channel MOS transistors Q _{25 to} Q ₂₇ .

FIG. 3 shows a concrete configuration example of the BICMOS sense amplifier 2. This sense amplifier is a bipolar transistor T ₁₁ , T
_It mainly consists of a differential amplifier composed of ₁₂ , T ₂₁ , and T ₂₂ and a current source MOS transistor Q ₃₂₇ . The collectors of the driver transistors T ₁₂ and T ₂₂ are connected to the output line O, respectively. The bases of the driver transistors T ₁₂ and T ₂₂ are MO controlled by the read clock φ _R , respectively.
S transistor Q _314, Q ₃₂₄ and the column selection signal CSL by being controlled MOS transistor Q _315, via the Q ₃₂₅ bit lines BL, ▲ connected thereto to ▼, also controlled by the write clock phi _w MOS transistor Q ₃₁₆ , Q ₃₂₆ to input line I ,. Bit line BL, ▲
The changeover switch circuit is provided between the ▼ and the BICMOS sense amplifier as described above, and the BICMOS sense amplifier is shared by a plurality of pairs of bit lines. Q ₃₁₂ ,
Q ₃₁₃ , Q ₃₂₂ , and Q ₃₂₃ are MOS transistors for precharging the bases of the transistors T ₁₂ and T ₂₂ .

Next, the operation of the sense amplifier section of FIG. 1 according to this embodiment will be described with reference to FIG. Bit line is (1/2) V _cc
Take the case of the method of pre-charging as an example. First, the pair of selected bit lines is connected to the pre-sense BICMOS sense amplifier 2 by complementary signals φ _x and φ _x ′ determined by the X address.
For example, when the signal φ _x becomes “H” level and φ _x ′ becomes “L” level, the bit line pair BL ₁ , ▲ ▼ is selected and connected to the BICMOS sense amplifier 2. After that, the selected word line WL and the dummy word line DWL are driven to read the cell information to the bit line pair. Then, the clock φ ₁ is input to activate the BICMOS sense amplifier 2. As a result, the potential difference between the selected bit lines BL ₁ and ▲ ▼ is amplified to a value that can be amplified by the CMOS sense amplifier. And the CMOS sense amplifier 1 connected to the selected bit line BL ₁ , ▲ ▼
_A high-speed rising clock φ ₂ is input to ₁ and, thereby, the selected bit line BL ₁ and ▲ ▼ can be connected to the I / O line. The unselected bit line pair BL ₂ , ▲ ▼ has a slow rising clock φ ₂ ′ because cell information is rewritten.
To operate. The operation of this clock φ ₂ ′ is not necessarily required to be particularly slow, but it is useful for sure rewriting with the CMOS sense amplifier even when the cell information amount is small, and the bit line discharge peak. It is also advantageous in that self-generated noise can be reduced by shifting the waveform of the discharge current and making the waveform of the discharge current dull. This effect is obtained by adopting the configuration of the present invention. Bit line pair BL ₂ , ▲
When ▼ is selected, the relationship between the clocks φ ₂ and φ ₂ ′ is reversed.

According to this embodiment, as is clear from FIG. 1, BICM
Arrangement of two pairs of bit lines within the pitch of the OS sense amplifier 2 is allowed, and high integration of the dRAM can be achieved by reducing the memory cell size. Moreover, since BICMOS sense amplifiers that require a large area are only one in two pairs of bit lines, BICM
It is possible to prevent an increase in chip size due to using the OS sense amplifier. Moreover, compared with the case where only CMOS sense amplifier is used, high-speed operation of dRAM is possible by using BICMOS sense amplifier together.

5 and 6 are modified examples of BICMOS sense amplifiers. Although the basic structure is the same as that in FIG. 3, the difference from FIG. 3 will be explained. In FIG. 5, the bit line BL, ▲
Capacitors D ₁ and D _{2 are} provided to cut between ▼ and the input line I and the bases of the transistors T ₁₂ and T ₂₂ in terms of direct current. FIG. 6 also shows the column selection signal CSL, ▲ in order to cut the direct current between the bit line BL, ▲ ▼ and the input line I, and the bases of the transistors T ₁₂ , T _22.
A clocked CMOS inverter controlled by ▼ is used.

FIG. 7 shows the main structure of the sense amplifier section of the dRAM of another embodiment, corresponding to FIG. The difference from FIG. 1 is that two CMOS sense amplifiers 1 ₁ and 1 ₂ are arranged side by side in the horizontal direction, that is, the bit line direction.

Such a configuration is used for memory cell MC and dummy cell DC.
Is further miniaturized, and the bit line pair BL, ▲ ▼ can be arranged at a very narrow interval, which is effective when the pitch of the CMOS sense amplifier does not fit within this bit line pair pitch. That is, according to this embodiment, the number of bits versus the pitch can be set narrow to a value determined by the memory cell structure regardless of the pitch of the CMOS sense amplifier, and the CMOS can be set in a range of twice the bit line pair pitch. Since the sense amplifier can be configured, the wiring of the CMOS sense amplifier becomes easy.

FIG. 8 shows the configuration of an embodiment in which the present invention is applied to the word line drive circuit side of a dRAM. 3 ₁ to 3 ₄ shown are word line decoder driver (first circuit), corresponding to the word lines WL ₁ to WL ₄ each present 4. 4 is a driver output stage (second circuit) shared by these decoders and drivers 3 _{1 to} 3 ₄
Is. The output stage 4 outputs the signal φ ₁ determined by the X address.
Is connected to only one word line selected by the MOS transistors Q _{81 to} Q ₈₄ controlled by ˜φ ₄ .

Figure 9 is a CMOS driver specific configuration of the decoder driver 3 ₁ to 3 _4, Fig. 10 is a BICMOS circuit of a specific configuration example of a driver output stage 4. Since these configurations are known, detailed description will be omitted.

FIG. 11 is a waveform diagram showing the operation of word line selection in this embodiment. When the signal φ ₁ is set to the “H” level by the X address and the other signals φ _{2 to} φ ₄ are set to the “L” level, only _one word line WL ₁ among the _four word lines WL _{1 to} WL ₄ is It is selected and connected to the driver output stage 4. And the decoder
The word line WL ₁ selected by the driver 3 ₁ is driven by the shared BICMOS output stage 4.

According to this embodiment, high density can be achieved in the bit line direction. The reason is the same as in the case of the above-described embodiment applied to the sense amplifier system. Moreover, since the output stage has a BICMOS configuration, high speed operation is ensured.

Although the dRAM has been described in the above embodiment, the present invention is applicable not only to sRAM but also programmable ROM when a BICMOS circuit is introduced into a circuit portion continuously arranged in a memory cell array to increase the speed. It is useful to apply.

[Effects of the Invention] As described above, according to the present invention, when a BICMOS circuit is introduced into a sense amplifier system, a word line drive circuit or the like, it is shared by a plurality of bit line pairs or a plurality of word lines. Thus, the circuit pitch is not limited by the BICMOS circuit, and can be set to a minute pitch determined by the memory cell size, for example. This allows BICM
Highly integrated and high-speed memory can be achieved without increasing the area of the memory chip due to the introduction of the OS circuit. Further, even a minute cell read signal can be surely read, and self-generated noise at the time of bit line discharge can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a sense amplifier section in a dRAM according to an embodiment of the present invention, FIG. 2 is a diagram showing a configuration example of the CMOS sense amplifier, and FIG. 3 is a configuration example of a BICMOS sense amplifier. 4 and 5 are signal waveform diagrams for explaining the operation of the sense amplifier section of this embodiment, FIGS. 5 and 6 are diagrams showing a modified example of the BICMOS sense amplifier, and FIG. 7 is another embodiment. FIG. 8 is a diagram showing the configuration of the sense amplifier section of the dRAM, FIG. 8 is a diagram showing the configuration of the word line drive circuit section of the dRAM of yet another embodiment, and FIG. 9 is a diagram showing an example of the configuration of its CMOS decoder driver. , FIG. 10 is a diagram showing an example of the configuration of the BICMOS driver output stage, FIG. 11 is a signal waveform diagram for explaining the operation of the word line drive circuit section, and FIG. 12 is a diagram showing the overall configuration of the dRAM. FIG. 13 is a diagram showing a conventional configuration example of the bit line sense amplifier section. 1 ₁ , 1 ₂ ...... CMOS sense amplifier (first circuit), 2 ...... BI
CMOS sense amplifier (second circuit), BL ₁ , ▲ ▼, B
L ₂ , ▲ ▼ …… Bit line, WL …… Word line, DWL…
... Dummy word line, MC ... dRAM memory cell, DC ... dummy cell, Q _{11 to} Q ₁₄ ... MOS transistor (switching circuit), 3 _{1 to} 3 ₄ ... CMOS word line decoder driver (first circuit) 4 ... BICMOS driver output stage (second circuit).

Claims (5)

(57) [Claims] 1. A semiconductor memory device having a plurality of memory cells arranged in a matrix on a semiconductor substrate, wherein a sense amplifier circuit arranged around a memory cell array is provided for each bit line pair, a MOS transistor. A pre-sense sense amplifier composed of a MOS transistor and a bipolar transistor shared by a plurality of bit line pairs and connected to a selected bit line through a switching circuit A semiconductor memory device comprising: 2. The semiconductor memory device according to claim 1, wherein the memory cell is a dRAM cell. 3. The semiconductor memory according to claim 1, wherein the activation of the non-selected bit line pair of the main sense sense amplifier is delayed with respect to the activation of the selected bit line. apparatus. 4. A semiconductor memory device having a plurality of memory cells arranged in a matrix on a semiconductor substrate, wherein a word line drive circuit arranged around the memory cell array is provided for each word line, a MOS transistor. And a decoder / driver output stage composed of a MOS transistor and a bipolar transistor, which is shared by a plurality of word lines and is connected to a selected word line through a switching circuit. A semiconductor memory device comprising: 5. The semiconductor memory device according to claim 4, wherein said memory cell is a dRAM cell.